JP2003163276A - Semiconductor device, electrooptical device, electronic apparatus, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a high breakdown voltage MIS unit can be formed at low temperatures, an electrooptical device using the semiconductor device as an active matrix substrate, an electric apparatus using the electrooptical device, and a method of manufacturing the semiconductor device. <P>SOLUTION: In a TFT 400 formed in a semiconductor device 300A, a insulation layer 330 comprises a tantalum oxide film 331 that is formed by oxidizing a tantalum film at the temperature of 300-400°C and under the pressure of 0.5-2 MPa, and a silicon oxide film 332 formed by a method such as CVD or the like. In this way, the insulation layer 330 contains the tantalum oxide film 331 which is generated by high pressure anneal processing, and it has a high breakdown voltage. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a MIS (Meta).
l-Insulator-Semiconductor)
The present invention relates to a semiconductor device including a semiconductor device, an electro-optical device using the semiconductor device as an active matrix substrate, an electronic apparatus using the electro-optical device, and a method for manufacturing the semiconductor device. More specifically, MIS
The present invention relates to a technique for forming an insulating layer used in the MIS portion of the semiconductor device.

[0002]

2. Description of the Related Art Among various semiconductor elements, MIS type diodes and thin film transistors are provided with a MIS portion composed of a metal layer, an insulating layer, and a semiconductor layer. The insulating layer is conventionally a silicon film as a semiconductor layer. It is said that the silicon oxide film obtained by thermally oxidizing the surface of the above under the condition of the temperature of about 1000 ° C. to about 1300 ° C. has a high breakdown voltage.

[0003]

[Problems to be Solved by the Invention] However, 100
The method of forming an insulating film at a high temperature exceeding 0 ° C. has a problem that an inexpensive substrate such as glass cannot be used as a substrate. If aluminum wiring or the like is formed on the substrate, 1000
Since a treatment temperature exceeding 0 ° C. exceeds the heat resistance of the aluminum wiring, there is a problem that the aluminum wiring cannot be formed when performing the treatment at such a high temperature.

In view of the above problems, the object of the present invention is to
A semiconductor device capable of forming a MIS portion having a high breakdown voltage at a relatively low temperature, an electro-optical device using the semiconductor device as an active matrix substrate, an electronic apparatus using the electro-optical device, and a method for manufacturing a semiconductor device. To provide.

[0005]

In order to solve the above problems, the present invention provides a semiconductor device in which a MIS type semiconductor element having a MIS portion composed of a metal layer, an insulating layer, and a semiconductor layer is formed on a substrate. The insulating layer includes an oxide film formed by oxidizing a metal film for forming an insulating layer by a high pressure annealing process in which the insulating layer is annealed under a high pressure in an atmosphere containing water vapor. .

Further, according to the present invention, in a method of manufacturing a semiconductor device in which a MIS type semiconductor element having a MIS portion including a metal layer, an insulating layer, and a semiconductor layer is formed on a substrate, a metal film for forming an insulating layer is formed. After forming, the insulating layer forming metal film is oxidized by a high pressure annealing process of annealing under high pressure in an atmosphere containing water vapor to form an oxide film, and the oxide film is used as a part of the insulating layer. Characterize.

Here, in the high pressure annealing treatment, for example, the temperature is 300 ° C. to 400 ° C. and the pressure is 0.5 MPa to.
The condition is 2 MPa.

According to the present invention, the insulating layer of the MIS portion contains the tantalum oxide film produced by the high-pressure annealing treatment, so that the withstand voltage of the insulating layer is high. Moreover, since the temperature of the high-pressure annealing treatment is sufficient to be 300 ° C. to 400 ° C., there is no problem even when a glass substrate is used as the substrate. Also,
Even when the aluminum wiring is formed when performing the high-voltage annealing treatment, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed on the substrate surface.

In the present invention, it is preferable that after the high-pressure annealing treatment, the annealing treatment is performed under normal pressure or reduced pressure.

Here, the insulating layer forming metal film is, for example, tantalum (Ta) or a tantalum alloy.

In the present invention, the insulating layer is, for example,
The metal layer side is provided with an oxide film formed of the insulating layer forming metal film, and the semiconductor layer side is provided with an insulating film formed of a semiconductor material having the same composition as the semiconductor layer. That is, when the semiconductor layer is made of silicon, the insulating layer has an insulating film such as a silicon oxide film or a silicon nitride film on the semiconductor layer side.

In the present invention, with respect to the metal layer,
At least the side in contact with the insulating layer may be made of the same metal material as the insulating layer forming metal film or may be made of a different metal material from the insulating layer forming metal film.

In the semiconductor device having such a structure, only the surface of the insulating layer forming metal film is oxidized in the high pressure annealing treatment to generate the oxide film, and the oxide film is used as a part of the insulating layer. A method of using the remaining insulating layer forming metal film as the metal layer or a part of the metal layer, or in the high-pressure annealing treatment, oxidizing the entire insulating layer forming metal film to form the oxide film, It can be manufactured by a method of using the oxide film as a part of the insulating layer.

In the present invention, on the substrate, the metal layer, the insulating layer, and the semiconductor layer are formed in this order from the lower layer side to the upper layer side, or from the lower layer side to the upper layer side. On the other hand, the semiconductor layer, the insulating layer, and the metal layer may be formed in this order.

A semiconductor device having such a structure is, for example,
After forming the metal layer on the lower side of the insulating layer forming metal film and performing the high pressure annealing treatment on the insulating layer forming metal film, the upper side of the oxide film of the insulating layer forming metal film. An insulating film formed of the same semiconductor material as the semiconductor layer, and a method of forming the semiconductor layer in this order, or the semiconductor layer below the insulating layer-forming metal film, and the semiconductor. After forming an insulating film formed of the same semiconductor material as the layer and performing the high-pressure annealing treatment on the insulating layer forming metal film, the insulating film is formed on the upper side of the oxide film of the insulating layer forming metal film. It can be manufactured by a method of forming a metal layer.

In the present invention, the MIS type semiconductor element is, for example, a thin film transistor.

If a semiconductor substrate is used as the substrate, the MIS type semiconductor element is not limited to a thin film transistor, but a bulk type MIS type transistor can be formed. That is, a semiconductor substrate is used as the substrate, an insulating film formed of the same semiconductor material as the semiconductor substrate is formed on the upper surface of the semiconductor substrate, and then the insulating layer forming metal film is formed to form the insulating layer. After the high-pressure annealing process is performed on the metal film for use as an insulating layer, the metal layer is formed on the upper side of the oxide film of the metal film for forming the insulating layer.

Further, in the present invention, a MIS type diode can be configured as the MIS type semiconductor element.

In the present invention, a capacitor element is formed on the substrate, in which at least an oxide film of the insulating layer forming metal film is used as a dielectric film and the metal layer is used as one electrode. You may.

Such a semiconductor device can be configured as an active matrix substrate used for an electro-optical device such as an active matrix type liquid crystal device. In this case, the thin film transistor is used as a non-linear element for pixel switching on the substrate. Further, according to the present invention, on the active matrix substrate, at least an oxide film of the same oxide film as the insulating layer forming metal film is used as a dielectric film, and a storage capacitor using the metal layer as one electrode is provided. It is preferably formed.

The electro-optical device according to the present invention can be used as a display unit of electronic equipment such as a mobile phone and a mobile computer. Further, the electro-optical device according to the invention can be used as a light valve of a projection type display device (electronic device).

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described with reference to the drawings. In the following description, first, as a semiconductor device including the MIS type semiconductor element to which the present invention is applied, the configurations of the TFT and the MIS type diode and the manufacturing method thereof will be described as the first, second, third, and fourth embodiments. After description, an example in which the present invention is applied to an active matrix substrate of a liquid crystal device will be described.

[First Embodiment] FIG. 1A shows a MIS included in a semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view schematically showing the configuration of the shaped semiconductor element.

In FIG. 1A, in a semiconductor device 300A according to the first embodiment, a gate electrode formed of a metal layer 320 as a gate electrode, an insulating layer 330 as a gate insulating layer, and an active layer are provided on a substrate 310. And a semiconductor layer 340 including a semiconductor layer 340 made of an intrinsic silicon film in this order and a semiconductor layer made of a metal layer 320, an insulating layer 330, and an N-type impurity-doped silicon film 350. MI formed in this order
An MIS type diode 500 having an S portion is formed. In the semiconductor device 300A of this embodiment, the substrate 3
A lower electrode made of a metal layer 320, an insulating layer 33
Silicon film 35 doped with 0 and N-type impurities
A capacitor 60 in which an upper electrode of 0 is formed in this order
0 is also formed.

Here, all of the metal layers 320 are entirely made of a tantalum film, and all of the insulating layers 330 are formed by oxidizing the surface of the tantalum film 33.
1 and a silicon oxide film 332 formed by a method such as CVD. Therefore, the insulating layer 330
Has a tantalum oxide film 331 on the metal layer 320 side and a silicon oxide film 332 on the silicon film 350 side.

In manufacturing the semiconductor device 300A having such a structure, after forming a tantalum film (metal film for forming an insulating layer) on the substrate 310, the surface of the tantalum film is exposed to an atmosphere containing water vapor. High-pressure annealing is performed to anneal under high pressure at. Here, the conditions of the high-pressure annealing treatment are, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa to 2 MPa. As a result, only the surface of the tantalum film is oxidized to form the tantalum oxide film 331. Therefore, this tantalum oxide film 331 is used as a part of the insulating layer 330, and the remaining tantalum film is used as the metal layer 320.

Next, a silicon oxide film 332 is formed on the surface side of the tantalum oxide film 331 by the CVD method or the like, and an insulating layer 330 composed of the tantalum oxide film 331 and the silicon oxide film 332 is formed.

Next, the insulating layer 33 is provided on the TFT 400 side.
An intrinsic silicon film 360 is formed on the surface of 0. At this time, the MIS diode 500 and the capacitor 60
No intrinsic silicon film is formed on the 0 side.

Next, a silicon film 350 doped with N-type impurities is formed on the TFT 400, the MIS diode 500, and the capacitor 600, respectively, to complete the MIS diode 500 and the capacitor 600. .

The silicon oxide film 332 may not be formed on the MIS diode 500 and the capacitor 600.

On the other hand, the TFT 400 is completed by forming a source electrode 360 and a drain electrode 370 which are respectively connected to the silicon film 350 doped with N-type impurities on the TFT 400 side.

In the semiconductor device 300 having the above structure, the insulating layer 330 includes the tantalum oxide film 331 produced by the high-pressure annealing process.
The breakdown voltage of 0 is high. Moreover, the temperature of the high-pressure annealing treatment is
Since the temperature is 300 ° C. to 400 ° C., there is no problem even if a glass substrate is used as the substrate 310, for example. Further, even when the aluminum wiring is formed during the high-pressure annealing treatment, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed on the substrate surface.

After the high-pressure annealing process, if the annealing process is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, water is removed from the tantalum oxide film 331, so the tantalum oxide film 331. Withstand voltage is further improved.

[Second Embodiment] FIG. 1B shows a MIS included in a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view schematically showing the configuration of the shaped semiconductor element.

In FIG. 1B, also in the semiconductor device 300B according to the second embodiment, as in the first embodiment, the gate electrode formed of the metal layer 320 as the gate electrode and the gate insulating layer are formed on the substrate 310. Insulating layer 330 and semiconductor layer 3 made of an intrinsic silicon film as an active layer
A TFT 40 having an MIS portion 40 formed in this order
0, a metal layer 320, an insulating layer 330, and a MIS diode 500 including a MIS portion in which a semiconductor layer including a silicon film 350 doped with N-type impurities is formed in this order. Also in the semiconductor device 300B of the present embodiment, the capacitor in which the lower electrode made of the metal layer 320, the insulating layer 330, and the upper electrode made of the silicon film 350 doped with N-type impurities are formed in this order on the substrate 310. 600 is also formed.

In this embodiment, the metal layer 320 has a metal film other than tantalum on the lower layer side, for example, the aluminum film 32.
1 and. The tantalum film 322 is formed so as to cover the aluminum film 321.

The insulating layers 330 are all tantalum oxide films 331 formed by oxidizing the surface of the tantalum film 322.
And a silicon oxide film 332 formed by a method such as CVD.

In manufacturing the semiconductor device 300B having such a structure, the aluminum film 3 is formed on the substrate 310.
After 21 and a tantalum film (metal film for forming an insulating layer) are formed in this order, the surface of this tantalum film is subjected to a high-pressure annealing treatment in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the conditions of the high pressure annealing treatment are, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa to.
It is 2 MPa. As a result, only the surface of the tantalum film is oxidized to form the tantalum oxide film 331. Therefore, this tantalum oxide film 331 is used as a part of the insulating layer 330, and the remaining tantalum film 322 is formed on the upper side of the metal layer 320. To use.

Since the subsequent steps are similar to those of the first embodiment, a detailed description thereof will be omitted. However, a silicon oxide film 332 is formed on the surface side of the tantalum oxide film 331, and the tantalum oxide film 331 and the silicon oxide film 332 are formed. Insulating layer 330
To form. Next, the insulating layer 33 is provided on the TFT 400 side.
After forming an intrinsic silicon film 360 on the surface of 0, TF
For example, if a silicon film 350 doped with N-type impurities is formed on the T400, the MIS diode 500, and the capacitor 600 side, respectively,
The shaped diode 500 and the capacitor 600 are completed. Further, on the TFT 300 side, a source electrode 360 and a drain electrode 3 which are respectively connected to the silicon film 350.
After forming 70, the TFT 300 is completed.

Also in the semiconductor device 300B thus configured, the insulating layer 330 includes the tantalum oxide film 331 produced by the high-pressure annealing process, so that the insulating layer 330 is formed.
The same effect as that of the first embodiment such as high withstand voltage is obtained. In addition, in this embodiment mode, the metal layer 320 includes the aluminum film 321 having a small electric resistance and the tantalum film 322.
Since it has a two-layer structure, the electric resistance of the metal layer 320 is small. Moreover, the temperature of the high-pressure annealing treatment for forming the insulating layer 330 having a high breakdown voltage is 300 ° C. to 400 ° C.
Since the temperature is in degrees Celsius, there is no problem even if a glass substrate is used as the substrate 310. Further, even when the aluminum film 321 is formed during the high-pressure annealing treatment, under such temperature conditions, the aluminum film 321 is not deteriorated unless the aluminum film 321 is exposed on the substrate surface. .

Also in this embodiment, after the high-pressure annealing treatment, the temperature is 200 ° C. to 5 ° C. under normal pressure or reduced pressure.
If the annealing treatment at 00 ° C. is performed, the tantalum oxide film 331
Since moisture is removed from the tantalum oxide film 331, the breakdown voltage of the tantalum oxide film 331 is further improved.

[Third Embodiment] FIG. 1C shows a MIS included in a semiconductor device according to a third embodiment of the present invention.
FIG. 3 is a cross-sectional view schematically showing the configuration of the shaped semiconductor element.

In FIG. 1C, also in the semiconductor device 300C according to the third embodiment, as in the first embodiment, the gate electrode formed of the metal layer 320 as the gate electrode and the gate insulating layer are formed on the substrate 310. Insulating layer 330 and semiconductor layer 3 made of an intrinsic silicon film as an active layer
A TFT 40 having an MIS portion 40 formed in this order
0, a metal layer 320, an insulating layer 330, and a MIS diode 500 including a MIS portion in which a semiconductor layer including a silicon film 350 doped with N-type impurities is formed in this order. Also in the semiconductor device 300C of the present embodiment, a capacitor in which the lower electrode made of the metal layer 320, the insulating layer 330, and the upper electrode made of the silicon film 350 doped with N-type impurities are formed in this order on the substrate 310. 600 is also formed.

Also in this embodiment, the insulating layer 330 is the tantalum oxide film 3 formed by oxidizing the surface of the tantalum film 332.
31 and a silicon oxide film 332 formed by a method such as CVD.

Here, unlike the first embodiment, each of the metal layers 320 is made of an aluminum film.

In manufacturing the semiconductor device 300C having such a structure, the metal layer 320 made of an aluminum film is formed on the substrate 310, and then the tantalum film (metal film for forming an insulating layer) is formed.

Next, a high pressure annealing process is performed to anneal the entire tantalum film under high pressure in an atmosphere containing water vapor.
Here, the condition of the high-pressure annealing treatment is, for example, that the temperature is 3
The temperature is 00 ° C to 400 ° C and the pressure is 0.5 MPa to 2 MPa. As a result, the entire tantalum film is oxidized to form the tantalum oxide film 331.
1 is used as a part of the insulating layer 330.

Since the subsequent steps are the same as those in the first embodiment, detailed description thereof will be omitted. However, a silicon oxide film 332 is formed on the surface side of the tantalum oxide film 331, and the tantalum oxide film 331 and the silicon oxide film 332 are formed. Insulating layer 330
To form. Next, the insulating layer 33 is provided on the TFT 400 side.
After forming an intrinsic silicon film 360 on the surface of 0, TF
For example, if a silicon film 350 doped with N-type impurities is formed on the T400, the MIS diode 500, and the capacitor 600 side, respectively,
The shaped diode 500 and the capacitor 600 are completed. Further, on the TFT 300 side, a source electrode 360 and a drain electrode 3 which are respectively connected to the silicon film 350.
After forming 70, the TFT 300 is completed.

Even in the semiconductor device 300C having the above structure, the insulating layer 330 includes the tantalum oxide film 331 produced by the high-pressure annealing process.
The same effect as that of the first embodiment such as high withstand voltage is obtained. In addition, in the present embodiment, the metal layer 320 is formed of an aluminum film having a low electric resistance, and thus the metal layer 320 has a low electric resistance. Moreover, since the temperature of the high-pressure annealing process for forming the insulating layer 330 having a high breakdown voltage is 300 ° C. to 400 ° C., for example, the substrate 31
Even if a glass substrate is used as 0, there is no problem. Further, even when the metal layer 320 made of an aluminum film is formed when performing the high-pressure annealing treatment, the metal layer 320 made of the aluminum film is under such temperature conditions even if it is formed.
Is covered with the tantalum film and is not exposed on the substrate surface, so that the metal layer 320 is not deteriorated by water vapor.

Also in this embodiment, after the high-pressure annealing treatment, the temperature is 200 ° C. to 5 ° C. under normal pressure or reduced pressure.
If the annealing treatment at 00 ° C. is performed, the tantalum oxide film 331
Since moisture is removed from the tantalum oxide film 331, the breakdown voltage of the tantalum oxide film 331 is further improved.

[Fourth Embodiment] FIG. 1D shows a MIS included in a semiconductor device according to a fourth embodiment of the present invention.
FIG. 3 is a cross-sectional view schematically showing the configuration of the shaped semiconductor element.

Although the TFTs shown in the above-mentioned modes 1, 2 and 3 are of the inverted stagger type in which the gate electrode is located on the lower layer side of the active layer, the gate electrode is formed on the upper layer side of the active layer as described below. The present invention may be applied to a semiconductor device provided with a positive staggered type TFT.

In FIG. 1D, in a semiconductor device 300D according to the fourth embodiment, on a substrate 310, a semiconductor layer 340 made of an intrinsic silicon film as an active layer, an insulating layer 330 as a gate insulating layer, and A TFT 400 having a MIS portion in which a metal layer 320 as a gate electrode is formed in this order, a semiconductor layer 380 made of a silicon film doped with N-type impurities, an insulating layer 330, and a metal layer 320 are formed in this order. MIS with a MIS section
And the diode 500 is formed. In the semiconductor device 300D of the present embodiment, the lower electrode (semiconductor layer 380) made of a silicon film doped with N-type impurities, the insulating layer 330, and the upper electrode made of the metal layer 320 are provided on the substrate 310 in this order. The formed capacitor 600 is also formed.

Here, the metal layers 320 are all made of various metals such as a tantalum film, a chromium film, and an aluminum film, and the insulating layers 330 are all tantalum films formed by oxidizing the tantalum film as described later. An oxide film 331,
Silicon oxide film 33 formed by a method such as CVD
2 and.

In the semiconductor device 300D of this embodiment, in the semiconductor layer 340, a portion facing the metal layer 320 as a gate electrode with the insulating layer 330 interposed therebetween is a channel formation region 343 made of an intrinsic silicon film. A source region 341 in which N-type impurities are doped on both sides in a self-aligned manner with respect to the metal layer 320 (gate electrode),
And a drain region 342. Further, with respect to the source region 341 and the drain region 342, the source electrode 3 is provided through a contact hole of the interlayer insulating film 390.
60 and the drain electrode 360 are electrically connected to each other.

In manufacturing the semiconductor device 300D having such a structure, after the semiconductor film 340 made of an intrinsic silicon film and the silicon film 380 are formed in an island shape on the substrate 310, the tantalum film is formed on the surface side thereof. (Insulating layer forming metal film) is formed.

Next, the whole tantalum film is subjected to a high-pressure annealing treatment in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the condition of the high-pressure annealing treatment is, for example,
Temperature is 300 ° C to 400 ° C, pressure is 0.5 MPa to 2M
Pa. As a result, the entire tantalum film is oxidized to form the tantalum oxide film 331. Next, a silicon oxide film 332 is formed on the surface side of the tantalum oxide film 331 by a CVD method or the like, and an insulating layer 330 including the tantalum oxide film 331 and the silicon oxide film 332 is formed.

Next, the silicon film 3 is formed through the insulating layer 330.
80 is doped with N-type impurities. However, TFT
Impurities are not introduced into the semiconductor layer 340 on the 400 side.

Next, the metal layer 320 is formed on the surface of the insulating layer 330.
Are formed, the MIS diode 500 and the capacitor 600 are completed.

On the other hand, on the TFT 300 side, the semiconductor layer 340 is doped with N-type impurities using the metal layer 320 as a gate electrode as a mask. As a result, the regions where the impurities are introduced are the source region 341 and the drain region 34.
2, the region where no impurities are introduced becomes the channel formation region 343.

Next, after forming an interlayer insulating film 390 made of a silicon oxide film on the upper side of the gate electrode (metal layer 320), a contact hole is formed in this interlayer insulating film 390, and then the source electrode 360, and The TFT 300 is completed by forming the drain electrode 370.

In the semiconductor device 300 having such a structure, the insulating layer 330 includes the tantalum oxide film 331 produced by the high-pressure annealing process, and therefore the insulating layer 33 is formed.
The breakdown voltage of 0 is high. Moreover, the temperature of the high-pressure annealing treatment is
Since the temperature is 300 ° C. to 400 ° C., there is no problem even if a glass substrate is used as the substrate 310, for example. Further, even when the aluminum wiring is formed during the high-pressure annealing treatment, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed on the substrate surface.

After the high-pressure annealing process, if the annealing process is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, water is removed from the tantalum oxide film 331, so the tantalum oxide film 331 is removed. Withstand voltage is further improved.

[Fifth Embodiment] Next, as an example of a semiconductor device and an electro-optical device, an active matrix substrate used for an active matrix type liquid crystal device will be described.
An example to which the present invention is applied will be described.

(Overall Structure of Liquid Crystal Device) First, the structure and operation of an active matrix type liquid crystal device (electro-optical device) will be described with reference to FIGS. 2, 3 and 4. FIG. 2 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels formed in a matrix to form an image display area of the liquid crystal device. FIG. 3 is a plan view of pixels adjacent to each other on an active matrix substrate on which data lines, scanning lines, pixel electrodes, etc. are formed.
FIG. 4 is an explanatory diagram showing a cross section at a position corresponding to a line AA ′ in FIG. 3 and a cross section in a state where liquid crystal as an electro-optical material is sealed between the active matrix substrate and the counter substrate. In these figures, the scales are different for each layer and each member in order to make each layer and each member recognizable in the drawings.

In FIG. 2, in the image display area of the liquid crystal device, a pixel electrode 9a and a pixel switching TFT 30 for controlling the pixel electrode 9a are formed in each of a plurality of pixels formed in a matrix. And
The data line 6a that supplies a pixel signal is electrically connected to the source of the TFT 30. The pixel signals S1, S2 ... Sn to be written to the data line 6a are line-sequentially supplied in this order. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2 ... Gm are applied to the scanning line 3a in a pulse-wise manner in this order at a predetermined timing. Is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the pixel signal S1, S2 ... Sn supplied from the data line 6a is generated by turning on the TFT 30 which is a switching element for a certain period. Is written in each pixel at a predetermined timing. In this way, the pixel electrode 9a
The pixel signal S of a predetermined level written in the liquid crystal through the
1, S2, ... Sn are held for a certain period of time with the counter electrode formed on the counter substrate described later.

Here, in order to prevent the held pixel signal from leaking, a storage capacitor 70 may be added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. By this storage capacitor 70, the pixel electrode 9a
Is held for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. As a result, the charge retention characteristic is improved, and a liquid crystal device capable of performing display with a high contrast ratio can be realized. The storage capacity 70
As a method of forming the capacitor, either the method of forming the capacitor and the capacitor line 3b which is a wiring for forming the capacitor or the method of forming the capacitor between the capacitor line 3b and the scanning line 3a in the preceding stage may be used.

In FIG. 3, on the active matrix substrate 10 of the liquid crystal device, a plurality of transparent pixel electrodes 9a (regions surrounded by a chain double-dashed line) are formed in a matrix for each pixel, and the pixel electrodes 9a are arranged vertically and horizontally. Along the boundary area of the data line 6a (shown by a chain line), the scanning line 3a (shown by a solid line),
And a capacitance line 3b (shown by a solid line) is formed. Here, in the semiconductor layer 1a, the gate electrode 3c projects from the scanning line 3a so as to face a channel forming region described later.

As shown in FIG. 4, the liquid crystal device 100 comprises an active matrix substrate 10 and a counter substrate 20 arranged to face the active matrix substrate 10. The base of the active matrix substrate 10 is a transparent substrate 10b such as a quartz substrate or a heat resistant glass plate, and the substrate of the counter substrate 20 is also a transparent substrate 20b such as a quartz substrate or a heat resistant glass plate.
A pixel electrode 9a is formed on the active matrix substrate 10, and an alignment film 64 that has been subjected to a predetermined alignment process such as a rubbing process is formed on the pixel electrode 9a. The pixel electrode 9a is formed of, for example, ITO (Indium Tin O).
xide) film or other transparent conductive thin film. The alignment film 64 is made of an organic thin film such as a polyimide thin film.

On the active matrix substrate 10, a pixel switching TFT 30 (MI) for controlling switching of each pixel electrode 9a is provided at a position adjacent to each pixel electrode 9a.
S-type semiconductor element) is formed. TFT shown here
Reference numeral 30 denotes an inverted stagger type, which includes a gate electrode 3c (metal layer), a gate insulating layer 2 (insulating layer), and an intrinsic silicon film 1
The a (semiconductor layer) includes a MIS portion formed in this order from the lower layer side to the upper layer side. A channel stopper 8 made of a silicon oxide film or the like is formed on the upper layer side of the silicon film 1a, and a source region 1g made of a silicon film doped with an N-type impurity so that the end portion overlaps the channel stopper 8, And a drain region 1h is formed. The data line 6a is formed on the upper layer side of the source region 1g, and the pixel electrode 9a is formed on the upper layer side of the drain region 1h. Further, a protective film 66 and an alignment film 64 are formed in this order on the upper layer side of the pixel electrode 9a.

Further, in this embodiment, the storage capacitor 70 (capacitor element) is formed using the same insulating layer as the gate insulating layer 2 of the TFT 30 as a dielectric film. In the storage capacitor 70, the capacitance line 3b, the gate insulating layer 2, and the drain electrode 6b are formed in this order from the lower layer side to the upper layer.

On the other hand, a counter electrode 21 is formed over the entire surface of the counter substrate 20, and an alignment film 65 subjected to a predetermined alignment treatment such as a rubbing treatment is formed on the surface thereof. The counter electrode 21 is also made of, for example, a transparent conductive thin film such as an ITO film. In addition, the alignment film 6 of the counter substrate 20
5 is also an organic thin film such as a polyimide thin film. On the counter substrate 20, counter substrate side light-shielding films 23 are formed in a matrix shape in regions other than the opening region of each pixel. Therefore, incident light from the counter substrate 20 side does not reach the channel formation region 1a 'of the semiconductor layer 1a of the TFT 30.
Further, the light shielding film 23 on the side of the counter substrate 20 has a function of improving contrast.

The active matrix substrate 10 and the counter substrate 20 thus configured are arranged so that the pixel electrode 9a and the counter electrode 21 face each other, and a space between these substrates is surrounded by a sealing material described later. A liquid crystal 50 as an electro-optical substance is enclosed and sandwiched in the enclosed space. The liquid crystal 50 has a predetermined alignment state by the alignment film in a state where the electric field from the pixel electrode 9a is not applied. Liquid crystal 50
Is composed of, for example, a mixture of one or several kinds of nematic liquid crystals. The sealing material is an adhesive made of a photo-curing resin or a thermosetting resin for bonding the active matrix substrate 10 and the counter substrate 20 around their periphery, and the distance between the substrates is set to a predetermined value. Gap material such as glass fiber or glass beads is blended.

(Structure of MIS Section) In the liquid crystal device 100 having the above structure, the active matrix substrate 10 is used.
In, the MIS portion of the TFT 30 is configured as described below.

First, in the present embodiment, both the scanning line 3a and the gate electrode 3c are made of a tantalum film, and the tantalum oxide film 201 formed by oxidizing the surface of this tantalum film.
Are used as a part of the gate insulating layer 2. That is, the gate insulating layer 2 includes the scanning line 3 a and the gate electrode 3.
A tantalum oxide film 201 formed by oxidizing the surface of the tantalum film used for c, and a silicon oxide film 2 formed on the surface of the tantalum oxide film 201 by a method such as CVD.
02.

In this embodiment, the capacitance line 3b forming the storage capacitor 70 is also made of a tantalum film, and the tantalum oxide film 201 formed by oxidizing the surface of this tantalum film is a dielectric layer (gate insulating layer 2). Form part of the. That is, the dielectric layer forming the storage capacitor 70 is similar to the gate insulating layer 2 in that the tantalum oxide film 201 formed by oxidizing the surface of the tantalum film used for the capacitance line 3b and the surface of this tantalum oxide film 201 And a silicon oxide film 202 formed by a method such as CVD.

Here, in forming the tantalum oxide film 201 by oxidizing the tantalum film, after the tantalum film is formed as an insulating layer forming metal film, the surface of the tantalum film is exposed to an atmosphere containing water vapor. High-pressure annealing is performed to anneal under high pressure at. Here, the conditions of the high-pressure annealing treatment are, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa to 2 MPa. As a result, only the surface of the tantalum film is oxidized to form the tantalum oxide film 201. Therefore, this tantalum oxide film 201 is used as a part of the gate insulating layer 2, and the remaining tantalum film is used as the scanning line 3a.
It is used as the gate electrode 3c and the capacitance line 3b.

As described above, in the active matrix substrate 10 of the present embodiment, the gate insulating layer 2 includes the tantalum oxide film 201 formed by the high-pressure annealing process, so that the gate insulating layer 201 has a high breakdown voltage. Moreover, since the temperature of the high-pressure annealing treatment is 300 ° C to 400 ° C,
For example, a heat-resistant glass plate or the like can be used as the transparent substrate 10b without using an expensive quartz substrate. Since the processing temperature is low when the tantalum oxide film 201 of the gate insulating layer 2 is formed by the high-pressure annealing process, the aluminum wiring is formed on the substrate surface even when aluminum wiring or the like is formed on the transparent substrate 10b when this processing is performed. As long as it is not exposed at, it will not deteriorate.

As shown in FIG. 1B, another electrode layer such as an aluminum electrode may be present under the tantalum film in the gate electrode 3c.

(Manufacturing Method of Active Matrix Substrate 10) A manufacturing method of the active matrix substrate 10 for a liquid crystal display device having such a structure will be described with reference to FIGS. 5 and 6.

5 and 6 are process sectional views showing a method of manufacturing the active matrix substrate 10 of the present embodiment, and correspond to a section taken along the line AA 'in FIG.

As shown in FIG. 5A, first, a transparent substrate 10a which is a base of the active matrix substrate 10 is prepared, and then a tantalum film 3 (insulating layer forming metal film) is sputtered on the entire surface of the transparent substrate 10a. And the scanning line 3a is formed on the tantalum film 3 by photolithography.
Patterning is performed along the formation pattern of the gate electrode 3c and the capacitance line 3b.

Next, the surface of the tantalum film 3 is subjected to a high pressure annealing treatment in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the conditions of the high pressure annealing treatment are, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa to.
It is 2 MPa. As a result, as shown in FIG.
Only the surface of the tantalum film 3 is oxidized and the tantalum oxide film 2
01 is formed, the tantalum oxide film 201 is used as a part of the gate insulating layer 2, and the remaining tantalum film is used as the scanning line 3a, the gate electrode 3c, and the capacitance line 3b.

After the high-pressure annealing process, if the annealing process is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201 and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, as shown in FIG. 5C, TEOS
(Tetra-ethyl-ortho-silicate) gas, TEB
A silicon oxide film 202 is formed by using a (tetra-ethyl borate) gas, a TMOP (tetra-methyl oxy-foslate) gas, or the like by a normal pressure or low pressure CVD method. As a result, the gate insulating layer 2 including the tantalum oxide film 201 and the silicon oxide film 202 is formed.

Next, in a relatively low temperature environment of about 450 ° C. to about 550 ° C., preferably about 500 ° C., a flow rate of about 400 cc.
/ Min to about 600 cc / min by a low pressure CVD method using a monosilane gas, a disilane gas or the like, after forming an amorphous silicon film over the entire surface of the transparent substrate 10b, patterning is performed by using a photolithography technique,
As shown in FIG. 5D, the island-shaped silicon film 1 a is formed on the upper layer side of the gate insulating layer 2. At this time, for example, about 6
The amorphous silicon film 1 may be solid-phase grown on the polysilicon film by performing the annealing treatment at 00 ° C. for about 1 hour to about 10 hours in a nitrogen atmosphere.

Next, a silicon oxide film or the like is formed on the entire surface of the transparent substrate 10b on the upper layer side of the silicon film 1 and then patterned by using a photolithography technique, as shown in FIG. 6 (A). The etching stopper 8 is formed on the upper layer side of the semiconductor film 1a.

Next, the transparent substrate 10b is formed by the CVD method or the like.
A silicon film doped with N-type impurities is formed on the entire surface of, and then patterned by using photolithography, and as shown in FIG. 6B, a source region 1g whose end overlaps the channel stopper 8 is formed. , And the drain region 1h are formed.

Next, a conductive film such as an aluminum film is formed on the entire surface of the transparent substrate 10b on the upper layers of the source region 1g and the drain region 1h by a sputtering method or the like, and then patterned by using a photolithography technique. As shown in FIG. 6C, a data line 6a and a drain electrode 6b which overlap with each of the source region 1g and the drain region 1h are formed. At this time, the drain electrode 6
About b, it forms so that one part may overlap with the capacity line 3b. As a result, the TFT 30 and the storage capacitor 70 are formed.

Next, the transparent substrate 10 is formed by a sputtering method or the like.
After forming an ITO film on the entire surface of b, patterning is performed by using a photolithography technique to form a pixel electrode 9a as shown in FIG. 6D.

As shown in FIG. 1B, another electrode layer such as an aluminum electrode may be present under the tantalum film in the gate electrode 3c.

[Sixth Embodiment] FIGS. 7, 8 and 9
With reference to, an active matrix substrate for a liquid crystal device will be described as a semiconductor device according to the sixth embodiment of the present invention. The active matrix substrate of the present embodiment and the liquid crystal device using the same have the basic configuration of the fifth embodiment.
The same reference numerals are given to portions having common functions, and detailed description thereof will be omitted.

FIG. 7 is a cross-sectional view of the liquid crystal according to Embodiment 6 of the present invention taken along the line AA ′ in FIG. 8A to 8D and FIG.
9A to 9D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

As shown in FIG. 7, the liquid crystal device 10 of the present embodiment.
0 also includes an active matrix substrate 10 and a counter substrate 20 arranged to face the active matrix substrate 10. TFTs 30 for pixel switching are formed on the active matrix substrate 10 at positions adjacent to the respective pixel electrodes 9a.
The T30 includes a MIS portion in which the gate electrode 3c, the gate insulating layer 2, and the intrinsic silicon film 1a are formed in this order from the lower layer side to the upper layer side. Further, in the active matrix substrate 10 of the present embodiment, the storage capacitor 7 in which the same insulating layer as the gate insulating layer 2 of the TFT 30 is used as the dielectric film 7
0 is formed. In this storage capacitor 70, the capacitance line 3
b, the gate insulating layer 2, and the drain electrode 6b are formed in this order from the lower layer side to the upper layer. A counter electrode 21 is formed on the entire surface of the counter substrate 20, and an alignment film 65 that has been subjected to a predetermined alignment process such as a rubbing process is formed on the surface of the counter electrode 21.

In the liquid crystal device 100 configured as described above, in the present embodiment, the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3b are not limited to the tantalum film, but are formed of various metal films, for example, aluminum films. Has been done. Further, a tantalum oxide film 201 is formed on the entire surface of the transparent substrate 10b above the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3b.
It is used as a part of the gate insulating layer 2. That is, the gate insulating layer 2 is composed of a tantalum oxide film 201 and a silicon oxide film 202 formed on the surface of the tantalum oxide film 201 by a method such as CVD.

To form such a tantalum oxide film 201, in this embodiment, as will be described later, after forming a tantalum film as a metal film for forming an insulating layer on the entire surface of the transparent substrate 10b, the entire tantalum film is formed. On the other hand, the tantalum film is oxidized by performing a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. The conditions of the high-pressure annealing treatment performed here are, for example, a temperature of 300 ° C. to 40 ° C.
The temperature is 0 ° C. and the pressure is 0.5 MPa to 2 MPa.

As described above, in the active matrix substrate 10 of the present embodiment, the gate insulating layer 2 includes the tantalum oxide film 201 formed by the high-pressure annealing process, so that the gate insulating layer 201 has a high breakdown voltage. The same effect as that of the fifth embodiment is obtained.

Further, in forming the tantalum oxide film 201, the entire tantalum film formed on the entire surface of the transparent substrate 10b is oxidized by a high pressure annealing process to form a tantalum film, which is used as a part of the gate insulating layer 2.
Therefore, unlike the fifth embodiment, the gate electrode 3c can be made of a metal other than the tantalum film. Therefore, since aluminum wiring can be used for the scanning lines 3a and the like, the electrical resistance of the scanning lines 3a can be reduced.

In manufacturing the active matrix substrate 10 for a liquid crystal display device having such a structure, first, as shown in FIG. 8A, after preparing a transparent substrate 10a which is a base of the active matrix substrate 10, An aluminum film is formed on the entire surface of the transparent substrate 10a by a sputtering method or the like, and the aluminum film is patterned using a photolithography technique to scan lines 3a and gate electrodes 3.
c and the capacitance line 3b are formed.

Next, a tantalum film 205 (metal film for forming an insulating layer) is formed on the entire surface of the transparent substrate 10a on the upper layers of the scanning lines 3a, the gate electrodes 3c, and the capacitance lines 3b by a sputtering method or the like. .

Next, the entire tantalum film 205 is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the conditions of the high-pressure annealing treatment are, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa.
~ 2 MPa. As a result, the entire tantalum film 205 is oxidized and a tantalum oxide film 201 is formed as shown in FIG.

After the high-pressure annealing treatment, if the annealing treatment is carried out at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201 and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, as shown in FIG. 8C, a silicon oxide film 202 is formed on the entire surface of the transparent substrate 10b.
As a result, the tantalum oxide film 201 and the silicon oxide film 20 are
A gate insulating layer 2 made of 2 is formed.

The subsequent steps are the same as in the fifth embodiment.
After forming an amorphous silicon film on the entire surface of the transparent substrate 10b, patterning is performed using a photolithography technique, and as shown in FIG. 8D, an island-shaped silicon film 1a is formed on the upper side of the gate insulating layer 2. Form. Next, after forming a silicon oxide film or the like on the entire surface of the transparent substrate 10b, patterning is performed using a photolithography technique,
As shown in FIG. 9A, the etching stopper 8 is formed on the upper layer side of the semiconductor film 1a. Next, a silicon film doped with an N-type impurity is formed on the entire surface of the transparent substrate 10b by the CVD method or the like, and then patterned by using a photolithography technique, as shown in FIG.
A source region 1g and a drain region 1h are formed.

Next, the transparent substrate 10 is formed by the sputtering method or the like.
After forming a conductive film such as an aluminum film on the entire surface of b, patterning using a photolithography technique,
As shown in FIG. 9C, the data line 6a and the drain electrode 6b are formed. At this time, the drain electrode 6b is formed so that a part thereof overlaps the capacitance line 3b.
As a result, the TFT 30 and the storage capacitor 70 are formed. Next, after forming an ITO film on the entire surface of the transparent substrate 10b by a sputtering method or the like, patterning is performed using a photolithography technique to form a pixel electrode 9a as shown in FIG. 9D. After that, as shown in FIG. 7, the protective film 66 and the alignment film 6 are formed on the upper layer side of the pixel electrode 9a.
When 4 is formed, the active matrix substrate 10 is completed.

[Seventh Embodiment] In the fifth and sixth embodiments,
Inverted stagger type T as a non-linear element for pixel switching
FT was formed, but like this embodiment, a positive stagger type TF
The present invention may be applied to an active matrix substrate using T as a non-linear element for pixel switching. Since the active matrix substrate of the present embodiment and the liquid crystal device using the same have the same basic configuration as that of the fifth embodiment, parts having common functions are designated by the same reference numerals. Detailed description is omitted.

(Structure of Active Matrix Substrate) FIG.
Reference numeral 0 is a plan view of pixels adjacent to each other on the active matrix substrate on which data lines, scanning lines, pixel electrodes, etc. are formed. FIG. 11 is an explanatory diagram showing a cross section at a position corresponding to a line BB ′ in FIG. 10 and a cross section in a state where liquid crystal as an electro-optical substance is sealed between the active matrix substrate and the counter substrate. . In these figures, the scales are different for each layer and each member in order to make each layer and each member recognizable in the drawings.

In FIG. 10, on the active matrix substrate 10 of the liquid crystal device 100, a plurality of transparent pixel electrodes 9a (area surrounded by a chain double-dashed line) are formed in a matrix for each pixel. A data line 6a (shown by a chain line), a scanning line 3a (shown by a metal layer / solid line), and a capacitor line 3b (shown by a metal layer / solid line) are formed along the vertical and horizontal boundary regions. The data line 6a is connected to the semiconductor layer 1a made of a polysilicon film through the contact hole 56.
Of these, it is electrically connected to the source region described later,
The pixel electrode 9a is electrically connected to a later-described drain region of the semiconductor layer 1a via the contact hole 57. In addition, the scanning line 3a passes through the semiconductor layer 1a so as to face a channel forming region described later.

As shown in FIG. 11, the liquid crystal device 100 is
An active matrix substrate 10 and a counter substrate 20 arranged to face the active matrix substrate 10 are provided. The base of the active matrix substrate 10 is a transparent substrate 10b such as a quartz substrate or a heat resistant glass plate, and the substrate of the counter substrate 20 is also a transparent substrate 20b such as a quartz substrate or a heat resistant glass plate. A pixel electrode 9a is formed on the active matrix substrate 10, and an alignment film 64 that has been subjected to a predetermined alignment process such as a rubbing process is formed on the pixel electrode 9a. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 64 is made of an organic thin film such as a polyimide thin film.

On the active matrix substrate 10, a pixel switching TFT 30 for switching control of each pixel electrode 9a is formed at a position adjacent to each pixel electrode 9a. The TFT 30 shown here is an LDD (Lig
a scanning line 3a, a channel forming region 1a '(semiconductor layer) of the semiconductor film 1a in which a channel is formed by an electric field of a scanning signal supplied from the scanning line 3a, and the scanning line 3a. Gate insulating layer 2 (insulating layer) that insulates the semiconductor layer 1a from the data line 6a, the low-concentration source region 1b and the low-concentration drain region 1c of the semiconductor layer 1a, and the high-concentration source region 1d and the high-concentration of the semiconductor layer 1a. The drain region 1e is provided.

An interlayer insulating film 4 is formed on the upper layer side of the scanning line 3a, and a data line 6a is formed on the upper layer of the interlayer insulating film 4. Therefore, the data line 6a is electrically connected to the high concentration source region 1d through the contact hole 56 formed in the interlayer insulating film 4. Also, the data line 6a
An interlayer insulating film 7 is formed on the upper layer side, and a pixel electrode 9a is formed on the upper layer side of the interlayer insulating film 7. Therefore,
The pixel electrode 9a is connected to the high-concentration drain region 1e through the interlayer insulating films 4 and 7 and the contact hole 57 formed in the gate insulating layer 2.

Here, the TFT 30 preferably has the LDD structure as described above, but has the offset structure in which the impurity ions are not implanted into the regions corresponding to the low concentration source region 1b and the low concentration drain region 1c. May be. Further, the TFT 30 may be a self-aligned type TFT in which high-concentration source and drain regions are formed in a self-aligned manner by implanting impurity ions at a high concentration using the gate electrode 3a as a mask.

In this embodiment, the gate insulating layer 2 of the TFT 30 is used.
Is extended from a position facing the gate electrode 3a to be used as a dielectric film, the semiconductor film 1a is extended to be a lower electrode 1f, and a part of the capacitance line 3b facing these is used as an upper electrode. The storage capacitor 70 is configured by the above. That is, the high-concentration drain region 1e of the semiconductor 1a
Are arranged to face the capacitance line 3b via the gate insulating layer 2 and serve as the lower electrode 1f of the storage capacitor 70.

On the other hand, a counter electrode 21 is formed over the entire surface of the counter substrate 20, and an alignment film 65 which has been subjected to a predetermined alignment treatment such as a rubbing treatment is formed on the surface thereof. The counter electrode 21 is also made of, for example, a transparent conductive thin film such as an ITO film. In addition, the alignment film 6 of the counter substrate 20
5 is also an organic thin film such as a polyimide thin film. On the counter substrate 20, counter substrate side light-shielding films 23 are formed in a matrix shape in regions other than the opening region of each pixel.

In the liquid crystal device 100 thus configured, the gate insulating layer 2 is formed on the upper side of the semiconductor film 1a by CVD.
Oxide film 202 formed by a method such as
And a tantalum oxide film 201 formed by oxidizing a tantalum film formed on the upper layer side of the silicon oxide film 202.

In forming the tantalum oxide film 201 as described above, in this embodiment, as will be described later, tantalum as a metal film for forming an insulating layer is formed on the entire surface of the transparent substrate 10b with respect to the upper layer side of the silicon oxide film 202. After the film is formed, the entire tantalum film is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor to oxidize the tantalum film. The conditions of the high-pressure annealing treatment performed here are, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa to 2 MPa.

Therefore, in the active matrix substrate 10 of the present embodiment, the gate insulating layer 2 includes the tantalum oxide film 201 formed by the high-pressure annealing process, so that the breakdown voltage of the gate insulating layer 201 is high. The same effect as that of the first embodiment is obtained.

In forming the tantalum oxide film 201, the entire tantalum film formed on the entire surface of the transparent substrate 10b is oxidized by a high pressure annealing process to form a tantalum film, which is used as a part of the gate insulating layer 2.
That is, the tantalum oxide film 201 does not oxidize only the surface of the tantalum film. Therefore, since the tantalum film does not remain after the tantalum oxide film 201 is formed,
Also in the positive stagger type TFT 30, the tantalum oxide film 201 can be included in the gate insulating layer 2. Also,
The scanning line 3a is not limited to the tantalum film, and an arbitrary metal film can be used. Therefore, a metal film having a low electric resistance such as an aluminum film can be used.

(Manufacturing Method of Active Matrix Substrate)
A method of manufacturing the active matrix substrate 10 for a liquid crystal display device configured as described above will be described with reference to FIGS.
This will be described with reference to FIG.

12 to 14 are process cross-sectional views showing the method of manufacturing the active matrix substrate 10 of this embodiment, which correspond to the cross section taken along the line BB 'of FIG.

As shown in FIG. 12A, first, a base protective film (not shown) is formed on the entire surface of the transparent substrate 10b, which is the base of the active matrix substrate 10, and then, on the upper layer side of the base protective film. Under a temperature condition of about 450 ° C. to about 550 ° C., a reduced pressure C using monosilane gas, disilane gas, etc.
An amorphous silicon film is formed by the VD method or the like. Next, an annealing process is performed at about 600 ° C. for about 1 hour to about 10 hours in a nitrogen atmosphere to solid-phase grow the polysilicon film, which is then patterned using photolithography technology to form islands. The silicon film 1a is formed.

Next, as shown in FIG. 12B, CVD
Silicon on the entire surface of the transparent substrate 10b by a method such as
The film 202 is formed. Next, in the silicon film 1a, the storage
For example, in the extended portion that becomes the lower electrode 1f of the product capacitance 70N, P
Ion dose about 3 × 10 ¹²/ Cm² Doped with low
Make it resistance.

Next, as shown in FIG. 12C, a tantalum film 205 (metal film for forming an insulating film) is formed on the entire surface of the transparent substrate 10b by sputtering or the like on the upper layer side of the silicon oxide film 202. Form.

Next, the entire tantalum film 205 is subjected to a high pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor. Here, the conditions of the high-pressure annealing treatment are, for example, a temperature of 300 ° C. to 400 ° C. and a pressure of 0.5 MPa.
~ 2 MPa. As a result, the entire tantalum film 205 is oxidized to form the tantalum oxide film 201 and the gate insulating layer 2 including the silicon oxide film 202 and the tantalum oxide film 201, as shown in FIG. .

After the high-pressure annealing process, if the annealing process is performed at a temperature of 200 ° C. to 500 ° C. under normal pressure or reduced pressure, moisture is removed from the tantalum oxide film 201, and the crystallinity is improved. Tantalum oxide film 201
The film quality is improved.

Next, with respect to the upper layer side of the gate insulating layer 2,
After forming an aluminum film on the entire surface of the transparent substrate 10b by a sputtering method or the like, patterning is performed using a photolithography technique to form a scanning line 3a and a capacitance line 3b as shown in FIG.

Next, when the TFT 30 is an N-channel type TFT having an LDD structure, the scanning line 3a is used as a diffusion mask to form the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a. As a dopant of a V group element such as P at a low concentration (for example, P
Ions are doped at a dose of 1 × 10 ¹³ / cm ^{2 to} 3 × 10 ¹³ / cm ² ). As a result, the semiconductor layer 1a below the scanning line 3a becomes the channel formation region 1a '.

Next, as shown in FIG. 13B, the TFT
In order to form the high-concentration source region 1d and the high-concentration drain region 1e of 30, a resist mask 202 is formed on the scanning line 3a with a mask wider than the scanning line 3a, and then a group V element such as P is also added. Dopant 201 is highly doped. Note that an offset structure TFT may be used without performing low-concentration doping, and a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, etc., using the scanning line 3a (gate electrode) as a mask. good.

Next, as shown in FIG. 13C, an interlayer insulating film 4 made of a silicon oxide film is formed so as to cover the scanning lines 3a and the capacitance lines 3. Next, a contact hole 56 is formed in the interlayer insulating film 4 by dry etching such as reactive ion etching or reactive ion beam etching, or wet etching.

Next, after forming an aluminum film on the entire surface of the transparent substrate 10b on the upper layer side of the interlayer insulating film 4,
Patterning is performed using the photolithography technique to form the data 6a as shown in FIG.

Next, as shown in FIG. 14A, an interlayer insulating film 7 made of a silicon oxide film is formed so as to cover the data lines 6a. Next, the contact holes 57 are formed in the interlayer insulating films 7 and 4 and the gate insulating layer 2 by dry etching such as reactive ion etching or reactive ion beam etching, or wet etching.

Next, with respect to the upper layer side of the interlayer insulating film 7, ITO is formed on the entire surface of the transparent substrate 10b by sputtering or the like.
After forming the film, patterning is performed by using the photolithography technique, and as shown in FIG.
a is formed.

Then, as shown in FIG. 11, after applying a coating liquid of a polyimide-based alignment film on the upper layer side of the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. Thus, the alignment film 64 is formed, and the active matrix substrate 10 is completed.

[Other Embodiments] In the above embodiment, tantalum (Ta) was used as the insulating layer forming metal film.
A tantalum alloy may be used. If an oxide film can be formed by high-pressure annealing, another metal such as niobium (Nb), molybdenum (Mo), titanium (Ti), or an alloy thereof is used as the insulating layer forming metal. Good.

In the above embodiment, the silicon oxide film is used as the insulating film laminated with the tantalum oxide film, but a silicon nitride film may be used.

Furthermore, if a semiconductor substrate is used as the substrate, the MIS type semiconductor element is not limited to a thin film transistor, but a bulk type MIS type transistor can be constructed. That is, a semiconductor substrate is used as a substrate, an insulating film made of the same semiconductor material as the semiconductor substrate is formed on the upper surface of the semiconductor substrate, and then an insulating layer forming metal film is formed. After the high-pressure annealing process is performed on the metal layer, a metal layer is formed on the upper side of the oxide film of the metal film for forming an insulating layer.
Shaped transistors can be formed.

Further, in the above embodiment, the active matrix type liquid crystal device using the TFT element as the non-linear element for pixel switching has been described as an example, but the present invention is not limited to this, and various circuits are configured in other semiconductor devices. The present invention may be applied when forming a MIS type diode or a transistor, and various modifications can be made within the scope of the invention described in the claims. The scope of this invention is
Of course, an active matrix type liquid crystal device using a TFD element as a nonlinear element for switching is also included. Further, the present invention is directed to electroluminescence (E
It is needless to say that the present invention is also applicable to an electro-optical device using L), a digital micro-mirror device (DMD), or various electro-optical elements using plasma light emission or fluorescence due to electron emission.

[Structure of Liquid Crystal Device] Embodiments 5, 6, and 7
The overall configuration of the liquid crystal device 100 using the active matrix substrate 10 manufactured by will be described with reference to FIGS. 15 and 16. Note that FIG. 15 is a plan view of the liquid crystal device 100 together with the components formed thereon as viewed from the counter substrate 20 side, and FIG. 16 is a H-H diagram of FIG. 15 including the counter substrate 20. ′ It is a cross-sectional view.

In FIG. 15, a sealing material 52 is provided along the edge of the active matrix substrate 10 of the liquid crystal device 100, and a frame 53 made of a light shielding material is formed in the inner area thereof. ing. Seal material 52
In the region outside of, the data line driving circuit 101 and the mounting terminals 102 are provided along one side of the active matrix substrate 10, and the scanning line driving circuit 104 is formed along two sides adjacent to this one side. ing. It goes without saying that the scanning line driving circuit 104 may be provided on only one side if the delay of the scanning signal supplied to the scanning line does not matter. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area 10a. For example, the odd-numbered data lines supply an image signal from a data line driving circuit arranged along one side of the image display area 10a,
The data lines in the even-numbered columns may be supplied with an image signal from a data line driving circuit arranged along the opposite side of the image display area 10a. By thus driving the data lines in a comb shape, the formation area of the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured. Furthermore, the active matrix substrate 10
A plurality of wirings 1 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area 10a are provided on the remaining one side.
05 is provided, and a precharge circuit and a test circuit may be provided under the frame 53. In addition, at least one of the corners of the counter substrate 20
At the location, a vertical conduction member 1 for electrically connecting the active matrix substrate 10 and the counter substrate 20.
06 is formed.

Then, as shown in FIG. 16, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG.
Is stuck to. In this counter substrate 20, a light-shielding film 23 called a black matrix or a black stripe is formed in a region facing the vertical and horizontal boundary regions of the pixel electrodes 9a formed on the active matrix substrate 10.
Is formed, and the counter electrode 21 made of an ITO film is formed on the upper side thereof. An alignment film (not shown) made of a polyimide film is formed on the upper layer side of the counter electrode 21, and the alignment film is a film obtained by rubbing the polyimide film.

Instead of forming the data line driving circuit 101 and the scanning line driving circuit 104 on the active matrix substrate 10, for example, a TAB (tape automated, bonding) substrate on which a driving LSI is mounted is used as an active matrix. You may make it electrically and mechanically connect to the terminal group formed in the peripheral part of the board | substrate 10 through an anisotropic conductive film. Further, on the light incident side surface or the light emitting side of the counter substrate 20 and the active matrix substrate 10, the type of the liquid crystal 50 used,
That is, TN (Twisted Nematic) mode,
A polarizing film, a retardation film, a polarizing plate, etc. are arranged in a predetermined direction depending on the operation mode such as STN (super TN) mode and the normally white mode / normally black mode.

The electro-optical device thus formed is used, for example, in a projection type liquid crystal display device (liquid crystal projector) described later. In this case, three liquid crystal devices 1
00 is used as a light valve for RGB, and the light of each color decomposed through the dichroic mirror for RGB color separation enters each of the liquid crystal devices 100 as projection light. Therefore, the color filter is not formed in the liquid crystal device 100 of each of the above-described embodiments.

However, in the counter substrate 20, each pixel electrode 9
By forming an RGB color filter together with its protective film in a region facing a, a mobile computer, a mobile phone, and
It can be used as a color liquid crystal display device for electronic devices such as liquid crystal televisions.

Further, by forming a microlens on the counter substrate 20 so as to correspond to each pixel,
Since the efficiency of collecting incident light on the pixel electrode 9a can be improved, bright display can be performed. Furthermore, by stacking a number of interference layers having different refractive indexes on the counter substrate 20, a dichroic filter that produces RGB colors may be formed by utilizing the interference effect of light. According to the counter substrate with the dichroic filter, brighter color display can be performed.

[Application to Electronic Device] Next, an example of an electronic device including an electro-optical device will be described with reference to FIGS. 17, 18, and 19.
And it demonstrates with reference to FIG.

First, FIG. 17 is a block diagram showing the configuration of an electronic apparatus including a liquid crystal device 100 having the same configuration as the electro-optical device according to each of the above embodiments.

In FIG. 17, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, the liquid crystal device 100, the clock generation circuit 1008,
And a power supply circuit 1010. The display information output source 1000 is a ROM (Read Only Me
memory), RAM (Random AccessMe)
memory), a memory such as an optical disk, a tuning circuit that tunes and outputs a picture signal of a television signal, and the like, and processes an image signal of a predetermined format based on a clock from a clock generation circuit 1008 to display information. Output to the processing circuit 1002. This display information output circuit 10
Reference numeral 02 denotes a well-known processing circuit such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, or a clamp circuit, which is a digital signal based on display information input based on a clock signal. Drive circuit 1 together with the clock signal CLK.
Output to 004. The drive circuit 1004 is used for the liquid crystal device 10.
Drive 0. The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The drive circuit 1004 may be formed on the active matrix substrate that constitutes the liquid crystal device 100, and in addition to this, the display information processing circuit 100
2 may also be formed on the active matrix substrate.

FIG. 1 shows an electronic device having such a configuration.
8, a projection type liquid crystal display device (liquid crystal projector), a multimedia compatible personal computer (PC), and an engineering workstation (EWS), a pager, a mobile phone, a word processor, a television, a viewfinder type or Examples include a monitor direct-view video tape recorder, an electronic notebook, an electronic desk calculator, a car navigation device, a POS terminal, and a touch panel. The present invention also provides an electronic device including an electro-optical device using electroluminescence (EL), a digital micromirror device (DMD), or various electro-optical elements that use plasma emission, fluorescence due to electron emission, or the like. It goes without saying that it is also applicable.

The projection type liquid crystal display device 1100 shown in FIG.
Prepares three liquid crystal modules including the liquid crystal device 100 in which the drive circuit 1004 is mounted on the active matrix substrate, and the light valves 100R for RGB respectively.
It is configured as a projector used as 100G and 100B. In this liquid crystal projector 1100, a lamp unit 1 for a white light source such as a metal halide lamp is used.
When light is emitted from 102, three mirrors 1106 and two dichroic mirrors 1108
The light components R, G, and B corresponding to the three primary colors R, G, and B are separated (light separating means), and the corresponding light valves 100R and
100G and 100B (liquid crystal device 100 / liquid crystal light valve), respectively. At this time, the light component B has a long optical path, and thus is guided through the relay lens system 1121 including the entrance lens 1122, the relay lens 1123, and the exit lens 1124 in order to prevent light loss. Then, the light components R, G, and B respectively corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 1112 (light combining means) from three directions, are combined again, and are then projected onto the projection lens. It is projected as a color image on the screen 1120 or the like via 1114.

FIG. 19 shows a mobile personal computer which is an embodiment of an electronic apparatus according to the present invention. The personal computer shown here includes a main body 82 having a keyboard 81 and a liquid crystal display unit 83.
Have and. The liquid crystal display unit 83 is configured to include the liquid crystal device 100 described above.

FIG. 20 shows a mobile phone which is another embodiment of the electronic apparatus according to the present invention. The mobile phone 90 shown here has a plurality of operation buttons 91 and a liquid crystal device 100.
have.

[0152]

As described above, in the semiconductor device according to the present invention, since the insulating layer contains the tantalum oxide film formed by the high-pressure annealing treatment, the insulating layer has a high breakdown voltage. Moreover, since the temperature of the high-pressure annealing treatment is 300 ° C. to 400 ° C., there is no problem even when a glass substrate is used as the substrate. Further, even when the aluminum wiring is formed during the high-pressure annealing treatment, under such temperature conditions, the aluminum wiring is not deteriorated unless the aluminum wiring is exposed on the substrate surface.

[Brief description of drawings]

1A to 1D are cross-sectional views each schematically showing a configuration of a semiconductor device according to first to fourth embodiments of the present invention.

FIG. 2 is an equivalent circuit diagram of various elements, wirings, etc. formed in a plurality of pixels arranged in a matrix in an image display area of a liquid crystal device to which the present invention is applied.

FIG. 3 is a plan view showing a configuration of each pixel formed on an active matrix substrate according to a fifth embodiment of the present invention in the liquid crystal device shown in FIG.

4 is a cross-sectional view of the liquid crystal device shown in FIG. 3 when cut at a position corresponding to line AA ′ in FIG.

5A to 5D are respectively FIG. 3 and FIG.
FIG. 6 is a process cross-sectional view showing the method for manufacturing the active matrix substrate shown in FIG.

6A to 6D are respectively FIGS. 3 and 4.
FIG. 6 is a process cross-sectional view of a process performed subsequent to the process shown in FIG. 5 in the manufacturing process of the active matrix substrate shown in FIG.

FIG. 7 shows a liquid crystal liquid crystal according to a sixth embodiment of the present invention.
FIG. 6 is a cross-sectional view when cut at a position corresponding to the line AA ′ in FIG.

8A to 8D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIG.

9A to 9D are process cross-sectional views of a process performed subsequent to the process shown in FIG. 8 in the manufacturing process of the active matrix substrate shown in FIG. 7.

FIG. 10 is a plan view showing a configuration of each pixel formed on an active matrix substrate used in a liquid crystal device according to Embodiment 7 of the present invention.

11 is a cross-sectional view of the liquid crystal device according to Embodiment 7 of the present invention when cut at a position corresponding to line BB ′ in FIG.

12A to 12D are process cross-sectional views showing a method for manufacturing the active matrix substrate shown in FIGS. 10 and 11, respectively.

13A to 13D are process cross-sectional views of a process performed subsequent to the process shown in FIG. 12 among the manufacturing processes of the active matrix substrate shown in FIGS. 10 and 11.

14A and 14B are process cross-sectional views of a process performed subsequent to the process shown in FIG. 13 in the manufacturing process of the active matrix substrate shown in FIG. 11.

FIG. 15 is a plan view of the liquid crystal device as seen from the counter substrate side.

16 is a cross-sectional view taken along the line HH 'of FIG.

FIG. 17 is a block diagram showing a circuit configuration of an electronic device using the liquid crystal device according to the present invention as a display unit.

FIG. 18 is a cross-sectional view showing a configuration of an optical system of a projection electro-optical device as an example of an electronic apparatus using the liquid crystal device according to the invention.

FIG. 19 is an explanatory diagram showing a mobile personal computer as an embodiment of an electronic apparatus using the liquid crystal device according to the present invention.

FIG. 20 is an explanatory diagram of a mobile phone as an embodiment of an electronic apparatus using the liquid crystal device according to the invention.

[Explanation of symbols]

1a semiconductor layer 1a 'Channel formation region (semiconductor layer) 2 Gate insulating layer (insulating layer) 3a Scan line (metal layer) 3b Capacitance line (metal layer) 3c gate electrode 6a data line 9a Pixel electrode 10 Active matrix substrate (semiconductor device) 10b transparent substrate 20 Counter substrate 30 pixel switching TFT 50 Liquid crystal (electro-optical material) 70 Storage capacity (capacitor element) 100 Liquid crystal device (electro-optical device) 201,331 Tantalum oxide film 202, 332 Silicon oxide film 205 Tantalum film (metal film for insulating film formation) 300A, 300B, 300C, 300D semiconductor device 310 substrate 320 metal layer 330 insulating layer 340 Intrinsic semiconductor layer 341 Source area 342 drain region 350 conductive silicon film 360 source electrode 370 drain electrode 400 TFT 500 MIS type diode 600 capacitors

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/786 H01L 29/78 617M 617T 617L F term (reference) 2H092 JA24 JB69 MA23 MA29 5F038 AC15 AC16 AC18 EZ17 EZ20 5F058 BA01 BA11 BB04 BD01 BD04 BD05 BF54 BF63 BJ01 5F110 AA12 BB01 BB20 CC02 DD02 DD03 DD11 EE03 EE04 EE14 EE44 FF01 FF02 FF03 FF09 FF22 FF23 FF28 FF29 FF36 GG02 GG13 GG35 GG47 HJ01 HJ04 HJ13 HK09 HK34 HL03 HL07 HL23 HM14 HM15 NN02 NN12 NN23 NN72 NN73 PP10 QQ11

Claims (27)

[Claims] 1. A semiconductor device in which a MIS type semiconductor element having a MIS portion composed of a metal layer, an insulating layer, and a semiconductor layer is formed on a substrate, wherein the insulating layer is under a high pressure in an atmosphere containing water vapor. 2. A semiconductor device comprising an oxide film formed by oxidizing a metal film for forming an insulating layer by a high-pressure annealing process of annealing at. 2. The semiconductor device according to claim 1, wherein the insulating layer forming metal film is a tantalum film or a tantalum alloy film. 3. The insulating layer according to claim 1, wherein the insulating layer includes an oxide film formed from the insulating layer forming metal film on the metal layer side, and the semiconductor layer on the semiconductor layer side includes the oxide film. A semiconductor device comprising an insulating film formed of the same semiconductor material. 4. The method according to any one of claims 1 to 3,
The semiconductor device, wherein the metal layer is made of the same metal material as the metal film for forming the insulating layer at least on the side in contact with the insulating layer. 5. The method according to any one of claims 1 to 3,
The semiconductor device, wherein the metal layer is made of a metal material different from that of the insulating layer forming metal film. 6. The method according to any one of claims 1 to 5,
On the substrate, the metal layer, the insulating layer, and the semiconductor layer are formed in this order from a lower layer side to an upper layer side. 7. The method according to any one of claims 1 to 5,
On the substrate, the semiconductor layer, the insulating layer, and the metal layer are formed in this order from a lower layer side to an upper layer side. 8. The method according to claim 1, wherein
The semiconductor device, wherein the MIS type semiconductor element is a thin film transistor. 9. The semiconductor device according to claim 7, wherein the MIS type semiconductor element is a MIS type transistor. 10. The semiconductor device according to claim 1, wherein the MIS type semiconductor element is a MIS type diode. 11. The dielectric film according to claim 1, wherein at least an oxide film of the same metal film as the insulating layer forming metal film is used as a dielectric film on the substrate, and one of the metal layers is formed on the substrate. A semiconductor device in which a capacitor element used as an electrode is formed. 12. An electro-optical device using the semiconductor device defined in claim 8 as an active matrix substrate, wherein the thin film transistor is used as a non-linear element for pixel switching on the substrate. Electro-optical device. 13. The oxide film according to claim 12, wherein at least the oxide film of the insulating layer forming metal film is used as a dielectric film and the metal layer is used as one electrode on the active matrix substrate. A semiconductor device having a previously formed storage capacitor. 14. An electronic apparatus using the electro-optical device defined in claim 12 or 13. 15. A method of manufacturing a semiconductor device in which a MIS-type semiconductor element having a MIS portion including a metal layer, an insulating layer, and a semiconductor layer is formed on a substrate, after forming a metal film for forming an insulating layer, A semiconductor characterized in that the metal film for forming an insulating layer is oxidized by a high-pressure annealing process in which it is annealed under a high pressure in an atmosphere containing water vapor to form an oxide film, and the oxide film is used as a part of the insulating layer. Device manufacturing method. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the insulating layer forming metal film is a tantalum film or a tantalum alloy film. 17. The high pressure annealing process according to claim 15, wherein only the surface of the insulating layer forming metal film is oxidized to generate the oxide film, and the oxide film is used as a part of the insulating layer. A method of manufacturing a semiconductor device, wherein the remaining insulating layer forming metal film is used as the metal layer or a part of the metal layer. 18. The high-pressure annealing process according to claim 15, wherein the insulating film forming metal film is entirely oxidized to form the oxide film, and the oxide film is used as a part of the insulating layer. A method for manufacturing a characteristic semiconductor device. 19. The insulating layer according to claim 18, wherein the metal layer is formed below the insulating layer forming metal film, and the high-pressure annealing treatment is performed on the insulating layer forming metal film. A method of manufacturing a semiconductor device, comprising: forming an insulating film made of the same semiconductor material as that of the semiconductor layer and the semiconductor layer in this order on the upper side of the oxide film of the forming metal film. 20. The insulating layer formed according to claim 18, wherein the semiconductor layer and an insulating film made of the same semiconductor material as the semiconductor layer are formed below the insulating layer forming metal film. A method of manufacturing a semiconductor device, comprising: performing the high-pressure annealing process on a metal film for use in a semiconductor device, and thereafter forming the metal layer on an upper layer side of an oxide film of the metal film for forming an insulating layer. 21. The semiconductor film according to claim 20, wherein a semiconductor substrate is used as the substrate, an insulating film made of the same semiconductor material as that of the semiconductor substrate is formed on an upper surface of the semiconductor substrate, and then the insulating layer forming metal film. And performing the high-pressure annealing treatment on the insulating-layer-forming metal film, and then forming the metal layer on the upper layer side of the oxide film of the insulating-layer-forming metal film. Method. 22. The method of manufacturing a semiconductor device according to claim 15, wherein a thin film transistor is manufactured as an MIS type semiconductor element including the MIS section. 23. The method of manufacturing a semiconductor device according to claim 21, wherein a MIS transistor is manufactured as the MIS semiconductor element including the MIS portion. 24. The method of manufacturing a semiconductor device according to claim 15, wherein a MIS diode is manufactured as the MIS semiconductor element including the MIS portion. 25. The dielectric layer or a part of the dielectric layer according to claim 15, wherein an oxide film formed at the same time as the oxide film of the insulating layer forming metal film is formed on the substrate. And a metal layer formed simultaneously with the metal layer is used as one electrode to form a capacitor element. 26. The high pressure annealing process according to claim 15, wherein the temperature is 300 ° C. to 40 ° C.
A method for manufacturing a semiconductor device, which is performed under conditions of 0 ° C. and a pressure of 0.5 MPa to 2 MPa. 27. The method of manufacturing a semiconductor device according to claim 15, wherein after the high-pressure annealing treatment is performed, the annealing treatment is performed under normal pressure or reduced pressure.