JP3316472B2 - Method of connecting electric element and method of manufacturing liquid crystal panel - Google Patents
Method of connecting electric element and method of manufacturing liquid crystal panelInfo
- Publication number
- JP3316472B2 JP3316472B2 JP8695199A JP8695199A JP3316472B2 JP 3316472 B2 JP3316472 B2 JP 3316472B2 JP 8695199 A JP8695199 A JP 8695199A JP 8695199 A JP8695199 A JP 8695199A JP 3316472 B2 JP3316472 B2 JP 3316472B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- adhesive layer
- semiconductor chip
- wiring pattern
- electric element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電気素子の電極と
基板の配線パターンを導通接続して電気素子を基板の上
へ搭載接合する構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure in which an electrode of an electric element is electrically connected to a wiring pattern of a substrate, and the electric element is mounted on the substrate and joined.
【０００２】[0002]
【従来の技術】従来の電気養子の接合構造は第２図
（ａ）〜（ｃ）のようなものであった。第２図におい
て、２１は基板、２２は基板上の配線パターン、２３は
電気素子、２４は電気素子の電極を示す。まず第２図
（ａ）は、基板上の配線パターンにプローバ２５をおし
あてて基板の検査をしている工程を示す。次に第２図
（ｂ）は、第２図（ａ）において合格になった基板につ
いて導電性微粒子２７を拡散・混在させた接着剤シート
２６を載置した工程を示す。2. Description of the Related Art A conventional joining structure of an electric adopter is as shown in FIGS. 2 (a) to 2 (c). In FIG. 2, 21 is a substrate, 22 is a wiring pattern on the substrate, 23 is an electric element, and 24 is an electrode of the electric element. First, FIG. 2 (a) shows a process of applying a prober 25 to a wiring pattern on a substrate to inspect the substrate. Next, FIG. 2 (b) shows a process in which an adhesive sheet 26 in which conductive fine particles 27 are diffused and mixed is placed on a substrate which has passed in FIG. 2 (a).
【０００３】この導電粒子を拡散・混在させた接着剤シ
ートは厚さ２０〜３０μｍ、導電微粒子の径は５〜１２
μｍである。The adhesive sheet in which the conductive particles are diffused and mixed has a thickness of 20 to 30 μm, and the diameter of the conductive fine particles is 5 to 12 μm.
μm.
【０００４】また、第２図（ｃ）は、電気素子の上面よ
り加熱しながら加圧し、接着剤を硬化させ、電気素子を
基板の上に接合させた様子を示す。FIG. 2 (c) shows a state in which pressure is applied while heating from the upper surface of the electric element, the adhesive is cured, and the electric element is bonded on the substrate.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来の電気素
子の接合構造は第２図より明らかなように幾多の問題点
を有するものであった。However, as shown in FIG. 2, the conventional structure for joining electric elements has a number of problems.
【０００６】まず電気素子２３を基板２１の上に接合す
る時電気素子の電極２４と対応する基板上の配線パター
ン２２とは平面的な位置合わせを行なう必要がある。First, when the electric element 23 is bonded onto the substrate 21, it is necessary to perform planar alignment between the electrode 24 of the electric element and the corresponding wiring pattern 22 on the substrate.
【０００７】しかし、この基板が機能的な基板であり、
検査を行なって良品の基板のみを遠別する必要がある場
合、第２図（ｃ）のような電気素子を基板上に接合する
工程の前に、第２図（ａ）のようなプローバ２５を使っ
た検査工程が必要となる。However, this substrate is a functional substrate,
When it is necessary to perform inspection and separate only non-defective substrates, a prober 25 as shown in FIG. 2A is connected before the step of bonding electric elements on the substrate as shown in FIG. 2C. The inspection process used is required.
【０００８】この検査工程も当然の事ながら、プローバ
２５の先端位置と基板の配線パターンの位置とを平面的
に位置合わせする必要がある。この結果、煩雑で作業工
数の大きな位置合わせ工程が上記の電気素子の電極と基
板の配線パターンとの位置合わせと合わせて２回必要と
いうことになり、全体として作業工数の大きな、従って
製造コストが大きなものとなってしまうものであった。As a matter of course, in this inspection step, it is necessary to align the position of the tip of the prober 25 with the position of the wiring pattern on the substrate in a planar manner. As a result, a complicated positioning step requiring a large number of man-hours is required twice in addition to the positioning between the electrodes of the electric elements and the wiring patterns on the substrate. It was a big one.
【０００９】さらに電気素子２３も別個に使用に検査し
ておく必要があり、検査もれがあった場合、そのまま第
２図（ｃ）のように接着剤を硬化させて接合した場合、
接合後の良品率が下がるものであった。Further, it is necessary to separately inspect the electric element 23 for use. If there is any leakage from the inspection, if the adhesive is hardened as shown in FIG.
The non-defective rate after joining was reduced.
【００１０】さらに、本説明の様に、導電性微粒子を拡
散、混在させた接着剤を用いて、電気素子を基板上へ接
合して、その後、不良が発見された場合、上記接着剤が
硬化しているにもかかわらず、電気素子を基板から剥離
して再生しなければならない。しかし、上記接着剤が硬
化している為、剥離再生は極めて難しく、剥離再生作業
の工数が大きいばかりでなく、剥離再生が失敗する確率
も高いものである。Further, as described in the present description, an electric element is bonded onto a substrate by using an adhesive in which conductive fine particles are diffused and mixed, and thereafter, when a defect is found, the adhesive is cured. Nevertheless, the electrical element must be peeled off from the substrate and regenerated. However, since the adhesive is hardened, peeling and regenerating is extremely difficult. Not only is the man-hour for peeling and regenerating work large, but also the probability of peeling and regenerating failure is high.
【００１１】そこで、本発明は従来のこの様な欠点を解
決し電気素子と基板の位置合わせを容易にし、不良時の
剥離再生を不用とする事を目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional drawbacks described above, facilitate the alignment between the electric element and the substrate, and eliminate the need for peeling and regenerating when there is a defect.
【００１２】[0012]
【課題を解決するための手段】本発明の電気素子の接続
方法は、配線パターンが形成された基板と複数の電極を
有した電気素子とを、前記基板上に形成された導電性微
粒子を含む第１の接着剤層と、当該第１の接着剤層上で
あって前記電気素子の前記複数の電極と前記基板の前記
配線パターンの対応部位を除いた前記電気素子の前記電
極の間に形成された第２の接着剤層とを介在して接合す
る電気素子の接続方法であって、前記電気素子を常温下
で前記基板上に押しつけて前記配線パターンと前記電気
素子の前記複数の電極とを前記第１の接着剤層を介して
電気的接続する工程と、前記配線パターン及び前記電気
素子に駆動信号を入力することによって検査を行う工程
と、しかる後に前記電気素子を上から加熱及び加圧して
前記第１の接着剤層と前記第２の接着剤層を硬化させ、
前記電気素子を前記基板に接合する工程と、を有するこ
とを特徴とする。又、本発明の液晶パネルの製造方法
は、配線パターンが形成された基板と複数の電極を有し
た半導体チップとを、前記基板上に形成された導電性微
粒子を含む第１の接着剤層と、当該第１の接着剤層上で
あって前記半導体チップの前記複数の電極と前記基板の
前記配線パターンの対応部位を除いた前記半導体チップ
の前記電極の間に形成された第２の接着剤層とを介在し
て接合する液晶パネルの製造方法であって、前記半導体
チップを常温下で前記基板上に押しつけて前記配線パタ
ーンと前記半導体チップの前記複数の電極とを前記第１
の接着剤層を介して電気的接続する工程と、前記配線パ
ターン及び前記半導体チップに駆動信号を入力すること
によって検査を行う工程と、しかる後に前記半導体チッ
プを上から加熱及び加圧して前記第１の接着剤層と前記
第２の接着剤層を硬化させ、前記半導体チップを前記基
板に接合する工程と、を有することを特徴とする。According to the present invention, there is provided a method for connecting an electric element, comprising connecting a substrate having a wiring pattern formed thereon and an electric element having a plurality of electrodes to conductive fine particles formed on the substrate. A first adhesive layer, formed on the first adhesive layer, between the plurality of electrodes of the electric element and the electrodes of the electric element except for portions corresponding to the wiring pattern of the substrate; A method for connecting an electric element to be joined with a second adhesive layer interposed therebetween, wherein the electric element is pressed onto the substrate at room temperature to form the wiring pattern and the plurality of electrodes of the electric element. Electrically connecting the wiring pattern via the first adhesive layer, performing a test by inputting a drive signal to the wiring pattern and the electrical element, and then heating and heating the electrical element from above. Press the first adhesive Curing the second adhesive layer and,
Bonding the electric element to the substrate. Further, the method of manufacturing a liquid crystal panel of the present invention includes the steps of: forming a substrate on which a wiring pattern is formed and a semiconductor chip having a plurality of electrodes by forming a first adhesive layer containing conductive fine particles formed on the substrate; A second adhesive formed on the first adhesive layer and between the plurality of electrodes of the semiconductor chip and the electrodes of the semiconductor chip except for a portion corresponding to the wiring pattern of the substrate; A method for manufacturing a liquid crystal panel in which a semiconductor chip is pressed onto the substrate at room temperature to bond the wiring pattern and the plurality of electrodes of the semiconductor chip to the first electrode.
Electrically connecting via an adhesive layer of the above, a step of performing an inspection by inputting a drive signal to the wiring pattern and the semiconductor chip, and then heating and pressurizing the semiconductor chip from above, the Curing the first adhesive layer and the second adhesive layer, and joining the semiconductor chip to the substrate.
【００１３】[0013]
【発明の実施の形態】以下に本発明の実施例を図面を用
いて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１４】第１図（ａ）〜（ｄ）は本発明による電気
素子の接続構造を示すものである。FIGS. 1A to 1D show a connection structure of an electric element according to the present invention.
【００１５】第１図において、１は基板たるガラス基
板、２はガラス基板上の配線パターン、３は電気素子た
る半導体チップ、４は半導体チップの電極、５は導電異
方性接着剤シート、６は導電性微粒子、７は液晶パネ
ル、８はシール部、９は液晶層、１０は液晶駆動用電
極、１１は接着剤シートを示す。In FIG. 1, 1 is a glass substrate as a substrate, 2 is a wiring pattern on the glass substrate, 3 is a semiconductor chip as an electric element, 4 is an electrode of the semiconductor chip, 5 is a conductive anisotropic adhesive sheet, 6 Denotes conductive fine particles, 7 denotes a liquid crystal panel, 8 denotes a seal portion, 9 denotes a liquid crystal layer, 10 denotes a liquid crystal driving electrode, and 11 denotes an adhesive sheet.
【００１６】第１図（ａ）は複数個の突起電極を有する
電気素子たる半導体チップと、これに対応する複数の配
線パターンが形成された液晶パネルのガラス基板の一部
の接合前の断面図を示す。この配線バターンの一部は液
晶パネルの液晶駆動用電極と電気的に結びついているも
のである。FIG. 1A is a cross-sectional view of a part of a glass substrate of a liquid crystal panel on which a semiconductor chip as an electric element having a plurality of projecting electrodes and a plurality of wiring patterns corresponding thereto are formed before bonding. Is shown. A part of this wiring pattern is electrically connected to a liquid crystal driving electrode of the liquid crystal panel.
【００１７】第１図（ｂ）は、上記基板たるガラス基板
の上に配された配線パターン部上に導電性微粒子を拡散
・混在させた薄い導電異方性接着剤シートと、非導電性
の接着剤シートを載置したものであり、上記非導電性の
接着剤シートは上記電気素子の突起電極と上記基板の配
線パターンの対応部位を除いて配されている。導電性粒
子の粒径は上記薄い導電異方性接着剤シートの厚さとほ
ぼ同等にしてある。FIG. 1 (b) shows a thin conductive anisotropic adhesive sheet in which conductive fine particles are diffused and mixed on a wiring pattern portion arranged on the glass substrate as the substrate, and a non-conductive anisotropic adhesive sheet. An adhesive sheet is placed, and the non-conductive adhesive sheet is disposed except for a portion corresponding to the protruding electrode of the electric element and the wiring pattern of the substrate. The particle size of the conductive particles is substantially equal to the thickness of the thin conductive anisotropic adhesive sheet.
【００１８】第１図（ｃ）は半導体チップを上記導電異
方性の接着剤シートと非導電性の接着剤シートを介し
て、ガラス基板上に常温下で押しつけているものであ
り、半導体チップの突起電極とガラス基板の配線パター
ンと平面的に位置があっている。上記導電異方性接着剤
シートは薄い為、半導体チップをガラス基板に押しつけ
ると、半導体チップの突起電極とガラス基板の配線パタ
ーンは電気的導通状態にする事ができる。この状態で外
部から駆動信号を半導体チップひいてはガラス基板に入
力してやれば、液晶パネルを駆動して検査する事ができ
る。FIG. 1 (c) shows a semiconductor chip pressed at room temperature on a glass substrate via the above-mentioned conductive anisotropic adhesive sheet and non-conductive adhesive sheet. And the wiring pattern on the glass substrate are planarly aligned. Since the conductive anisotropic adhesive sheet is thin, when the semiconductor chip is pressed against the glass substrate, the protruding electrodes of the semiconductor chip and the wiring pattern of the glass substrate can be electrically connected. In this state, if a driving signal is externally input to the semiconductor chip and thus to the glass substrate, the liquid crystal panel can be driven and inspected.
【００１９】さらに第１図（ｄ）は、第１図（ｃ）の工
程において検査合格となったものについて、半導体チッ
プの上から加熱しながら加圧し、接着剤層を硬化させ
て、半導体チップとガラス基板を強固に接合、固定した
ものである。この時、半導体チップの突起電極とガラス
基板の配線パターンは導電性微粒子を介して電気的導通
状態にある。Further, FIG. 1 (d) shows a semiconductor chip which passes the inspection in the step of FIG. 1 (c) while being heated and pressurized from above the semiconductor chip to cure the adhesive layer. And the glass substrate are firmly joined and fixed. At this time, the protruding electrodes of the semiconductor chip and the wiring pattern of the glass substrate are in an electrically conductive state via the conductive fine particles.
【００２０】導電異方性接着剤シートは薄いので、導電
異方性接着剤シートのみで半導体チップとガラス基板を
接合した場合、総接着剤量が足りず、半導体チップとガ
ラス基板の間に接着剤が充分充填されず大きな気泡ある
いはすきまが残ってしまう。その結果、電気素子のガラ
ス基板への接合強度が弱い、電気素子の突起電極とガラ
ス基板の配線パターンとの間の電気的導通の接続信頼性
の低下等の問題が起こるものであった。Since the conductive anisotropic adhesive sheet is thin, when the semiconductor chip and the glass substrate are joined only with the conductive anisotropic adhesive sheet, the total adhesive amount is insufficient, and the adhesive is applied between the semiconductor chip and the glass substrate. The agent is not sufficiently filled, leaving large air bubbles or gaps. As a result, there have been problems such as a low bonding strength of the electric element to the glass substrate and a reduction in connection reliability of electrical conduction between the projecting electrode of the electric element and the wiring pattern of the glass substrate.
【００２１】本発明においては、薄い導電異方性接着剤
シールと重ね合わせて非導電性の接着剤シートがあり、
この非導電性の接着剤シートは電気素子の突起電極部を
除いて配されている為、電気素子の突起電極とガラス基
板の配線パターンの電気的導通を容易に確保した上で、
電気素子たる半導体チップとガラス基板の間の総接着剤
量を充分に確保して充填し、気泡を抱き込む事なく、半
導体チップをガラス基板の上に接合することができるも
のであり、その結果、半導体チップのガラス基板への接
合強度を向上させ、半導体チップの突起電極とガラス基
板配線パターンとの間の電気的導通の接続信頼性を極め
て向上させるものである。In the present invention, there is a non-conductive adhesive sheet superimposed on a thin conductive anisotropic adhesive seal,
Since this non-conductive adhesive sheet is disposed except for the protruding electrode portion of the electric element, the electric conduction between the protruding electrode of the electric element and the wiring pattern of the glass substrate is easily ensured.
The semiconductor chip can be bonded onto the glass substrate without entrapping air bubbles by filling and securing the total amount of adhesive between the semiconductor chip as an electric element and the glass substrate. Another object of the present invention is to improve the bonding strength of a semiconductor chip to a glass substrate and significantly improve the reliability of electrical connection between the protruding electrode of the semiconductor chip and the wiring pattern of the glass substrate.
【００２２】第１図（ｄ）においては、第１図（ｃ）に
おいて半導体チップとガラス基板を位置合わせしたもの
をそのまま加熱加圧する為、煩雑で作業工数の大きな位
置合わせ工程が、全工程で一回ですむ為製造コストが少
なくてすむものである。In FIG. 1 (d), since the semiconductor chip and the glass substrate aligned in FIG. 1 (c) are heated and pressed as they are, a complicated and large number of steps are required in all the steps. Since it only needs to be performed once, the manufacturing cost is low.
【００２３】さらに、本発明による電気素子の接続構造
は第１図（ｃ）の検査の後、合格の品物のみを第１図
（ｄ）の様に加熱加圧して接着剤層を硬化させれば、接
合後の良品率もおのずと向上するものである。従って剥
離再生の必要性も極端に低減され、作業の効率も極めて
向上するものである。Further, in the connection structure of the electric element according to the present invention, after the inspection of FIG. 1 (c), only the passed products are heated and pressed as shown in FIG. 1 (d) to cure the adhesive layer. If this is the case, the non-defective rate after joining naturally increases. Therefore, the necessity of peeling and regenerating is extremely reduced, and the working efficiency is extremely improved.
【００２４】[0024]
【発明の効果】本発明は以上説明したように、電気素子
と基板の間に薄い導電異方性接着剤層と非導電性の接着
剤を二重に形成することによって、電気素子と基板を初
期的な電気的接続状態にして検査をする事を可能にし
て、位置合わせ工数を低減し、剥離再生必要な確立を低
減させ、さらには接者強度を向上させて、接続信頼性を
向上させる効果がある。According to the present invention, as described above, the electric element and the substrate are formed by forming a thin conductive anisotropic adhesive layer and a non-conductive adhesive between the electric element and the substrate. It is possible to conduct inspections in the initial electrical connection state, reduce the number of alignment steps, reduce the need for peeling and regeneration, and further improve the contact strength and improve connection reliability effective.
【図１】（ａ）〜（ｄ）は、本発明による電気素子の接
続構造を示す図。1A to 1D are views showing a connection structure of an electric element according to the present invention.
【図２】（ａ）〜（ｃ）は、従来の電気素子の接続構造
を示す図。FIGS. 2A to 2C are diagrams showing a conventional connection structure of an electric element.
１・・・ガラス基板 ２・・・配線パターン ３・・・半導体チップ ４・・・突起電極 ５・・・導電性接着剤シート ６・・・導電性微粒子 ７・・・液晶パネル ８・・・シール部 ９・・・液晶層 １０・・・液晶駆動用電極 １１・・・接着剤シート ２１・・・基板 ２２・・・配線パターン ２３・・・電気素子 ２４・・・電極 ２５・・・検査用プローバ ２６・・・接着剤シート ２７・・・導電性粒子 DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Wiring pattern 3 ... Semiconductor chip 4 ... Protruding electrode 5 ... Conductive adhesive sheet 6 ... Conductive fine particles 7 ... Liquid crystal panel 8 ... Seal part 9 ... Liquid crystal layer 10 ... Liquid crystal drive electrode 11 ... Adhesive sheet 21 ... Substrate 22 ... Wiring pattern 23 ... Electric element 24 ... Electrode 25 ... Inspection Prober 26 ... adhesive sheet 27 ... conductive particles
Claims (2)
極を有した電気素子とを、前記基板上に形成された導電
性微粒子を含む第１の接着剤層と、当該第１の接着剤層
上であって前記電気素子の前記複数の電極と前記基板の
前記配線パターンの対応部位を除いた前記電気素子の前
記電極の間に形成された第２の接着剤層とを介在して接
合する電気素子の接続方法であって、 前記電気素子を常温下で前記基板上に押しつけて前記配
線パターンと前記電気素子の前記複数の電極とを前記第
１の接着剤層を介して電気的接続する工程と、前記配線
パターン及び前記電気素子に駆動信号を入力することに
よって検査を行う工程と、 しかる後に前記電気素子を上から加熱及び加圧して前記
第１の接着剤層と前記第２の接着剤層を硬化させ、前記
電気素子を前記基板に接合する工程と、を有することを
特徴とする電気素子の接続方法。A first adhesive layer containing conductive fine particles formed on the substrate, the first adhesive layer including conductive fine particles, and the first adhesive layer; A second adhesive layer formed on a layer and between the electrodes of the electric element except for the corresponding portions of the wiring pattern on the substrate and the plurality of electrodes of the electric element, and joined together A method of connecting the electrical element to the wiring pattern and the plurality of electrodes of the electrical element via the first adhesive layer by pressing the electrical element onto the substrate at room temperature. Performing a test by inputting a drive signal to the wiring pattern and the electric element. Thereafter, the electric element is heated and pressed from above to apply the first adhesive layer and the second Curing the adhesive layer, Method for connecting an electrical device characterized by having the steps of bonding to the substrate.
極を有した半導体チップとを、前記基板上に形成された
導電性微粒子を含む第１の接着剤層と、当該第１の接着
剤層上であって前記半導体チップの前記複数の電極と前
記基板の前記配線パターンの対応部位を除いた前記半導
体チップの前記電極の間に形成された第２の接着剤層と
を介在して接合する液晶パネルの製造方法であって、 前記半導体チップを常温下で前記基板上に押しつけて前
記配線パターンと前記半導体チップの前記複数の電極と
を前記第１の接着剤層を介して電気的接続する工程と、 前記配線パターン及び前記半導体チップに駆動信号を入
力することによって検査を行う工程と、 しかる後に前記半導体チップを上から加熱及び加圧して
前記第１の接着剤層と前記第２の接着剤層を硬化させ、
前記半導体チップを前記基板に接合する工程と、を有す
ることを特徴とする液晶パネルの製造方法。2. A first adhesive layer containing conductive fine particles formed on a substrate on which a wiring pattern is formed and a semiconductor chip having a plurality of electrodes, said first adhesive layer comprising conductive fine particles formed on said substrate. Bonding via a second adhesive layer formed on the layer and between the plurality of electrodes of the semiconductor chip and the electrodes of the semiconductor chip excluding a portion corresponding to the wiring pattern of the substrate; A method of manufacturing a liquid crystal panel, wherein the semiconductor chip is pressed onto the substrate at room temperature to electrically connect the wiring pattern and the plurality of electrodes of the semiconductor chip via the first adhesive layer. Performing a test by inputting a drive signal to the wiring pattern and the semiconductor chip; and then, heating and pressing the semiconductor chip from above to apply the first adhesive layer and the second Chakuzaiso to cure the,
Bonding the semiconductor chip to the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8695199A JP3316472B2 (en) | 1999-03-29 | 1999-03-29 | Method of connecting electric element and method of manufacturing liquid crystal panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8695199A JP3316472B2 (en) | 1999-03-29 | 1999-03-29 | Method of connecting electric element and method of manufacturing liquid crystal panel |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02191221A Division JP3112470B2 (en) | 1990-07-19 | 1990-07-19 | Connection structure of electric element and liquid crystal panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11330153A JPH11330153A (en) | 1999-11-30 |
| JP3316472B2 true JP3316472B2 (en) | 2002-08-19 |
Family
ID=13901191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8695199A Expired - Fee Related JP3316472B2 (en) | 1999-03-29 | 1999-03-29 | Method of connecting electric element and method of manufacturing liquid crystal panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3316472B2 (en) |
-
1999
- 1999-03-29 JP JP8695199A patent/JP3316472B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11330153A (en) | 1999-11-30 |
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