JPH0897256A - Method of mounting electronic part - Google Patents

Method of mounting electronic part

Info

Publication number
JPH0897256A
JPH0897256A JP25728394A JP25728394A JPH0897256A JP H0897256 A JPH0897256 A JP H0897256A JP 25728394 A JP25728394 A JP 25728394A JP 25728394 A JP25728394 A JP 25728394A JP H0897256 A JPH0897256 A JP H0897256A
Authority
JP
Japan
Prior art keywords
wiring
conductive particles
joining
glass substrate
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25728394A
Other languages
Japanese (ja)
Inventor
Masayasu Kizaki
正康 木崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP25728394A priority Critical patent/JPH0897256A/en
Publication of JPH0897256A publication Critical patent/JPH0897256A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive

Abstract

PURPOSE: To provide a method of mounting an electronic part capable of detecting any defective electronic part and defective connection as well as easily removing electronic part. CONSTITUTION: Conductive particles 13 whereon a thin thermoplastic bonding agent layer 17 is formed are dispersed on a glass substrate 12, a semiconductor chip 19 is put thereon in place. Later, an Au layer 16 is exposed from the thermoplastic bonding agent layer 17 by heating and pressing steps so as to make a bump electrode 18 and an ITO wiring 11 conductive. At this time, since the thermoplastic bonding agent layer 17 supports the semiconductor chip 19 and the glass substrate 12 by feeble bonding force, the conduction test, etc., can be performed in such a state thereby enabling the electronic parts to be rebonded. In such a state, when an insulating resin is injected between the semiconductor chip 19 and the glass substrate 12, both elements can be bonded together.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、電子部品の接合方法
に関し、さらに詳しくは、配線基板に導電性粒子を用い
て電子部品を電気的に接続された状態で接合させる方法
に係る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for joining electronic components, and more particularly to a method for joining electronic components to a wiring board in a state where they are electrically connected by using conductive particles.

【0002】[0002]

【従来の技術】従来、この種の電子部品の接合方法とし
ては、図8に示すように導電性粒子1を熱硬化性接着剤
2に混ぜてなる異方性導電接着剤3を用いて接合させる
技術が知られている。この方法は、まず配線パターン5
が形成された配線基板4を用意し、図8(A)に示すよ
うに、この基板4におけるICチップを接合(搭載)す
る領域に異方性導電接着剤3を転写する。次に、図8
(B)に示すようにICチップ6の突起電極7が配線パ
ターン5と異方性導電接着剤3を介して対向するよう
に、配線基板4とICチップ6とを重ね合わせる。そし
て、ICチップ6を配線基板4側に押圧しながら熱処理
を施し、熱硬化性接着剤2を硬化させることにより配線
基板4にICチップ6を一体的に接合させるとともに導
電粒子1を介して配線基板4の配線パターンとICチッ
プ6の突起電極7とを電気的に接続させている。また、
このような方法は、半導体チップを搭載したテープキャ
リアパッケージ(TCP)等の電子部品の外部接続用端
子と配線基板の配線パターンとを、異方性導電接着剤を
介して接続させて、しかもテープキャリアパッケージと
配線基板とを一体的に接合する場合などにも用いられて
いる。
2. Description of the Related Art Conventionally, as a method for joining electronic components of this type, as shown in FIG. 8, an anisotropic conductive adhesive 3 made by mixing conductive particles 1 with a thermosetting adhesive 2 is used for bonding. Techniques for making them known are known. This method starts with wiring pattern 5
The wiring substrate 4 having the wirings formed therein is prepared, and as shown in FIG. 8A, the anisotropic conductive adhesive 3 is transferred to the region of the substrate 4 where the IC chip is bonded (mounted). Next, FIG.
As shown in (B), the wiring board 4 and the IC chip 6 are superposed so that the protruding electrodes 7 of the IC chip 6 face the wiring pattern 5 via the anisotropic conductive adhesive 3. Then, heat treatment is performed while pressing the IC chip 6 toward the wiring board 4 side, and the thermosetting adhesive 2 is hardened to integrally bond the IC chip 6 to the wiring board 4 and to wire via the conductive particles 1. The wiring pattern of the substrate 4 and the protruding electrodes 7 of the IC chip 6 are electrically connected. Also,
In such a method, an external connection terminal of an electronic component such as a tape carrier package (TCP) on which a semiconductor chip is mounted and a wiring pattern of a wiring board are connected via an anisotropic conductive adhesive, and a tape is used. It is also used when integrally bonding a carrier package and a wiring board.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の接合方法では、異方性導電接着剤3が熱硬化
性接着剤2に導電性粒子1を混ぜたものであるため、接
合のために一旦接着してしまうと接着強度が大きくな
り、そのため接合時にICチップ6の動作不良や接続不
良などが生じた場合に、ICチップ6を配線基板から剥
離することが困難となる問題があった。特に、熱硬化性
接着剤2を用いているため、この接着剤を加熱して溶融
(流動)させる方法が使えず、機械的にICチップ6を
剥離した場合、ともすると、ICチップ6や配線基板4
を損傷する問題があった。また、このような損傷を免れ
てICチップ6を剥離することができたとしても、図9
に示すように配線パターン5や突起電極7の表面に熱硬
化性接着剤2や導電性粒子1が残存することによって、
ICチップ6や配線基板4を再生することができなくな
る問題があった。この発明が解決しようとする課題は、
電子部品の動作不良や接続不良が生じている場合に容易
に電子部品の交換や接続のやり直しができる、実装歩留
まりのよい電子部品の接合方法を得るにはどのような手
段を講じればよいかという点にある。
However, in such a conventional joining method, since the anisotropic conductive adhesive 3 is a mixture of the thermosetting adhesive 2 and the conductive particles 1, the anisotropic bonding adhesive 3 is used for joining. Once adhered, the adhesive strength becomes large, and therefore, when the IC chip 6 malfunctions or the connection fails at the time of bonding, there is a problem that it is difficult to peel the IC chip 6 from the wiring board. . In particular, since the thermosetting adhesive 2 is used, the method of heating (melting) this adhesive cannot be used, and when the IC chip 6 is mechanically peeled off, the IC chip 6 and the wiring may be removed. Board 4
There was a problem to damage. In addition, even if the IC chip 6 can be peeled off by avoiding such damage, as shown in FIG.
As shown in, the thermosetting adhesive 2 and the conductive particles 1 remain on the surface of the wiring pattern 5 and the protruding electrodes 7,
There is a problem that the IC chip 6 and the wiring board 4 cannot be regenerated. The problem to be solved by this invention is
What measures should be taken to obtain a bonding method for electronic components that allows easy replacement of electronic components and reconnection of electronic components when malfunctions or poor connection of electronic components occur and that has a good mounting yield In point.

【0004】[0004]

【課題を解決するための手段】そこで、請求項1記載の
発明は、少なくとも配線基板の配線パターンもしくは電
子部品の接続部上に、表面に接着剤層を設けた導電性粒
子を配置させる工程と、前記配線基板の配線パターンと
前記電子部品の接続部とを前記導電性粒子を介して重ね
合わせ、加熱及び加圧を行って該導電性粒子を介して前
記配線パターンと前記接続部とを電気的に接続させる仮
接合工程と、前記導電性粒子を介して接続された前記配
線パターンと前記接続部との間に、絶縁性樹脂を配設す
る本接合工程と、を備えることを、その解決手段として
いる。
Therefore, the invention according to claim 1 comprises a step of disposing conductive particles having an adhesive layer on the surface thereof, at least on a wiring pattern of a wiring board or a connection portion of an electronic component. A wiring pattern of the wiring board and a connecting portion of the electronic component are superposed on each other via the conductive particles, and heating and pressing are performed to electrically connect the wiring pattern and the connecting portion via the conductive particles. The provision of a temporary joining step of electrically connecting and a main joining step of disposing an insulating resin between the wiring pattern and the connection portion connected via the conductive particles is solved. As a means.

【0005】また、請求項2記載の発明は、前記仮接合
工程を行った後、前記本接合工程の前に、前記配線パタ
ーンと前記接続部との間の電気的導通もしくは前記電子
部品の動作を検査し、前記検査の結果不良が検出された
場合、前記電子部品を前記配線基板から剥離して、良品
として検出されるまで再度上記仮接合工程までを繰り返
す検査リペア工程を備えることを特徴としている。さら
に、請求項記載の発明は、前記絶縁性樹脂は熱硬化性樹
脂でなり、加熱により硬化することを特徴とすることを
特徴としている。
According to the second aspect of the invention, after the temporary joining step is performed and before the main joining step, electrical continuity between the wiring pattern and the connection portion or operation of the electronic component is performed. In the case where a defective product is detected as a result of the inspection, the electronic component is separated from the wiring board, and an inspection repair process is repeated until the temporary bonding process is repeated until a defective product is detected. There is. Further, the invention according to claim is characterized in that the insulating resin is a thermosetting resin and is cured by heating.

【0006】さらに、請求項4記載の発明は、前記接着
剤層が熱可塑性を有することを特徴としている。請求項
5記載の発明は、前記電子部品が半導体チップであるこ
とを特徴としている。請求項6記載の発明は、前記配線
基板が液晶表示装置のガラス基板であり、前記配線パタ
ーンが透明配線なることを特徴としている。また、請求
項7記載の発明は、前記配線基板が液晶表示装置のガラ
ス基板であり、前記配線パターンが透明配線でなる場合
に、前記絶縁性樹脂をUV硬化性樹脂となし、前記ガラ
ス基板の裏面側からUV露光されることにより硬化する
ことを特徴としている。
Further, the invention according to claim 4 is characterized in that the adhesive layer has thermoplasticity. According to a fifth aspect of the invention, the electronic component is a semiconductor chip. According to a sixth aspect of the invention, the wiring board is a glass substrate of a liquid crystal display device, and the wiring pattern is a transparent wiring. In the invention according to claim 7, when the wiring substrate is a glass substrate of a liquid crystal display device and the wiring pattern is a transparent wiring, the insulating resin is a UV curable resin, It is characterized by being cured by being exposed to UV from the back side.

【0007】[0007]

【作用】この発明においては、少なくとも配線基板の配
線パターンもしくは電子部品の接続部の上に、表面に接
着剤層を設けた導電性粒子を配置し、配線基板の配線パ
ターンと電子部品の接続部とを重ね合わせ、加熱及び加
圧を行うことにより、接着剤層は流動化し配線パターン
及び接続部に導電性粒子が直接接触する。また、流動化
した接着剤は導電性粒子が配線パターンと接続部とに接
触した状態で、配線基板と電子部品とを仮接合する。こ
の状態では、仮接合されているため、電子部品側と配線
基板側とが電気的に接続しているかどうかの検査や、電
子部品の動作不良の有無を判別する検査を行うことが可
能となる。このような検査によって不良が認められた場
合、電子部品は導電性粒子の表面に設けられた薄い接着
剤層のみによって配線基板側に接合されているため接着
強度が微弱であり、電子部品を容易に剥離することがで
きる。また、この接着剤層に熱可塑性樹脂を用いれば、
加熱を行うことにより接着剤が流動化して電子部品をさ
らに容易に剥離することが可能となる。このように接着
剤層の接着強度が微弱なため、電子部品の剥離に伴って
電子部品や配線基板に損傷を与えることを防止できる。
そして、電子部品を剥離した後は、配線パターンや接続
部に付着している接着剤が少量であるため、電子部品や
配線基板を再生させることが容易となる。さらに、配線
基板が液晶表示装置のガラス基板であり、配線パターン
が透明基板でなる場合、本接合工程で用いる絶縁性樹脂
にUV硬化性樹脂を用いて裏面露光により硬化させるこ
とが可能となる。
According to the present invention, conductive particles having an adhesive layer on the surface thereof are disposed on at least the wiring pattern of the wiring board or the connection portion of the electronic component, and the connection portion between the wiring pattern of the wiring board and the electronic component is arranged. By overlapping and heating and pressing, the adhesive layer is fluidized and the conductive particles come into direct contact with the wiring pattern and the connecting portion. Further, the fluidized adhesive temporarily bonds the wiring board and the electronic component with the conductive particles in contact with the wiring pattern and the connecting portion. In this state, since the components are temporarily joined, it is possible to perform an inspection as to whether or not the electronic component side and the wiring board side are electrically connected, and an inspection for determining whether or not the electronic component is malfunctioning. . If a defect is found by such an inspection, the electronic component is bonded to the wiring board side only by the thin adhesive layer provided on the surface of the conductive particles, so the adhesive strength is weak and the electronic component is easily Can be peeled off. If a thermoplastic resin is used for this adhesive layer,
By heating, the adhesive fluidizes and the electronic component can be peeled off more easily. Since the adhesive strength of the adhesive layer is weak as described above, it is possible to prevent the electronic component and the wiring board from being damaged due to the peeling of the electronic component.
After the electronic component is peeled off, the amount of the adhesive attached to the wiring pattern and the connection portion is small, so that the electronic component and the wiring board can be easily regenerated. Furthermore, when the wiring substrate is a glass substrate of a liquid crystal display device and the wiring pattern is a transparent substrate, it is possible to cure the insulating resin used in the main bonding step by UV exposure using a UV curable resin by backside exposure.

【0008】[0008]

【実施例】以下、この発明に係る電子部品の接合方法の
詳細を図面に示す実施例に基づいて説明する。なお、本
実施例は、液晶表示装置のガラス基板上に半導体チップ
を接合する場合に本発明を適用した例である。まず、本
実施例では、図2に示すような配線パターンとしてのI
TO配線11が表面に形成された、配線基板としての、
液晶表示装置のガラス基板12を用意する。そして、同
図に示すように、ガラス基板12における半導体チップ
を接合する領域(ITO配線11も含む)の表面に導電
性粒子13を分散させる。この導電性粒子13の構造
は、図1に示すように、コアとなる微細な球状のポリス
チレン粒子14と、その表面に無電解メッキ法にて順次
形成されたニッケル(Ni)層15、金(Au)層16
と、金層16の表面に形成された、膜厚の薄いアクリル
樹脂などの熱可塑性樹脂からなる接着剤層17と、から
なる。また、この導電性粒子13をガラス基板12上に
配置させるには、導電性粒子13を例えばメチルアルコ
ール等の分散媒中に分散させたものをガラス基板12上
に塗布すればよく、分散媒が蒸発することによって導電
性粒子13のみがガラス基板上に配置される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method for joining electronic components according to the present invention will be described below with reference to the embodiments shown in the drawings. The present embodiment is an example in which the present invention is applied to the case where a semiconductor chip is bonded onto a glass substrate of a liquid crystal display device. First, in this embodiment, I as a wiring pattern as shown in FIG.
The TO wiring 11 is formed on the surface of the wiring board,
A glass substrate 12 of a liquid crystal display device is prepared. Then, as shown in the figure, the conductive particles 13 are dispersed on the surface of the region (including the ITO wiring 11) on the glass substrate 12 where the semiconductor chip is bonded. As shown in FIG. 1, the structure of the conductive particles 13 is such that fine spherical polystyrene particles 14 serving as a core, a nickel (Ni) layer 15 and a gold ( Au) layer 16
And an adhesive layer 17 formed on the surface of the gold layer 16 and made of a thermoplastic resin such as a thin acrylic resin. Further, in order to dispose the conductive particles 13 on the glass substrate 12, it is sufficient to coat the glass substrate 12 with the conductive particles 13 dispersed in a dispersion medium such as methyl alcohol. By evaporation, only the conductive particles 13 are placed on the glass substrate.

【0009】次に、図3に示すように、接続部としての
突起電極18が設けられた半導体チップ19を、ガラス
基板12の導電性粒子13を配置した領域に、突起電極
18とITO配線11とが対向するように位置合わせを
行って両者を重ね合わせる。この状態では、突起電極1
8とITO配線11との間に、導電性粒子13が複数介
在されているが接着は行われていない。続いて、半導体
チップ19の背面側から熱圧着ヘッド(図示省略する)
を押し当てて加熱及び加圧する仮接合工程を行う。な
お、ここで行う加熱の温度は、接着剤層17の膜厚が薄
いため軟化する程度の比較的低温でよく、また加圧圧力
も小さくてよい。これにより、図4に示すように、突起
電極18とITO配線11との間の導電性粒子13の接
着剤層17が押しつぶされる。このとき、図5に示すよ
うに、導電性粒子13表面の接着剤層17は熱軟化し、
突起電極18とITO配線11とに接着する。この接着
は、総接着面積が極めて小さいため微弱な接着力であ
る。このため、このような仮接合工程によって、導電性
粒子13の金層16が突起電極18とITO配線11と
に接触して電気的に接続された状態で上記した微弱な接
着力で保持される。
Next, as shown in FIG. 3, the semiconductor chip 19 provided with the protruding electrode 18 as a connecting portion is provided in the region of the glass substrate 12 where the conductive particles 13 are arranged, and the protruding electrode 18 and the ITO wiring 11 are formed. Position them so that and are opposite to each other, and overlap them. In this state, the protruding electrode 1
Although a plurality of conductive particles 13 are interposed between the electrode 8 and the ITO wiring 11, no bonding is performed. Then, a thermocompression bonding head (not shown) is applied from the back side of the semiconductor chip 19.
A temporary joining process of pressing and heating and pressing is performed. The heating temperature performed here may be a relatively low temperature at which the adhesive layer 17 is softened because it is thin, and the pressure applied may be low. As a result, as shown in FIG. 4, the adhesive layer 17 of the conductive particles 13 between the protruding electrode 18 and the ITO wiring 11 is crushed. At this time, as shown in FIG. 5, the adhesive layer 17 on the surface of the conductive particles 13 is thermally softened,
It adheres to the protruding electrode 18 and the ITO wiring 11. This adhesion is a weak adhesion because the total adhesion area is extremely small. Therefore, by such a temporary bonding process, the gold layer 16 of the conductive particles 13 is held by the above-mentioned weak adhesive force in a state where the gold layer 16 of the conductive particles 13 is in contact with and electrically connected to the protruding electrode 18 and the ITO wiring 11. .

【0010】このように半導体チップ19をガラス基板
12に仮接合させた状態とすることにより、後記する本
接合工程の前に、検査リペア工程として、突起電極18
とITO配線11との間の電気的導通を検査することが
可能となるとともに、半導体チップ19をガラス基板1
2から剥離困難な状態にする前に再度仮接合工程までを
やり直すことができる。即ち、検査リペア工程におい
て、検査の結果、突起電極18とITO配線11との間
が電気的に非導通である場合は、図6に示すように半導
体チップ19をガラス基板12から剥離し、その後半導
体チップ19とガラス基板12とを例えばアセトン等の
溶剤を用いて洗浄して導電性粒子13を除去する。次
に、再度ガラス基板12へ導電性粒子13を分散して配
置させ、半導体チップ19を重ね合わせる。その後、半
導体チップ19を同様に加熱及び加圧して再度仮接合さ
せる。
By thus preliminarily bonding the semiconductor chip 19 to the glass substrate 12, the protruding electrode 18 is provided as an inspection repair process before the main bonding process described later.
It becomes possible to inspect the electrical continuity between the ITO wiring 11 and the ITO wiring 11, and the semiconductor chip 19 is attached to the glass substrate 1.
It is possible to repeat the process of temporary joining again before changing from 2 to a state in which peeling is difficult. That is, in the inspection repair step, when the result of the inspection shows that the protruding electrode 18 and the ITO wiring 11 are not electrically connected to each other, the semiconductor chip 19 is separated from the glass substrate 12 as shown in FIG. The semiconductor chip 19 and the glass substrate 12 are washed with a solvent such as acetone to remove the conductive particles 13. Next, the conductive particles 13 are dispersed and arranged again on the glass substrate 12, and the semiconductor chips 19 are stacked. After that, the semiconductor chip 19 is heated and pressed in the same manner to temporarily bond again.

【0011】なお、導電性粒子13は、上記したように
半導体チップ19側及びガラス基板12側に熱可塑性接
着剤の微弱な接着力のみで付着している。このため、導
電性粒子13の除去方法は、上記洗浄の他、機械的な除
去方法を用いることも可能である。さらに、仮接合した
状態では、上記した導通検査の他に、半導体チップ19
側の動作不良の有無や、ガラス基板12側の液晶表示装
置の動作不良の有無などの検査を行うことができる。こ
れらの検査により不良の存在が検出された場合は、半導
体チップ19や、ガラス基板12を交換して再度仮接合
工程までをやり直せばよい。
The conductive particles 13 are attached to the semiconductor chip 19 side and the glass substrate 12 side only by the weak adhesive force of the thermoplastic adhesive as described above. Therefore, as the method for removing the conductive particles 13, a mechanical removal method can be used in addition to the above cleaning. Further, in the temporarily joined state, in addition to the above-mentioned continuity test, the semiconductor chip 19
It is possible to inspect whether there is a malfunction in the liquid crystal display device on the glass substrate 12 side or not. If the presence of defects is detected by these inspections, the semiconductor chip 19 and the glass substrate 12 may be replaced and the temporary bonding process may be performed again.

【0012】次に、上記した検査を経て不良が検出され
ない仮接合されたもの又は不良が解消した仮接合された
ものに対しては、図7に示すように、半導体チップ19
とガラス基板12との間隙に例えばエポキシ樹脂などの
熱硬化性樹脂からなる絶縁性樹脂20を注入する本接合
工程を行う。なお、この本接合工程では、少なくとも導
電性粒子13を介して接続された突起電極18とITO
配線11との周囲に絶縁性樹脂20を配設させ、十分な
強度を有する接着を行う。このようにして、導通不良等
のない電子部品の接合(実装)を行うことができる。
Next, as shown in FIG. 7, the semiconductor chip 19 is provided for the temporarily bonded product in which no defect is detected through the above-described inspection or the temporarily bonded product in which the defect is eliminated.
The main bonding step of injecting the insulating resin 20 made of a thermosetting resin such as epoxy resin into the gap between the glass substrate 12 and the glass substrate 12 is performed. In this main joining step, the protruding electrode 18 and the ITO that are connected at least through the conductive particles 13 are connected.
An insulating resin 20 is arranged around the wiring 11 and is bonded with sufficient strength. In this way, the electronic components can be joined (mounted) without a conduction failure or the like.

【0013】本実施例においては、電気的な導通を得な
がらも、導電性粒子13の接着剤層17の微弱な接着力
で半導体チップ19とガラス基板12とを一時的に保持
したことにより、半導体チップ19、液晶表示装置など
の不良や、突起電極18とITO配線11との間の接続
不良などが生じた場合に、半導体チップ19の剥離が容
易に行え、ガラス基板12や半導体チップ19の再生が
可能となる。このため、仮接合の状態で、電子部品の不
良や接続不良が生じた場合に容易に電子部品の交換や接
続のやり直しを行うことが可能となり、実装歩留りを向
上させることができる。
In this embodiment, the semiconductor chip 19 and the glass substrate 12 are temporarily held by the weak adhesive force of the adhesive layer 17 of the conductive particles 13 while obtaining electrical continuity. When the semiconductor chip 19, the liquid crystal display device, or the like is defective, or the connection between the protruding electrode 18 and the ITO wiring 11 is defective, the semiconductor chip 19 can be easily peeled off, and the glass substrate 12 or the semiconductor chip 19 can be easily separated. Playback is possible. For this reason, when a defective electronic component or a defective connection occurs in the temporarily joined state, the electronic component can be easily replaced or the connection can be redone, and the mounting yield can be improved.

【0014】なお、本実施例では、本接合工程で熱硬化
性樹脂を絶縁性樹脂として用いたが、配線基板がガラス
基板12であり、且つ配線パターンがITO配線11で
あるため、熱硬化性樹脂に代えてUV(紫外光)硬化性
樹脂を用い、ガラス基板12の下面(裏面)側からUV
露光を行ってもよい。このようにUV硬化性樹脂を用い
ると、熱硬化性樹脂と異なり加熱を行わずに済むという
利点がある。
In this embodiment, the thermosetting resin is used as the insulating resin in the main joining process, but since the wiring substrate is the glass substrate 12 and the wiring pattern is the ITO wiring 11, the thermosetting resin is used. UV (ultraviolet light) curable resin is used instead of resin, and UV is applied from the lower surface (back surface) side of the glass substrate 12.
Exposure may be performed. As described above, the use of the UV curable resin has an advantage that heating is not required unlike the thermosetting resin.

【0015】以上、実施例について説明したが、本発明
はこれに限定されるものではなく、構成の要旨に付随す
る各種の設計変更が可能である。例えば、上記実施例に
おいては、配線基板としてガラス基板12を用いたが、
他の材料でなる各種の配線基板を適用することができ
る。上記実施例では、導電性粒子13のコア材がポリス
チレン粒子14であるが、フェノール樹脂やアクリル樹
脂等の適度の硬度を有するものであればよい。また、コ
ア材の表面に形成する導電性材料層も上記実施例のよう
にニッケル層15、金層16などに限定されるものでは
ない。さらに、導電性粒子13の表面には、接着剤層と
してアクリルなどの熱可塑性樹脂からなる接着剤層17
を設けたが、熱可塑性を持たない接着剤でもよい。要
は、一時的に電子部品と配線基板とを接合させることが
でき、電子部品を剥離した後の洗浄等により除去が容易
な接着剤であればよい。さらに、上記実施例では、ガラ
ス基板12上に導電性粒子13を分散、配置させたが、
導電性粒子13を均一に配置できれば、半導体チップ1
9側もしくはガラス基板12と半導体チップ19との両
側に配置しても勿論よい。またさらに、上記実施例で
は、半導体チップ19をガラス基板12上に直接接続し
たが、テープキャリアパッケージ(TCP)の外部端子
や、その他の電子部品の電極を接続する場合にも本発明
を適用することができる。
Although the embodiment has been described above, the present invention is not limited to this, and various design changes accompanying the gist of the configuration can be made. For example, although the glass substrate 12 is used as the wiring substrate in the above embodiment,
Various wiring boards made of other materials can be applied. In the above embodiment, the core material of the conductive particles 13 is the polystyrene particles 14, but any material having appropriate hardness such as phenol resin or acrylic resin may be used. Further, the conductive material layer formed on the surface of the core material is not limited to the nickel layer 15, the gold layer 16 and the like as in the above embodiment. Further, on the surface of the conductive particles 13, an adhesive layer 17 made of a thermoplastic resin such as acrylic is used as an adhesive layer.
However, an adhesive having no thermoplasticity may be used. In short, an adhesive that can temporarily bond the electronic component and the wiring board and that can be easily removed by washing after peeling the electronic component may be used. Further, in the above-mentioned embodiment, the conductive particles 13 are dispersed and arranged on the glass substrate 12,
If the conductive particles 13 can be uniformly arranged, the semiconductor chip 1
Of course, they may be arranged on the 9 side or both sides of the glass substrate 12 and the semiconductor chip 19. Furthermore, in the above embodiment, the semiconductor chip 19 is directly connected to the glass substrate 12, but the present invention is also applied to the case of connecting an external terminal of a tape carrier package (TCP) or an electrode of another electronic component. be able to.

【0016】[0016]

【発明の効果】以上の説明から明らかなように、この発
明によれば、電子部品の動作不良や、接続不良などが生
じた場合に、電子部品の剥離が容易に行え、配線基板や
電子部品の再生を可能にする効果を奏する。また、最終
的に接合するための絶縁性樹脂を例えばUV硬化性樹脂
とすれば、加熱工程を削減できる利点がある。
As is apparent from the above description, according to the present invention, the electronic component can be easily peeled off when the electronic component malfunctions, the connection is defective, etc., and the wiring board and the electronic component are easily separated. Has the effect of enabling the reproduction of. Further, if the insulating resin for final bonding is, for example, a UV curable resin, there is an advantage that the heating process can be reduced.

【0017】[0017]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例で用いた導電性粒子の断面図。FIG. 1 is a cross-sectional view of conductive particles used in an example of the present invention.

【図2】本発明の実施例における導電性粒子の分散工程
を示す断面図。
FIG. 2 is a cross-sectional view showing a step of dispersing conductive particles in an example of the present invention.

【図3】本発明の実施例における半導体チップをガラス
基板に載せた状態を示す断面図。
FIG. 3 is a sectional view showing a state in which a semiconductor chip according to an embodiment of the present invention is placed on a glass substrate.

【図4】本発明の実施例における仮接合工程を示す断面
図。
FIG. 4 is a cross-sectional view showing a temporary joining step in the example of the present invention.

【図5】本発明の実施例における仮接合状態を示す要部
断面図。
FIG. 5 is a cross-sectional view of essential parts showing a temporarily joined state in the example of the present invention.

【図6】本発明の実施例における半導体チップの剥離工
程を示す断面図。
FIG. 6 is a cross-sectional view showing a step of peeling a semiconductor chip according to an example of the present invention.

【図7】本発明の実施例における本接合工程を示す断面
図。
FIG. 7 is a cross-sectional view showing a main joining step in the example of the present invention.

【図8】(A)及び(B)は従来の接合方法を示す断面
図。
8A and 8B are cross-sectional views showing a conventional joining method.

【図9】従来例の問題点を示す断面図。FIG. 9 is a cross-sectional view showing a problem of the conventional example.

【符号の説明】[Explanation of symbols]

11 ITO配線(配線パターン) 12 ガラス基板(配線基板) 13 導電性粒子 15 ニッケル層 16 金層 17 熱可塑性接着剤 18 突起電極(接続部) 19 半導体チップ(電子部品) 20 絶縁性樹脂 11 ITO Wiring (Wiring Pattern) 12 Glass Substrate (Wiring Substrate) 13 Conductive Particles 15 Nickel Layer 16 Gold Layer 17 Thermoplastic Adhesive 18 Projection Electrode (Connecting Part) 19 Semiconductor Chip (Electronic Component) 20 Insulating Resin

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも配線基板の配線パターンもし
くは電子部品の接続部上に、表面に接着剤層を設けた導
電性粒子を配置させる工程と、 前記配線基板の配線パターンと前記電子部品の接続部と
を前記導電性粒子を介して重ね合わせ、加熱及び加圧を
行って該導電性粒子を介して前記配線パターンと前記接
続部とを電気的に接続させる仮接合工程と、 前記導電性粒子を介して接続された前記配線パターンと
前記接続部との間に、絶縁性樹脂を配設する本接合工程
と、を備えることを特徴とする電子部品の接合方法。
1. A step of disposing conductive particles having an adhesive layer on a surface thereof at least on a wiring pattern of a wiring board or a connection portion of an electronic component, and a connection portion between the wiring pattern of the wiring substrate and the electronic component. And superimposing via the conductive particles, a temporary bonding step of electrically connecting the wiring pattern and the connection portion through the conductive particles by heating and pressing, and the conductive particles. A main joining step of disposing an insulating resin between the wiring pattern and the connection portion connected via the joining method.
【請求項2】 前記仮接合工程を行った後、前記本接合
工程の前に、前記配線パターンと前記接続部との間の電
気的導通もしくは前記電子部品の動作を検査し、前記検
査の結果不良が検出された場合、前記電子部品を前記配
線基板から剥離して、良品として検出されるまで再度上
記仮接合工程までを繰り返す検査リペア工程を備えるこ
とを特徴とする請求項1記載の電子部品の接合方法。
2. After performing the temporary joining step and before the main joining step, electrical continuity between the wiring pattern and the connection portion or an operation of the electronic component is inspected, and a result of the inspection is obtained. The electronic component according to claim 1, further comprising an inspection repair step of peeling the electronic component from the wiring board when a defect is detected and repeating the temporary bonding step again until it is detected as a non-defective product. How to join.
【請求項3】 前記絶縁性樹脂は熱硬化性樹脂でなり、
加熱により硬化することを特徴とする請求項1記載の電
子部品の接合方法。
3. The insulating resin is a thermosetting resin,
The method of joining electronic components according to claim 1, wherein the method is a method of curing by heating.
【請求項4】 前記接着剤層は熱可塑性樹脂からなるこ
と特徴とする請求項1記載の電子部品の接合方法。
4. The method of joining electronic components according to claim 1, wherein the adhesive layer is made of a thermoplastic resin.
【請求項5】 前記電子部品は半導体チップであること
を特徴とする請求項1記載の電子部品の接合方法。
5. The method for joining electronic components according to claim 1, wherein the electronic components are semiconductor chips.
【請求項6】 前記配線基板は液晶表示装置のガラス基
板であり、前記配線パターンは透明配線でなることを特
徴とする請求項1記載の電子部品の接合方法。
6. The method of joining electronic components according to claim 1, wherein the wiring substrate is a glass substrate of a liquid crystal display device, and the wiring pattern is a transparent wiring.
【請求項7】 前記絶縁性樹脂はUV硬化性樹脂でな
り、前記ガラス基板の裏面側からUV露光されることに
より硬化することを特徴とする請求項6記載の電子部品
の接合方法。
7. The method for joining electronic components according to claim 6, wherein the insulating resin is a UV curable resin and is cured by being exposed to UV from the back surface side of the glass substrate.
JP25728394A 1994-09-28 1994-09-28 Method of mounting electronic part Pending JPH0897256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25728394A JPH0897256A (en) 1994-09-28 1994-09-28 Method of mounting electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25728394A JPH0897256A (en) 1994-09-28 1994-09-28 Method of mounting electronic part

Publications (1)

Publication Number Publication Date
JPH0897256A true JPH0897256A (en) 1996-04-12

Family

ID=17304231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25728394A Pending JPH0897256A (en) 1994-09-28 1994-09-28 Method of mounting electronic part

Country Status (1)

Country Link
JP (1) JPH0897256A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100376044B1 (en) * 1999-05-13 2003-03-15 한오근 Solder of semiconductor package and semiconductor package utilizing thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100376044B1 (en) * 1999-05-13 2003-03-15 한오근 Solder of semiconductor package and semiconductor package utilizing thereof

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