JP2961825B2 - Liquid crystal device manufacturing method - Google Patents
Liquid crystal device manufacturing methodInfo
- Publication number
- JP2961825B2 JP2961825B2 JP18480990A JP18480990A JP2961825B2 JP 2961825 B2 JP2961825 B2 JP 2961825B2 JP 18480990 A JP18480990 A JP 18480990A JP 18480990 A JP18480990 A JP 18480990A JP 2961825 B2 JP2961825 B2 JP 2961825B2
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- semiconductor chip
- substrate
- fine particles
- conductive fine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本明は、電気素子の接続方法に関する。具体的には、
半導体チップが基板上に搭載された液晶表示装置の製造
方法に関するものである。The present invention relates to a method for connecting an electric element. In particular,
The present invention relates to a method for manufacturing a liquid crystal display device having a semiconductor chip mounted on a substrate.
従来の電気素子の接合方法は、第２図（ａ）〜（ｃ）
のようなものであった。第２図において、21は基板、22
は基板上の配線パターン、23は電気素子、24は電気素子
の電極を示す。まず第２図（ａ）は、基板上の配線パタ
ーンにプローバ25をおしあてて基板の検査をしている工
程を示す。次に第２図（ｂ）は、第２図（ａ）において
合格になった基板について導電性微粒子27を拡散、混在
させた接着剤シート26を載置した工程を示す。FIGS. 2 (a) to 2 (c) show a conventional method for joining electric elements.
It was something like In FIG. 2, 21 is a substrate, 22
Indicates a wiring pattern on the substrate, 23 indicates an electric element, and 24 indicates an electrode of the electric element. First, FIG. 2A shows a process of applying a prober 25 to a wiring pattern on a substrate to inspect the substrate. Next, FIG. 2 (b) shows a process in which an adhesive sheet 26 in which conductive fine particles 27 are diffused and mixed is placed on a substrate which has passed in FIG. 2 (a).
この導電粒子を拡散、混在させた接着剤シートは厚さ
20〜30μｍ、導電微粒子の径は５〜12μｍである。The adhesive sheet in which the conductive particles are diffused and mixed is thick
20 to 30 μm, and the diameter of the conductive fine particles is 5 to 12 μm.
また、第２図（ｃ）は、電気素子の上面より加熱しな
がら加圧し、接着剤を硬化させ、電気素子を基板の上に
接合させた様子を示す。FIG. 2 (c) shows a state in which pressure is applied while heating from the upper surface of the electric element, the adhesive is cured, and the electric element is bonded on the substrate.
しかし、従来の電気素子の接合方法は第２図より明ら
かなように幾多の問題点を有するものであった。However, the conventional method for joining electric elements has a number of problems as apparent from FIG.
まず電気素子23を基板21の上に接合する時電気素子の
電極24と対応する基板上の配線パターン22とは平面的な
位置合わせを行なう必要がある。First, when the electric element 23 is bonded onto the substrate 21, it is necessary to perform planar alignment between the electrode 24 of the electric element and the corresponding wiring pattern 22 on the substrate.
しかし、この基板が機能的な基板であり、検査を行な
って良品の基板のみを選別する必要がある場合、第２図
（ｃ）のような電気素子を基板上に接合する工程の前
に、第２図（ａ）のようなプローバ25を使った検査工程
が必要となる。However, when this substrate is a functional substrate and it is necessary to perform inspection and select only non-defective substrates, before the step of bonding the electric elements on the substrate as shown in FIG. An inspection process using a prober 25 as shown in FIG. 2A is required.
この検査工程も当然の事ながら、プローバ25の先端位
置と基板の配線パターンの位置とを平面的に位置合わせ
する必要がある。この結果、煩雑で作業工数の大きな位
置合わせ工程が上記の電気素子の電極と基板の配線パタ
ーンとの位置合わせと合わせて２回必要ということにな
り、全体として作業工数の大きな、従って製造コストが
大きなものとなってしまうものであった。As a matter of course, it is necessary to align the position of the tip of the prober 25 with the position of the wiring pattern on the board in a planar manner. As a result, a complicated positioning step requiring a large number of man-hours is required twice in addition to the positioning between the electrodes of the electric elements and the wiring patterns on the substrate. It was a big one.
さらに電気素子23も別個に使用に検査しておく必要が
あり、検査もれがあった場合、そのまま第２図（ｃ）の
ように接着剤を硬化させて接合した場合、接合後の良品
率が下がるものであった。Further, it is necessary to separately inspect the electric element 23 for use. If there is any omission in the inspection, if the adhesive is cured and bonded as shown in FIG. Was going down.
さらに、本説明の様に、導電性微粒子を拡散、混在さ
せた接着剤を用いて、電気素子を基板上へ接合して、そ
の後、不良が発見された場合、上記接着剤が硬化してい
るにもかかわらず、電気素子を基板から剥離して再生し
なければならない。しかし、上記接着剤が硬化している
為、剥離再生は極めて難しく、剥離再生作業の工数が大
きいばかりでなく、剥離再生が失敗する確率も高いもの
である。Furthermore, as described in the present description, the electric element is bonded onto the substrate using an adhesive in which conductive fine particles are diffused and mixed, and then, when a defect is found, the adhesive is cured. Nevertheless, the electric element must be peeled off from the substrate and regenerated. However, since the adhesive is hardened, peeling and regenerating is extremely difficult. Not only is the man-hour for peeling and regenerating work large, but also the probability of peeling and regenerating failure is high.
そこで、本発明は従来のこの様な欠点を解決し電気素
子と基板の位置合わせを容易にし、不良時の剥離再生を
不用とする事を目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional drawbacks described above, to facilitate the alignment between the electric element and the substrate, and to eliminate the need for peeling and regenerating when there is a defect.
本発明の液晶装置の製造方法は、液晶パネルの基板上
に、導電性微粒子が混在された接着剤層を介して半導体
チップを接続する液晶装置の製造方法であって、 前記基板に形成された液晶駆動用電極と前記半導体チ
ップとの間に、前記接着剤層を介在させた状態で、前記
基板と前記半導体チップとを常温で加圧することにより
前記液晶駆動用電極と前記半導体チップに設けられた電
極とを電気的に接続し、前記半導体チップを通して、前
記液晶駆動用電極に電気信号を印加することによって、
前記液晶パネルの検査を行う工程と、 前記検査の結果合格となった場合、前記基板と前記半
導体チップとを加熱しながら加圧して前記接着剤層を硬
化させる工程とを備えてなることを特徴とする。The method for manufacturing a liquid crystal device according to the present invention is a method for manufacturing a liquid crystal device in which a semiconductor chip is connected to a substrate of a liquid crystal panel via an adhesive layer in which conductive fine particles are mixed, the method being formed on the substrate. The liquid crystal driving electrode and the semiconductor chip are provided on the liquid crystal driving electrode and the semiconductor chip by pressing the substrate and the semiconductor chip at room temperature with the adhesive layer interposed between the liquid crystal driving electrode and the semiconductor chip. By electrically connecting the electrodes, and applying an electrical signal to the liquid crystal drive electrode through the semiconductor chip,
A step of inspecting the liquid crystal panel, and a step of heating and pressing the substrate and the semiconductor chip to cure the adhesive layer when the result of the inspection is successful. And
以下に本発明の実施例を図面を用いて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）は、複数個の突起電極を有する電気素子
たる半導体チップと、これに対応する複数の配線パター
ンが形成された液晶パネルのガラス基板の一部の接合前
の断面図を示す。この配線パターンの一部は液晶パネル
の液晶駆動用電極と電気的に結びついているものであ
る。FIG. 1A is a cross-sectional view of a part of a glass substrate of a liquid crystal panel on which a semiconductor chip as an electric element having a plurality of projecting electrodes and a plurality of wiring patterns corresponding thereto are formed before bonding. . A part of this wiring pattern is electrically connected to the liquid crystal driving electrode of the liquid crystal panel.
第１図（ｂ）は、上記電気素子たる半導体チップと、
基板たるガラス基板の間に導電性微粒子を拡散、混在さ
せた接着剤フィルムを挟持したものであり、導電性微粒
子の径は接着剤フィルム厚とほぼ同等にしてある。FIG. 1B shows a semiconductor chip as the electric element,
An adhesive film in which conductive fine particles are diffused and mixed is sandwiched between glass substrates as substrates, and the diameter of the conductive fine particles is substantially equal to the thickness of the adhesive film.
第１図（ｃ）は、半導体チップの上から常温で加圧
し、この加圧のもとにおいて、半導体チップの電極とガ
ラス基板の配線パターンとの電気的接続をはかり、上記
半導体チップを通してガラス基板に電気信号を印加し、
検査をしている工程を示す。FIG. 1 (c) shows that the semiconductor chip is pressurized at room temperature from above, and under this pressurization, the electrical connection between the electrodes of the semiconductor chip and the wiring pattern of the glass substrate is made. Apply an electrical signal to
This shows the inspection process.
さらに第１図（ｄ）は、第１図（ｃ）の工程において
検査合格となったものについて、半導体チップの上から
加熱しながら加圧し、接着剤層を硬化させて、半導体チ
ップとガラス基板を強固に接合、固定したものである。
この時、半導体チップの突起電極とガラス基板の配線パ
ターンは導電性微粒子を介して電気的導通状態にある。Further, FIG. 1 (d) shows that the semiconductor chip and the glass substrate which were passed the inspection in the step of FIG. Are firmly joined and fixed.
At this time, the protruding electrodes of the semiconductor chip and the wiring pattern of the glass substrate are in an electrically conductive state via the conductive fine particles.
第１図において、１は基板たるガラス基板、２はガラ
ス基板上の配線パターン、３は電気素子たる半導体チッ
プ、４は半導体チップの電極、５は接着剤シート、６は
導電性微粒子、７は液晶パネル、８はシール部、９は液
晶層、10は液晶駆動用電極を示す。In FIG. 1, 1 is a glass substrate as a substrate, 2 is a wiring pattern on the glass substrate, 3 is a semiconductor chip as an electric element, 4 is an electrode of a semiconductor chip, 5 is an adhesive sheet, 6 is conductive fine particles, and 7 is a conductive fine particle. A liquid crystal panel, 8 is a seal portion, 9 is a liquid crystal layer, and 10 is a liquid crystal drive electrode.
第１図（ｂ）のように、半導体チップと基板の間に導
電性微粒子を拡散、混在させた接着剤フィルムを挟持し
た状態においては、必ずしも半導体チップの電極とガラ
ス基板の配線パターンは電気的導通状態ではない。なぜ
ならば、導電性微粒子径が必ずしも接着剤フィルムの厚
さよりも大きいとは限らないからである。As shown in FIG. 1B, when an adhesive film in which conductive fine particles are diffused and mixed is sandwiched between a semiconductor chip and a substrate, the electrodes of the semiconductor chip and the wiring pattern of the glass substrate are not necessarily electrically connected. Not conductive. This is because the diameter of the conductive fine particles is not always larger than the thickness of the adhesive film.
第１図（ｃ）のように、半導体チップの上から常温で
加圧すると、半導体チップの電極の部分で柔らかい接着
剤フィルムは押しつぶされ、全般的に導電性微粒子が、
半導体チップの電極とガラス基板の配線パターンの両方
と電気的に接続するようになる。この時、半導体チップ
３を通して液晶パネル７の液晶駆動用電極10に電気信号
を印加すれば、実際に使用する半導体チップと液晶パネ
ルの両方を一括して検査する事ができる。従ってこの検
査の後、合格の品物のみを第１図（ｄ）の様に加熱加圧
して接着剤層を硬化させれば、接合後の良品率もおのず
と向上するものである。従って剥離再生の必要性も極端
に低減され、作業の効卒も極めて向上するものである。As shown in FIG. 1 (c), when pressure is applied from above the semiconductor chip at room temperature, the soft adhesive film is crushed at the electrode portions of the semiconductor chip, and the conductive fine particles are generally removed.
It becomes electrically connected to both the electrode of the semiconductor chip and the wiring pattern of the glass substrate. At this time, if an electric signal is applied to the liquid crystal driving electrode 10 of the liquid crystal panel 7 through the semiconductor chip 3, both the semiconductor chip and the liquid crystal panel actually used can be inspected collectively. Therefore, after this inspection, if only the acceptable products are heated and pressed to cure the adhesive layer as shown in FIG. 1 (d), the non-defective product ratio after joining is naturally improved. Therefore, the necessity of peeling and regenerating is extremely reduced, and the efficiency of the operation is greatly improved.
第１図（ｄ）においては、第１図（ｃ）において半導
体チップとガラス基板を位置合わせしたものをそのまま
加熱加圧する為、煩雑で作業工数の大きな位置合わせ工
程が、全工程で一回ですむ為製造コストが少なくてすむ
ものである。In FIG. 1 (d), since the alignment of the semiconductor chip and the glass substrate in FIG. 1 (c) is heated and pressurized as it is, a complicated and large man-hour alignment process is performed once in all processes. Therefore, the manufacturing cost is low.
本発明は以上説明したように、電気素子を常温におい
て導電性微粒子を拡散、混在させた接着剤層を介して基
板に加圧することによって電気素子と基板を初期的な電
気的接続状態にして検査をすることを可能にして、位置
合わせ工数を低減し、剥離再生必要な確率を低減させる
効果がある。As described above, the present invention provides an initial electrical connection between an electric element and a substrate by inspecting the electric element at room temperature by pressing the substrate through an adhesive layer in which conductive fine particles are diffused and mixed. This has the effect of reducing the number of alignment steps and the probability of the need for peeling and regeneration.
第１図（ａ）〜（ｄ）は本発明における電気素子の接合
方法の工程説明図。 第２図（ａ）〜（ｃ）は従来の電気素子の接合方法の工
程説明図。 １……ガラス基板 ２……配線パターン ３……半導体チップ ４……電極 ５……接着剤シート ６……導電性微粒子 ７……液晶パネル ８……シール部 ９……液晶層 10……液晶駆動用電極 21……基板 22……配線パターン 23……電気素子 24……電極 25……検査用プローバ 26……接着剤シート 27……導電性粒子1 (a) to 1 (d) are process explanatory views of a method for bonding electric elements according to the present invention. 2 (a) to 2 (c) are process explanatory views of a conventional method for bonding electric elements. DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Wiring pattern 3 ... Semiconductor chip 4 ... Electrode 5 ... Adhesive sheet 6 ... Conductive fine particles 7 ... Liquid crystal panel 8 ... Seal part 9 ... Liquid crystal layer 10 ... Liquid crystal Driving electrode 21 Substrate 22 Wiring pattern 23 Electrical element 24 Electrode 25 Prober for inspection 26 Adhesive sheet 27 Conductive particles
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 21/60 321 H01L 21/66 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. 6 , DB name) H01L 21/60 311 H01L 21/60 321 H01L 21/66
Claims (1)
在された接着剤層を介して半導体チップを接続する液晶
装置の製造方法であって、 前記基板に形成された液晶駆動用電極と前記半導体チッ
プとの間に、前記接着剤層を介在させた状態で、前記基
板と前記半導体チップとを常温で加圧することにより前
記液晶駆動用電極と前記半導体チップに設けられた電極
とを電気的に接続し、前記半導体チップを通して、前記
液晶駆動用電極に電気信号を印加することによって、前
記液晶パネルの検査を行う工程と、 前記検査の結果合格となった場合、前記基板と前記半導
体チップとを加熱しながら加圧して前記接着剤層を硬化
させる工程とを備えてなることを特徴とする液晶装置の
製造方法。1. A method for manufacturing a liquid crystal device in which a semiconductor chip is connected to a substrate of a liquid crystal panel via an adhesive layer in which conductive fine particles are mixed, comprising: a liquid crystal driving electrode formed on the substrate; By pressing the substrate and the semiconductor chip at room temperature with the adhesive layer interposed between the semiconductor chip and the substrate, the liquid crystal driving electrodes and the electrodes provided on the semiconductor chip are electrically connected. Testing the liquid crystal panel by applying an electrical signal to the liquid crystal drive electrode through the semiconductor chip through the semiconductor chip; and, if the test results in a pass, the substrate and the semiconductor chip. And heating and pressurizing to cure the adhesive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18480990A JP2961825B2 (en) | 1990-07-12 | 1990-07-12 | Liquid crystal device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18480990A JP2961825B2 (en) | 1990-07-12 | 1990-07-12 | Liquid crystal device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0471246A JPH0471246A (en) | 1992-03-05 |
| JP2961825B2 true JP2961825B2 (en) | 1999-10-12 |
Family
ID=16159672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18480990A Expired - Fee Related JP2961825B2 (en) | 1990-07-12 | 1990-07-12 | Liquid crystal device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2961825B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997027492A1 (en) * | 1996-01-22 | 1997-07-31 | Hitachi, Ltd. | Method for mounting bare chip and bare chip carrier |
| JP3343642B2 (en) * | 1996-04-26 | 2002-11-11 | シャープ株式会社 | Tape carrier package and liquid crystal display |
| US6103553A (en) | 1996-12-11 | 2000-08-15 | Hyundai Electronics Industries Co., Ltd. | Method of manufacturing a known good die utilizing a substrate |
-
1990
- 1990-07-12 JP JP18480990A patent/JP2961825B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0471246A (en) | 1992-03-05 |
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