JPH0121620B2 - - Google Patents

Info

Publication number
JPH0121620B2
JPH0121620B2 JP58028245A JP2824583A JPH0121620B2 JP H0121620 B2 JPH0121620 B2 JP H0121620B2 JP 58028245 A JP58028245 A JP 58028245A JP 2824583 A JP2824583 A JP 2824583A JP H0121620 B2 JPH0121620 B2 JP H0121620B2
Authority
JP
Japan
Prior art keywords
flip
chip integrated
integrated circuit
test
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58028245A
Other languages
Japanese (ja)
Other versions
JPS59154035A (en
Inventor
Tetsuo Fujii
Toshio Sonobe
Michitaka Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP58028245A priority Critical patent/JPS59154035A/en
Publication of JPS59154035A publication Critical patent/JPS59154035A/en
Publication of JPH0121620B2 publication Critical patent/JPH0121620B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 本発明はフリツプチツプ集積回路のテスト方法
に関するものである。フリツプチツプ集積回路は
チツプの一面に多数の電極部となるバンプが形成
された集積回路の一種である。このフリツプチツ
プ集積回路は、通常入出力端子を持つセラミツク
ス基板表面にハンダで一体的に接合されて導通性
を確保して使用されている。しかし、フリツプチ
ツプ集積回路のバーンインが非常に困難であるた
めに、欠陥のあるフリツプチツプ集積回路をセラ
ミツクス基板上に固定してしまう場合が多々あ
り、半導体装置が完成した後に欠陥のあるフリツ
プチツプ集積回路がみつけられる場合が多い。か
かる場合には、欠陥のあるフリツプチツプ集積回
路を取り換るのが非常に繁雑であり、生産性向上
を阻害する要因ともなつている。又、時には、正
常なフリツプチツプ集積回路を含めて半導体装置
全体を放棄しなければならないといつた問題が生
じている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing flip-chip integrated circuits. A flip chip integrated circuit is a type of integrated circuit in which a large number of bumps serving as electrode portions are formed on one side of a chip. This flip-chip integrated circuit is normally used by being integrally bonded with solder to the surface of a ceramic substrate having input/output terminals to ensure conductivity. However, because burn-in of flip-chip integrated circuits is extremely difficult, defective flip-chip integrated circuits are often fixed onto ceramic substrates, and defective flip-chip integrated circuits are discovered after the semiconductor device is completed. This is often the case. In such a case, it is very complicated to replace the defective flip-chip integrated circuit, and this is a factor that hinders productivity improvement. Also, sometimes problems arise in which the entire semiconductor device, including the normal flip-chip integrated circuit, has to be abandoned.

本発明は、半導体装置にフリツプチツプ集積回
路を組み込まない前に、フリツプチツプ集積回路
のバーンインを行い、欠陥のあるフリツプチツプ
集積回路を排除することを目的とするものであ
る。
An object of the present invention is to perform burn-in of a flip-chip integrated circuit and eliminate defective flip-chip integrated circuits before incorporating the flip-chip integrated circuit into a semiconductor device.

本発明のフリツプチツプ集積回路のテスト方法
は、1個のフリツプチツプ集積回路の通電を必要
とする複数個のバンプと接続するための複数個の
電極部と、電源に接続するための複数個の端子
と、該電極部および該端子を結ぶ複数個の導電部
とで構成される少なくとも1組のテスト回路をも
つテスト基板の上記複数個の電極部とフリツプチ
ツプ集積回路の複数個のバンプとを導電性有機結
合剤で電気的に結線する工程、上記テスト基板の
上記複数個の端子と電源とを結線し、フリツプチ
ツプ集積回路に通電してバーンインテストを行う
工程、上記フリツプチツプ集積回路を加熱または
溶剤を接触させる等で導電性有機結合剤を除去し
て上記フリツプチツプ集積回路を上記テスト基板
より分離する工程を順次実施することを特徴とす
るものである。
The flip-chip integrated circuit testing method of the present invention includes a plurality of electrode portions for connecting to a plurality of bumps that require energization of one flip-chip integrated circuit, and a plurality of terminals for connection to a power source. , the plurality of electrode portions of a test board having at least one set of test circuits comprising the electrode portion and a plurality of conductive portions connecting the terminals and the plurality of bumps of the flip-chip integrated circuit are connected to each other using a conductive organic material. a step of electrically connecting the plurality of terminals of the test board with a power source and conducting a burn-in test by energizing the flip-chip integrated circuit; and heating or contacting the flip-chip integrated circuit with a solvent. The present invention is characterized in that the steps of removing the conductive organic binder and separating the flip-chip integrated circuit from the test substrate are sequentially performed.

本発明のテスト方法では半導体装置のセラミツ
クス基板に代えて、バーンイン用のテスト基板を
使用する。そしてこのテスト基板上にテストすべ
きフリツプチツプ集積回路を結線し、バーンイン
の後にフリツプチツプ集積回路をテスト基板より
分離してバーンインテストを行うものである。
In the test method of the present invention, a burn-in test substrate is used in place of the ceramic substrate of the semiconductor device. Then, a flip-chip integrated circuit to be tested is wired onto this test board, and after burn-in, the flip-chip integrated circuit is separated from the test board and a burn-in test is performed.

このテスト基板は、1個のフリツプチツプ集積
回路のバーンイン時に通電を必要とする複数個の
バンプと接続するための複数個の電極部と外部電
源に接続するための複数個の端子と該電極部およ
び該端子をむすぶ複数個の導電部とで構成される
すくなくとも1組のテスト回路を持つている。
This test board includes a plurality of electrode sections for connecting to a plurality of bumps that require energization during burn-in of one flip-chip integrated circuit, a plurality of terminals for connecting to an external power supply, and the electrode section and It has at least one set of test circuits comprising a plurality of conductive parts connecting the terminals.

本発明の第1工程は、上記テスト基板の1組の
テスト回路を構成する電極部に少なくとも1個の
フリツプチツプ集積回路の通電を必要とするバン
プを導電性有機結合剤で結合させる工程である。
多数組のテスト回路を持つ場合には、1度に多数
のフリツプチツプ集積回路のバーンインが実施で
きる。
The first step of the present invention is to bond, with a conductive organic binder, bumps that require energization of at least one flip-chip integrated circuit to the electrode portions constituting a set of test circuits on the test board.
When having multiple sets of test circuits, burn-in of multiple flip-chip integrated circuits can be performed at one time.

第2工程はテスト基板の上記複数個の端子と外
部電源とを結線し、フリツプチツプ集積回路に通
電してバーンインを行う工程である。フリツプチ
ツプ集積回路の通電テストを行う以外に、フリツ
プチツプ集積回路が使用される環境と似た環境状
態で、フリツプチツプ集積回路の通電を行うこと
もできる。
The second step is a step of connecting the plurality of terminals of the test board to an external power source and applying power to the flip-chip integrated circuit to perform burn-in. In addition to energizing a flip-chip integrated circuit, the flip-chip integrated circuit can also be energized under environmental conditions similar to the environment in which the flip-chip integrated circuit is used.

第3工程は、バーンイン後、導電性有機結合剤
の部分を加熱あるいは溶剤を接触させ、導電性有
機結合剤を溶融あるいは溶解させてテスト基板よ
りバーンインしたフリツプチツプ集積回路を取り
出す工程である。
The third step is, after burn-in, heating or contacting the conductive organic binder with a solvent to melt or dissolve the conductive organic binder and take out the burned-in flip-chip integrated circuit from the test substrate.

この方法を具体的に説明すると、例えば、テス
ト基板としては、第1図及び第2図に示すテスト
基板1を使用することができる。このテスト基板
1はサフアイヤ、石英等の透明セラミツクスで作
られ、その基板1上に3組のテスト回路2が形成
されている。各回路2は、フリツプチツプ集積回
路のバンプと接続するための5個の電極部31,
32,33,34,35と5個の端子41,4
2,43,44,45および5個の電極部31〜
35および端子41〜45を夫々連結する導電部
51,52,53,54,55で形成されてい
る。尚、導電部51〜55の上面には、例えば膜
厚印刷等によるガラス層の絶縁膜6を形成する。
このテスト基板1を用い、第3図にその断面を示
す様に電極部31〜35に未硬化の導電性ゴム7
を塗布する。導電性ゴム7が硬化しない前にフリ
ツプチツプ集積回路8のハンダバンプ81をこの
未硬化の導電性ゴム7に押し付ける。この状態の
断面を第4図に示す。この状態で導電性ゴム7を
硬化し、テスト基板1の電極部31〜35とフリ
ツプチツプ集積回路8のハンダバンプ81とを接
合する。次に、第5図にその断面を示すようにコ
ネクタ9をテスト基板1の端子41〜45に被嵌
し、端子41〜45と外部電源(図示せず)とを
接続する。次にコネクタより必要な電流、信号を
流し、テスト基板1上の各フリツプチツプ集積回
路8をバーンインする。バーンイン後は、テスト
基板1をコネクタ9より引き離し、かつこの導電
性ゴム7を溶解あるいは膨潤して接合力を弱める
適当な溶剤中に浸漬し、あるいは溶剤をふりか
け、テスト基板1の導電部31〜35よりフリツ
プチツプ集積回路8を分離する。これにより、フ
リツプチツプ集積回路8のバーンインが達成され
る。
To explain this method in detail, for example, the test board 1 shown in FIGS. 1 and 2 can be used as the test board. This test board 1 is made of transparent ceramics such as sapphire or quartz, and three sets of test circuits 2 are formed on the board 1. Each circuit 2 includes five electrode portions 31 for connection to bumps of a flip-chip integrated circuit;
32, 33, 34, 35 and five terminals 41, 4
2, 43, 44, 45 and five electrode parts 31~
35 and terminals 41 to 45, respectively. Incidentally, on the upper surfaces of the conductive parts 51 to 55, an insulating film 6 of a glass layer is formed by, for example, film thickness printing.
Using this test board 1, as shown in the cross section of FIG.
Apply. Before the conductive rubber 7 is cured, the solder bumps 81 of the flip-chip integrated circuit 8 are pressed onto the uncured conductive rubber 7. A cross section in this state is shown in FIG. In this state, the conductive rubber 7 is cured, and the electrode parts 31 to 35 of the test board 1 and the solder bumps 81 of the flip-chip integrated circuit 8 are bonded. Next, the connector 9 is fitted onto the terminals 41 to 45 of the test board 1 as shown in the cross section in FIG. 5, and the terminals 41 to 45 are connected to an external power source (not shown). Next, necessary current and signals are passed through the connector to burn-in each flip-chip integrated circuit 8 on the test board 1. After burn-in, the test board 1 is separated from the connector 9, and the conductive rubber 7 is immersed in or sprinkled with a suitable solvent that dissolves or swells the bonding force and weakens the bonding force. The flip chip integrated circuit 8 is separated from 35. Burn-in of the flip-chip integrated circuit 8 is thereby achieved.

バーンインによつて欠陥のあるフリツプチツプ
集積回路は取り除き、合格したフリツプチツプ集
積回路のみを次の半導体装置用のフリツプチツプ
集積回路として使用する。尚、テスト用基板とし
て、透明な基板を用いて説明したが、この透明基
板を用いた場合には、例えば、基板の裏面よりパ
ターン認識能をもつテレビカメラ等でテスト基板
1上の電導部31〜35と、フリツプチツプ集積
回路8のバンプ8とを一致させ、自動的に電極部
にフリツプチツプ集積回路のバンプを固定するこ
とができる利点がある。
Faulty flip-chip integrated circuits are removed by burn-in, and only flip-chip integrated circuits that pass the test are used as flip-chip integrated circuits for the next semiconductor device. Although the explanation has been made using a transparent substrate as the test substrate, if this transparent substrate is used, for example, the conductive portions 31 on the test substrate 1 can be viewed from the back side of the substrate with a television camera or the like having pattern recognition ability. .about.35 and the bumps 8 of the flip-chip integrated circuit 8, and there is an advantage that the bumps of the flip-chip integrated circuit can be automatically fixed to the electrode portions.

このテレビカメラを使用しない場合には、テス
ト基板は透明でなくともよい。又、テスト基板上
には、簡略化のために3個のテスト回路のみを表
示したが、通常は数個ないし数百個のテスト回路
を組み付け、1度に多数のフリツプチツプ集積回
路をバーンインを行う。又、基板上に形成した端
子もテスト基板の全周に端子を設けることもでき
る。
If this television camera is not used, the test board does not need to be transparent. Also, although only three test circuits are shown on the test board for the sake of simplicity, normally several to several hundred test circuits are assembled, and a large number of flip-chip integrated circuits are burn-in at one time. . Furthermore, the terminals formed on the board can also be provided all around the test board.

導電性有機結合剤としては、導電性ゴムが最も
すぐれている様に思われる。この導電性ゴムは柔
軟性があるために、バーンイン中にテスト基板と
フリツプチツプ集積回路との間で熱膨張係数等の
歪が生じる様な場合においても導電性ゴムがその
歪を吸収し、フリツプチツプ集積回路に異常な歪
を与えない様な利点がある。より好ましくは、熱
可塑性の軟質樹脂状の導電性高分子が好ましい。
この場合には、結合剤の固化、軟化はテスト基板
を軟化点以上に加熱する。あるいは軟化点以下に
冷却することによりテスト基板へのフリツプチツ
プ集積回路固着および分離が可能となる。尚、こ
の場合において、軟化温度は、バーンイン時のテ
スト温度より高いことが必要である。
As a conductive organic binder, conductive rubber seems to be the best. Because this conductive rubber is flexible, even if distortions such as thermal expansion coefficients occur between the test board and the flip-chip integrated circuit during burn-in, the conductive rubber absorbs the distortion and improves the flip-chip integrated circuit. It has the advantage of not causing abnormal distortion to the circuit. More preferably, a thermoplastic soft resin-like conductive polymer is used.
In this case, the hardening and softening of the binder heats the test substrate above its softening point. Alternatively, by cooling the flip-chip integrated circuit to below its softening point, it becomes possible to fix the flip-chip integrated circuit to the test board and separate it. In this case, the softening temperature needs to be higher than the test temperature during burn-in.

導電性有機結合剤は加熱を併用しつつ適当な溶
媒等で有機結合剤を溶解あるいは膨潤させて接着
力を失わさせ、フリツプチツプ集積回路をテスト
基板より分離することができる。
The flip-chip integrated circuit can be separated from the test substrate by dissolving or swelling the conductive organic binder with a suitable solvent or the like in conjunction with heating to lose its adhesive strength.

テスト基板は、繰り返し使用することが可能で
ある。この場合に、熱可塑性の導電性有機結合剤
の場合には、繰り返し使用が可能の場合もある。
しかし、熱硬化性の導電性有機結合剤を用いる場
合には、バーンイン毎に導電部に未硬化の導電性
有機結合剤を塗布する必要がある。特殊な場合に
は、導電性有機結合剤の塗布をフリツプチツプ集
積回路のバンプの先端に行い、この結合剤を塗布
されたバンプをもつフリツプチツプ集積回路をテ
スト基板に押し付けて接着してもよい。
The test board can be used repeatedly. In this case, in the case of a thermoplastic conductive organic binder, repeated use may be possible.
However, when a thermosetting conductive organic binder is used, it is necessary to apply an uncured conductive organic binder to the conductive portion every burn-in. In special cases, a conductive organic binder may be applied to the tips of the bumps of the flip-chip integrated circuit, and the flip-chip integrated circuit with the bumps coated with the binder may be pressed and bonded to a test substrate.

上記した本発明のフリツプチツプ集積回路のテ
スト方法は導電性有機結合剤が熱あるいは溶媒に
より容易に結合剤としての作用をなくすことがで
きることに着目し、フリツプチツプ集積回路のハ
ンダバンプとテスト基板の電極部との着脱可能な
接合を達成し、これにより、バーンインを可能と
したものである。本発明のテスト方法により、
個々のフリツプチツプ集積回路をバーンインによ
りチエツクすることが可能であるために、欠陥の
ないフリツプチツプ集積回路のみを半導体装置の
部品として供給することができる。このために、
半導体装置の組み付け後におけるフリツプチツプ
集積回路の欠陥による手なおし、半導体装置の廃
棄等の無駄がなくなる。
The above-described method for testing flip-chip integrated circuits of the present invention focuses on the fact that the conductive organic binder can easily eliminate its action as a binder by heat or a solvent, and uses the method of testing the flip-chip integrated circuit between the solder bumps of the flip-chip integrated circuit and the electrode portion of the test substrate. A removable bond was achieved, thereby making burn-in possible. By the test method of the present invention,
Since it is possible to check individual flip-chip integrated circuits by burn-in, only defect-free flip-chip integrated circuits can be supplied as components of semiconductor devices. For this,
This eliminates waste such as repair work due to defects in the flip-chip integrated circuit after assembly of the semiconductor device and disposal of the semiconductor device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のテスト方法の具体例として説
明したテスト基板の平面図、第2図は第1図のA
−A矢視断面図、第3図は本発明のテスト方法の
第1工程を説明する部分断面図、第4図はテスト
基板にフリツプチツプ集積回路を固定した状態の
部分断面図、第5図はテスト基板をコネクターに
組付けた状態の一部断面図である。 1…テスト基板、2…テスト回路、31〜35
…電極部、41〜45…端子、51〜55…導電
部、6…絶縁膜、7…導電性ゴム、8…フリツプ
チツプ集積回路、81…ハンダバンプ、9…コネ
クタ。
FIG. 1 is a plan view of a test board explained as a specific example of the test method of the present invention, and FIG. 2 is an A of FIG.
3 is a partial sectional view illustrating the first step of the test method of the present invention, FIG. 4 is a partial sectional view of a flip-chip integrated circuit fixed to a test board, and FIG. FIG. 3 is a partial cross-sectional view of the test board assembled to the connector. 1...Test board, 2...Test circuit, 31-35
... Electrode part, 41-45... Terminal, 51-55... Conductive part, 6... Insulating film, 7... Conductive rubber, 8... Flip chip integrated circuit, 81... Solder bump, 9... Connector.

Claims (1)

【特許請求の範囲】 1 1個のフリツプチツプ集積回路の通電を必要
とする複数個のバンプと接続するための複数個の
電極部と、電源に接続するための複数個の端子
と、該電極部および該端子を結ぶ複数個の導電部
とで構成される少なくとも1組のテスト回路をも
つテスト基板の上記複数個の電極部とフリツプチ
ツプ集積回路の複数個のバンプとを導電性有機結
合剤で電気的に結線する工程、 上記テスト基板の上記複数個の端子と電源とを
結線し、フリツプチツプ集積回路に通電してバー
ンインテストを行う工程、 上記フリツプチツプ集積回路を加熱または溶剤
を接触させる等で上記導電性有機結合剤を除去し
て上記フリツプチツプ集積回路を上記テスト基板
より分離する工程を順次実施することを特徴とす
るフリツプチツプ集積回路のテスト方法。 2 導電性有機結合剤は熱可塑性の導電性ゴムで
ある特許請求の範囲第1項記載のテスト方法。
[Claims] 1. A plurality of electrode sections for connecting to a plurality of bumps that require energization of one flip chip integrated circuit, a plurality of terminals for connection to a power source, and the electrode section. and a plurality of conductive parts connecting the terminals, the plurality of electrode parts of the test board having at least one set of test circuits and the plurality of bumps of the flip-chip integrated circuit are electrically connected using a conductive organic binder. a step of connecting the plurality of terminals of the test board to a power source and conducting a burn-in test by energizing the flip-chip integrated circuit; heating the flip-chip integrated circuit or contacting it with a solvent to 1. A method for testing a flip-chip integrated circuit, comprising sequentially performing the steps of removing the organic binder and separating the flip-chip integrated circuit from the test substrate. 2. The test method according to claim 1, wherein the conductive organic binder is a thermoplastic conductive rubber.
JP58028245A 1983-02-22 1983-02-22 Testing of flip-chip integrated circuit Granted JPS59154035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58028245A JPS59154035A (en) 1983-02-22 1983-02-22 Testing of flip-chip integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58028245A JPS59154035A (en) 1983-02-22 1983-02-22 Testing of flip-chip integrated circuit

Publications (2)

Publication Number Publication Date
JPS59154035A JPS59154035A (en) 1984-09-03
JPH0121620B2 true JPH0121620B2 (en) 1989-04-21

Family

ID=12243193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58028245A Granted JPS59154035A (en) 1983-02-22 1983-02-22 Testing of flip-chip integrated circuit

Country Status (1)

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DE3817600C2 (en) * 1987-05-26 1994-06-23 Matsushita Electric Works Ltd Method of manufacturing a semiconductor device with a ceramic substrate and an integrated circuit
JPS6481333A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Test board for flip-chip
JPH0563029A (en) * 1991-09-02 1993-03-12 Fujitsu Ltd Semiconductor device
US5206585A (en) * 1991-12-02 1993-04-27 At&T Bell Laboratories Methods for testing integrated circuit devices
US5971253A (en) * 1995-07-31 1999-10-26 Tessera, Inc. Microelectronic component mounting with deformable shell terminals
DE59611449D1 (en) 1995-09-08 2007-12-20 Fraunhofer Ges Forschung METHOD AND DEVICE FOR TESTING A CHIP
US6635514B1 (en) 1996-12-12 2003-10-21 Tessera, Inc. Compliant package with conductive elastomeric posts
DE69915299T2 (en) 1998-07-15 2005-02-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. METHOD FOR TRANSLATING SOLDERING ON AN ARRANGEMENT AND / OR TESTING THE ARRANGEMENT
US7159292B2 (en) 2002-05-27 2007-01-09 Yamaichi Electronics Co., Ltd. Recovery processing method of an electrode
JP2007259833A (en) * 2006-03-30 2007-10-11 Tachikawa Heiwa Nouen:Kk Wooden plant pot

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