JPH03184352A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03184352A JPH03184352A JP32317789A JP32317789A JPH03184352A JP H03184352 A JPH03184352 A JP H03184352A JP 32317789 A JP32317789 A JP 32317789A JP 32317789 A JP32317789 A JP 32317789A JP H03184352 A JPH03184352 A JP H03184352A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- electrodes
- electrode
- insulating substrate
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000853 adhesive Substances 0.000 claims abstract description 25
- 230000001070 adhesive effect Effects 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 238000003825 pressing Methods 0.000 claims abstract 5
- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 10
- 208000028659 discharge Diseases 0.000 claims description 2
- 238000004070 electrodeposition Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 5
- 229920005989 resin Polymers 0.000 abstract description 5
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000035939 shock Effects 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000005416 organic matter Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関するものであり、特
にハイブリッドＩＣ（以後ＨＩＣと略す）に搭載するＬ
ＳＩチップの実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
This relates to a method for mounting an SI chip.
従来の技術
従来の上記ＬＳＩチップの実装方法を第５図の工程断面
図にしたがって順に説明する。2. Description of the Related Art A conventional method for mounting the above-mentioned LSI chip will be explained in order with reference to process cross-sectional views in FIG.
まず、第５図（ａ）に示すように、ガラス、セラミック
スなどよりなる配線基板１のＡｕ 、 Ａｇ 、 Ｃｕ
、 ＩＴＯ（すすを含んだ酸化インジウム）なとより
なる導体配線２を有した面に、熱で硬化する特性を有す
るなどの接着剤１４を塗布する。次に＠５図（ｂ）に示
すように、ＬＳＩチップ４を接着剤１４の塗布面の所定
位置１こ配置し、接着剤を硬化させる。次に第５図（ｃ
）に示すように、ＬＳＩチップ４のＡＩ！電極５と導体
配線２をワイヤボンディングマシンによってＡｕワイヤ
１３で接続する。First, as shown in FIG. 5(a), a wiring board 1 made of glass, ceramics, etc. is made of Au, Ag, Cu.
An adhesive 14 having a property of curing with heat is applied to the surface having the conductor wiring 2 made of ITO (indium oxide containing soot). Next, as shown in Figure 5 (b), the LSI chip 4 is placed at a predetermined position on the surface coated with the adhesive 14, and the adhesive is cured. Next, Figure 5 (c
), the AI of LSI chip 4! The electrode 5 and the conductor wiring 2 are connected with an Au wire 13 using a wire bonding machine.
発明が解決しようとする課題
しかし、従来のＬＳＩチップの実装方法では、Ａｕワイ
ヤ１３で外部配線導体電ａｉ２と接続するために次に示
すような問題点があった。Problems to be Solved by the Invention However, the conventional LSI chip mounting method has the following problems because the Au wire 13 is connected to the external wiring conductor ai2.
（１） Ａｕワイヤ１３の接続不良あるいはＬＳＩチ
ップ４の不良があった場合、ＬＳＩチップ４の交換がで
きず、配線基板１をも廃棄せざるを得ないので非常に材
料ロスが大きい。(1) If there is a poor connection of the Au wire 13 or a defect in the LSI chip 4, the LSI chip 4 cannot be replaced and the wiring board 1 must also be discarded, resulting in a very large loss of material.
（２１Ａｕワイヤ１３の断線、あるいはＡＪｌｌを極５
の酸化を防ぐためにＡｕワイヤ１３の接続後にＬＳＩチ
ップ４の全体を樹脂によってモールドして保護してやら
ねばならないため、ＬＳＩチップ４の所要スペースが大
きくなる。(21Au wire 13 disconnected or AJll connected to pole 5)
In order to prevent oxidation of the LSI chip 4, the entire LSI chip 4 must be protected by being molded with resin after the Au wires 13 are connected, which increases the space required for the LSI chip 4.
＜３１ ＬＳＩチップ４はＬＳＩパッケージ品よりも
相当小さくなるが、接続がＬＳＩチップ４の外周側にあ
る導体配線２とされるために実装直積がＬＳＩチップ４
自身よりも大きくなる。<31 Although the LSI chip 4 is considerably smaller than the LSI package product, since the connection is made with the conductor wiring 2 on the outer periphery of the LSI chip 4, the mounting direct product is smaller than the LSI chip 4.
Become bigger than yourself.
本発明は上記問題を解決するものであり、配線基板を廃
棄せずｉこＬＳＩチップの交換ができ、ＬＳＩチップ８
樹脂によってモールドする必要がなく、ＬＳＩ ＝ｆ−
ツブの実装面積を小さくできる半導体装置の製造方法を
提供することを目的とするものである。The present invention solves the above-mentioned problems, and allows the replacement of IC LSI chips without discarding the wiring board.
There is no need to mold with resin, LSI = f-
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the mounting area of a bump.
課題を解決するための手段
上記問題を解決するため本発明の半導体装置の製造方法
は、配線基板に突起状電極を形成し、突起状電極と半導
体素子の電極の位置合わせを行い、半導体素子を加熱し
ながら加圧接続した後に、半導体素子と配線基板間に絶
縁性接着剤を塗布浸透させ硬化し、半導体素子と配線基
板を電気的に接続するものである。Means for Solving the Problems In order to solve the above-mentioned problems, the method for manufacturing a semiconductor device of the present invention forms a protruding electrode on a wiring board, aligns the protruding electrode with the electrode of a semiconductor element, and then removes the semiconductor element. After the connection is made under pressure while heating, an insulating adhesive is applied between the semiconductor element and the wiring board and cured, thereby electrically connecting the semiconductor element and the wiring board.
作用
上記製造方法では、半導体素子の電極が半導体素子の面
積内で配線基板に形成した突起状電極と接続され、接着
剤にて半導体素子を配線基板に固着するため、半導体素
子の不良や接続不良があった場合でも接着剤を特定の溶
剤で溶解するか、あるいは熱的に接着剤を分解すること
によって別の半導体素子を再実装することが可能となる
。しかも、半導体素子へのモールドは不要となり、さら
にスペース的ｆこも小さくなり高密度配線に有利となる
。Effects In the above manufacturing method, the electrodes of the semiconductor element are connected to the protruding electrodes formed on the wiring board within the area of the semiconductor element, and the semiconductor element is fixed to the wiring board with adhesive, so there is no possibility of defects in the semiconductor element or poor connections. Even in such cases, it is possible to remount another semiconductor element by dissolving the adhesive with a specific solvent or thermally decomposing the adhesive. Furthermore, there is no need to mold the semiconductor element, and the space f is also reduced, which is advantageous for high-density wiring.
実施例 以下、本発明の一実施例を図面ｆこ基づいて説明する。Example DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
なお、従来例の第５図の構成部品と同一の部品には同一
の符号を付して説明を省略する。Components that are the same as those of the conventional example shown in FIG.
第１図（ａ）〜（ｄ）は本発明の半導体装置の製造方法
を順に示す工程断固図である。FIGS. 1(a) to 1(d) are step-by-step diagrams sequentially showing the method for manufacturing a semiconductor device of the present invention.
まず第１図（ａ）に示すようなＡｌ電極５を片面に設け
たＬＳＩテップ４を用意する。First, an LSI chip 4 having an Al electrode 5 on one side as shown in FIG. 1(a) is prepared.
一方第１図（ｂ）に示すように、配線基板１として平面
度の良好なガラス基板やセラミック基板を選び、配線基
板１の一方の内に薄膜のＡｕを導体配線２として形成し
、続いて導体配線２上でＬＳＩチッフ４ノＡｌｔＩＬ極
５ノ位置に合わせてエツチングマスクを用いてＡｕペー
ストを印刷し焼成してＡｕの突起状電極３を形成する。On the other hand, as shown in FIG. 1(b), a glass substrate or a ceramic substrate with good flatness is selected as the wiring board 1, a thin film of Au is formed as a conductor wiring 2 on one side of the wiring board 1, and then Au paste is printed on the conductor wiring 2 using an etching mask in alignment with the positions of the LSI chip 4 and the AltIL pole 5, and is fired to form the protruding Au electrodes 3.
本実施例では突起状電極３のサイズを直径約８０μｍ１
膜厚２ｏμｍとしている。In this embodiment, the size of the protruding electrode 3 is approximately 80 μm in diameter.
The film thickness is 20 μm.
次に第１図（ｄに示すように、ＬＳＩチップ４をヒータ
を内蔵した加圧ツール６で吸着し、配線基板１の突起状
電極３にＬＳＩチップ４のＡｌ電極５の位置合わせを行
い、加熱しながら接触、加圧する。Next, as shown in FIG. 1(d), the LSI chip 4 is adsorbed using a pressure tool 6 with a built-in heater, and the Al electrode 5 of the LSI chip 4 is aligned with the protruding electrode 3 of the wiring board 1. Contact and pressurize while heating.
本実施例では、ヒータｌζより温度を３５０″ＣＪこ保
持し、加圧を１５０ｇ／ＩＩＣ極とし、加圧時間を２〜
３秒としており、突起状電極３はおよそ６μｍ程圧縮さ
れる。加圧が終わると、加圧ツール６をはずしても、Ａ
Ｊ［極５とＡｕの突起状電極３とが共晶接合されて、Ｌ
ＳＩチップ４はしっかりと配線基板１に接続される。In this example, the temperature was maintained at 350"CJ by the heater lζ, the pressure was set to 150g/IIC pole, and the pressure was applied for 2 to 30"CJ.
The time is 3 seconds, and the protruding electrode 3 is compressed by approximately 6 μm. When the pressure is finished, even if the pressure tool 6 is removed, the A
J[The pole 5 and the Au protruding electrode 3 are eutectic bonded, and L
SI chip 4 is firmly connected to wiring board 1.
次に第１図（ｄ）に示すように、ＬＳＩチップ４の側面
より絶縁性接着剤７をＬＳＩチップ４と配線基板１との
間に浸透させて硬化させる。本実施例では接着強度が高
い紫外線硬化型接着剤を使用している。以上でＬＳＩチ
ップ４の配線基板１への実装は終了する。Next, as shown in FIG. 1(d), the insulating adhesive 7 is infiltrated between the LSI chip 4 and the wiring board 1 from the side surface of the LSI chip 4 and hardened. In this embodiment, an ultraviolet curing adhesive with high adhesive strength is used. This completes the mounting of the LSI chip 4 onto the wiring board 1.
また、第１図（ｃ）に示したＡＩＮ極５と突起状電極３
との接合の際に、第２図に示すように、加圧ツール６に
ＬＳＩチップ４を吸着しｔこままで、所定温度を３５０
℃に保持し、突起状電極３を加圧（１００ｇ／ｌ電極）
しながら、配線基板ｌに水平な方向Ａに、左右に各１０
μｍずつ摩擦運動を１回行うと、より確実な接合を行う
ことができる。本実施例では加圧・摩擦運動時間は２〜
３秒としており、このとき突起状電極３はおよそ６μｍ
程圧縮される。In addition, the AIN pole 5 and the protruding electrode 3 shown in FIG.
As shown in FIG.
℃ and pressurize the protruding electrode 3 (100 g/l electrode)
10 each on the left and right in the direction A horizontal to the wiring board l.
If the frictional movement is performed once in micrometer increments, more reliable joining can be achieved. In this example, the pressurization/friction motion time is 2~
3 seconds, at which time the protruding electrode 3 has a thickness of approximately 6 μm.
It is compressed as much as possible.
また、第１図（ｃ）に示したＡ／電極５と突起状電極３
との接合の際に、第３図に示すように、配線基板１の下
のステージ８にヒータ９を内蔵させ、ステージ温度を１
００°Ｃに保温し、配線基板１を加熱すると、ＬＳＩチ
ップ４の突起状電極３への加圧接続条件が同じ場合加圧
時間を１〜２秒に短縮することができる。In addition, the A/electrode 5 and the protruding electrode 3 shown in FIG.
As shown in FIG. 3, a heater 9 is built into the stage 8 under the wiring board 1 to lower the stage temperature to
If the wiring board 1 is heated by keeping it at 00°C, the pressurizing time can be shortened to 1 to 2 seconds if the conditions for pressurizing and connecting the LSI chip 4 to the protruding electrodes 3 are the same.
また、ＬＳＩチップ４を配線基板ｌに固着するために、
絶縁性接着剤７を使用しているが、接着剤７の熱膨張係
数α。が突起状電極３を形成するＡｕの熱膨張係数α１
より大きい場合、高温時に材料の膨張の差によって突起
状電極３とＬＳＩ電極５のＡｕ −Ａ／共晶接合が破壊
され断線することが予想される。In addition, in order to fix the LSI chip 4 to the wiring board l,
Although the insulating adhesive 7 is used, the coefficient of thermal expansion α of the adhesive 7 is is the thermal expansion coefficient α1 of Au forming the protruding electrode 3
If it is larger, it is expected that the Au-A/eutectic bond between the protruding electrode 3 and the LSI electrode 5 will be destroyed and disconnected due to the difference in material expansion at high temperatures.
第４図１こ接着剤Ａ（α。＝９０Ｘ１０ ’／”Ｃ）と
接着剤Ｂ（αｏ＝４５０Ｘ１０ ’／”Ｃ）の熱衝撃テ
スト（−５５°Ｃ→、１２５°Ｃ）の結果を示す。突起
状電極３は直径８０μｍで膜厚が２０μｍと１０μｍの
ものを用意した。Figure 4 shows the results of the thermal shock test (-55°C→, 125°C) of adhesive A (α = 90 x 10'/''C) and adhesive B (αo = 450 x 10'/''C) . The protruding electrodes 3 were prepared with a diameter of 80 μm and film thicknesses of 20 μm and 10 μm.
テスト結果によると、熱膨張係数α。がＡｕの膨張係数
α、よりも小さい場合、２０００サイクルでも異常は生
じないことが確認された。According to the test results, the thermal expansion coefficient α. It was confirmed that no abnormality occurs even after 2000 cycles when is smaller than the expansion coefficient α of Au.
また、突起状電極３を形成した後に、大気中の粉塵や有
機物などが、突起状電極３に付着したときにはＡ１１ｌ
極５との接続ができないことは明らかであり、不良率を
高める原因となる。それら大気中の粉塵や有機物などを
除去するために加圧接続前に放電処理を実施した。それ
によると、接続不良率はＬＳＩチップ４の自身による不
良の他はほぼ皆無Ｉこすることができた。In addition, if dust or organic matter in the atmosphere adheres to the protruding electrode 3 after forming the protruding electrode 3, A11l
It is clear that connection with pole 5 cannot be made, which causes an increase in the defective rate. In order to remove dust and organic matter from the atmosphere, discharge treatment was performed before pressurizing the connection. According to this, the connection failure rate was almost completely eliminated except for failures caused by the LSI chip 4 itself.
このように、ＬＳＩチップ４を配線基板１に実装するこ
とにより、ＬＳＩチ・７プ４の不良や接続不良があった
場合でも接着剤７を特定の溶剤で溶解するか、あるいは
熱的に接着剤７を分解することにまって別のＬＳＩチッ
プ４を再実装することができ、配線基板１を廃棄すると
いうロスをなくすこと力Ｓできる。またＬＳＩチップ４
を樹脂でモールドする必要がなくなり、さらにＬＳＩチ
ップの取り付ζすスペースも小さくでき、高密度配線を
実現できる。By mounting the LSI chip 4 on the wiring board 1 in this way, even if there is a defect in the LSI chip 4 or a poor connection, the adhesive 7 can be melted with a specific solvent or bonded thermally. Another LSI chip 4 can be remounted by decomposing the agent 7, and the loss of discarding the wiring board 1 can be eliminated. Also, LSI chip 4
There is no need to mold the LSI chip with resin, and the space for mounting the LSI chip can also be reduced, making it possible to realize high-density wiring.
発明の効果
以上のように本発明によれば、配線基板ｌこ突起状電極
を形成し、突起状電極と半導体素子の電極を接触させて
、半導体素子を加熱しながら加圧接続した後に、半導体
素子と配線基板間に絶縁性接着剤を塗布浸透させ硬化す
ることにより次に示す効果を有すら。Effects of the Invention As described above, according to the present invention, a protruding electrode is formed on a wiring board, the protruding electrode is brought into contact with an electrode of a semiconductor element, and the semiconductor element is connected under pressure while heating. By applying an insulating adhesive between the element and the wiring board, allowing it to penetrate and harden, the following effects can be achieved.
（１１半導体素子が不良であった場合でも、接着剤を特
定の溶剤か、あるいは加熱による接着剤の分解により、
不良の半導体素子を配線基板より取りはずし新しい半導
体素子に交換して再接続させることができるため、配線
基板のロスをなくすことができる。(11 Even if the semiconductor element is defective, the adhesive can be replaced with a specific solvent or by heating to decompose the adhesive.)
Since the defective semiconductor element can be removed from the wiring board, replaced with a new semiconductor element, and reconnected, loss of the wiring board can be eliminated.
（２） 半導体素子と配線基板間に絶縁性接着剤を介
在させるために半導体素子全体を樹脂モールドする必要
がなくなり、所要スペースを小さくできる。(2) There is no need to resin mold the entire semiconductor element to interpose an insulating adhesive between the semiconductor element and the wiring board, and the space required can be reduced.
（３） 半導体素子の電極の対向面にて突起状電極と
接続されるために、極めて高い実装密度の回路基板が実
現できる。(3) Since the electrodes of the semiconductor element are connected to the protruding electrodes on the opposing surface, a circuit board with extremely high packaging density can be realized.
（４）突起状電極は印刷方式にて一括して多数の形成が
可能であるために極めて量産性に優れ、低価格に実現で
きる。(4) Since a large number of protruding electrodes can be formed at once using a printing method, they are extremely suitable for mass production and can be realized at low cost.
（５） 絶縁性接着剤の熱膨張係数が突起状電極の熱
膨張係数よりも小さくすると、熱衝撃テストをはじめ高
温高湿テスト高温負荷テストなどの信頼性テストに極め
て高い性能を実現できる。(5) When the thermal expansion coefficient of the insulating adhesive is smaller than that of the protruding electrode, extremely high performance can be achieved in reliability tests such as thermal shock tests, high temperature and high humidity tests, and high temperature load tests.
第１図（ａ）〜（（至）は本発明の半導体装置の製造方
法を順に示す工程断面図、第２図は第１図（ｃ）の加圧
工程に摩擦運動を付加しｔこ断簡図、第３図は第１図（
ｃ）の加圧工程にステージ加熱を付加した断簡図、第４
図は本発明の半導体装置の製造方法において異なる絶縁
性接着剤を使用したときの熱衝撃テスト時の特性図、第
５図（ａ）〜（ｃ）は従来の半導体装置の製造方法を順
に示す工程断面図である。
１・・・配線基板、２・・・導体配線、３・・・突起状
電極、４・・・ＬＳＩチップ、５・・・ＡＪＩＩ！極、
６・・・加圧ツール、７・−・絶縁性接着剤、８・・・
加熱ステージ、９・・・ヒータ。Figures 1(a) to (to) are process cross-sectional views sequentially showing the method for manufacturing a semiconductor device of the present invention, and Figure 2 is a cross-sectional view in which frictional motion is added to the pressurizing process of Figure 1(c). Figure, Figure 3 is Figure 1 (
A simplified diagram showing stage heating added to the pressurizing process in c), No. 4
The figure shows characteristics during a thermal shock test when different insulating adhesives are used in the semiconductor device manufacturing method of the present invention, and FIGS. 5(a) to 5(c) sequentially show the conventional semiconductor device manufacturing method. It is a process sectional view. 1... Wiring board, 2... Conductor wiring, 3... Protruding electrode, 4... LSI chip, 5... AJII! very,
6... Pressure tool, 7... Insulating adhesive, 8...
Heating stage, 9...heater.
Claims (1)
し焼成して実装する半導体素子の電極位置に合わせてＡ
ｕの突起状電極を形成する工程と、この突起状電極と前
記半導体素子の電極の位置合わせを行い、半導体素子の
電極を突起状電極に接触させ、半導体素子を加熱しなが
ら前記絶縁性基板に加圧する工程と、前記半導体素子と
前記絶縁性基板の間に絶縁性接着剤を塗布浸透させ硬化
し、半導体素子を絶縁性基板に固着するとともに前記突
起状電極と半導体素子の電極を電気的に接続する工程を
有する半導体装置の製造方法。 ２、半導体素子を加熱しながら絶縁性基板に加圧すると
きに、半導体素子の電極と突起状電極を接触させながら
相対的に摩擦運動をさせることを特徴とする請求項１記
載の半導体装置の製造方法。 ３、半導体素子を加熱しながら絶縁性基板に加圧すると
きに、半導体素子と絶縁性基板の双方を加熱しながら半
導体素子を絶縁性基板に加圧することを特徴とする請求
項１および請求項２記載の半導体装置の製造方法。 ４、絶縁性接着剤の熱膨張係数が突起状電極の熱膨張係
数より小さいことを特徴とする請求項１、請求項２およ
び請求項３記載の半導体装置の製造方法。 ５、突起状電極を形成するときに、突起状電極形成後こ
の突起状電極の表面を放電処理することを特徴とする請
求項１、請求項２、請求項３および請求項４記載の半導
体装置の製造方法。[Claims] 1. Au paste is printed on an insulating substrate having conductor wiring, and A is printed in accordance with the electrode position of the semiconductor element to be mounted by baking.
A process of forming a protruding electrode u, aligning the protruding electrode with the electrode of the semiconductor element, bringing the electrode of the semiconductor element into contact with the protruding electrode, and heating the semiconductor element while heating the insulating substrate. Applying pressure, applying an insulating adhesive between the semiconductor element and the insulating substrate, allowing it to harden, fixing the semiconductor element to the insulating substrate, and electrically connecting the protruding electrode and the electrode of the semiconductor element. A method for manufacturing a semiconductor device including a step of connecting. 2. Manufacturing the semiconductor device according to claim 1, wherein when applying pressure to the insulating substrate while heating the semiconductor element, the electrodes of the semiconductor element and the protruding electrodes are brought into contact with each other and subjected to relative frictional motion. Method. 3. Claims 1 and 2, characterized in that when pressing the insulating substrate while heating the semiconductor element, the semiconductor element is pressed against the insulating substrate while heating both the semiconductor element and the insulating substrate. A method of manufacturing the semiconductor device described above. 4. The method of manufacturing a semiconductor device according to claim 1, 2, or 3, wherein the thermal expansion coefficient of the insulating adhesive is smaller than that of the protruding electrode. 5. The semiconductor device according to claim 1, claim 2, claim 3, and claim 4, wherein when forming the projecting electrode, the surface of the projecting electrode is subjected to a discharge treatment after forming the projecting electrode. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32317789A JPH03184352A (en) | 1989-12-13 | 1989-12-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32317789A JPH03184352A (en) | 1989-12-13 | 1989-12-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03184352A true JPH03184352A (en) | 1991-08-12 |
Family
ID=18151936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32317789A Pending JPH03184352A (en) | 1989-12-13 | 1989-12-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03184352A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998001901A1 (en) * | 1996-07-04 | 1998-01-15 | Matsushita Electric Industrial Co., Ltd. | Ic discarding apparatus for flip chip mounting facility |
-
1989
- 1989-12-13 JP JP32317789A patent/JPH03184352A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998001901A1 (en) * | 1996-07-04 | 1998-01-15 | Matsushita Electric Industrial Co., Ltd. | Ic discarding apparatus for flip chip mounting facility |
| US6129203A (en) * | 1996-07-04 | 2000-10-10 | Matsushita Electric Industrial Co., Ltd. | IC discarding apparatus for flip chip mounting facility |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5601675A (en) | Reworkable electronic apparatus having a fusible layer for adhesively attached components, and method therefor | |
| JPS60262430A (en) | Manufacture of semiconductor device | |
| JP2004363434A (en) | Electronic circuit device and its manufacturing method | |
| JP3760063B2 (en) | Electronic package manufacturing method by simultaneous curing of adhesive and encapsulant | |
| JP3451987B2 (en) | Functional element, substrate for mounting functional element, and method of connecting them | |
| US6762506B2 (en) | Assembly of semiconductor device and wiring substrate | |
| JPH1041615A (en) | Substrate for mounting semiconductor chip and method for mounting semiconductor chip | |
| JPH05218137A (en) | Manufacture of semiconductor device | |
| JPH0121620B2 (en) | ||
| JPS63151033A (en) | Manufacture of semiconductor device | |
| JP3163751B2 (en) | Method for manufacturing semiconductor device | |
| JPH03184352A (en) | Manufacture of semiconductor device | |
| JP2002198458A (en) | Semiconductor device and its manufacturing method | |
| JP2000068321A (en) | Semiconductor device and manufacture thereof | |
| JP2000252391A (en) | Wiring board for mounting semiconductor device and its mounting structure | |
| JP2003197681A (en) | Electronic apparatus | |
| JP3472342B2 (en) | Method of manufacturing semiconductor device package | |
| JP2765139B2 (en) | Method for manufacturing semiconductor device | |
| JPH09266227A (en) | Bonding method of electronic parts | |
| JP2000174066A (en) | Method of mounting semiconductor device | |
| JP2001237277A (en) | Taped wiring board and method for assembling the same | |
| JP3271404B2 (en) | Terminal connection method for chip components | |
| JP2004146540A (en) | Connection type circuit substrate and manufacturing method therefor | |
| JP3277830B2 (en) | How to assemble electronic components | |
| JP3319127B2 (en) | Semiconductor device and manufacturing method thereof |