JP3217559B2 - LCD drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit used in a device using a liquid crystal display panel such as a liquid crystal TV and a liquid crystal projection.

[0002]

2. Description of the Related Art Generally, a liquid crystal drive circuit for driving an active matrix type liquid crystal panel includes a clock generation circuit for generating a horizontal system clock, a vertical system clock and a system system clock based on a horizontal synchronization signal and a vertical synchronization signal. A driving signal generating circuit for generating a liquid crystal driving signal based on a system clock from a video signal, and a driving circuit for applying the liquid crystal driving signal to a liquid crystal panel in a predetermined manner under the control of horizontal and vertical clocks. Consists of

FIG. 12 shows a configuration of an example of a clock generation circuit among these circuit portions.

The clock generation circuit 27 receives a clock signal f _VCO synchronized with the horizontal synchronizing signal and having a frequency multiplied by N, a horizontal reference signal HPL synchronized with the horizontal synchronizing signal and having the same frequency, and a vertical synchronizing signal VD. And outputs a plurality of horizontal system clocks, vertical system clocks, and system system clocks based on these. The horizontal clock is a clock for horizontal scanning of the liquid crystal panel, and the vertical clock is a clock for vertical scanning of the liquid crystal panel.
These are supplied to the horizontal drive circuit and the vertical drive circuit, respectively. on the other hand,
The system clock is a clock used to create a liquid crystal drive signal from a video signal, and is supplied to a drive signal creation circuit.

[0005] The clock generation circuit 27 outputs a clock signal f
Horizontal down counter 29 that counts down the _VCO ,
Horizontal counter 3 for counting clock signal f _VCO
0, a horizontal decoder 31 that decodes the output from the horizontal counter and uses it as a horizontal clock, a vertical down counter 32 that counts down the horizontal reference signal, and a vertical that counts the output (HRT signal) from the horizontal down counter 29 A system-related counter 33, a vertical-system decoder 34 which decodes the output from the vertical-system counter 33 and uses it as a vertical-system clock.
And f _VCO signal, horizontal reference signal HPL, vertical synchronization signal V
D, the output of the vertical down counter (VRT signal) and the output of the horizontal down counter (HRT signal) are input, and the system clock generating circuit 35 generates a system clock.

The horizontal system down counter 29 is for adjusting the display start horizontal position with respect to the horizontal synchronizing signal of an image, and an initial value is preset from outside by means not shown, and reset (down count start) by a horizontal reference signal. ) Is done. The horizontal counter 30 indicates the current display horizontal position, and is reset (count starts) by the output (HRT signal) of the horizontal down counter.

On the other hand, the vertical down counter 32 is for adjusting the display start vertical position with respect to the vertical synchronizing signal of the video, and its initial value is preset from outside by means not shown, and reset (down counting) by the vertical synchronizing signal. Started). The vertical counter 33 indicates the current display vertical position (the number of lines), and is reset (starts counting) by the output (VRT signal) of the vertical down counter 32.

The output (VRT signal) of the vertical down counter is output to the outside as a switching timing signal for AC driving of the liquid crystal panel.

According to the above configuration, first, the horizontal down counter 29 _{converts the} clock signal f _VCO to the horizontal reference signal HPL.
The HRT signal is output at the timing when the count value becomes 0 to drive the horizontal counter 30 at the next stage. The horizontal counter 30 counts and outputs the clock signal f _VCO at a timing based on the HRT signal.
1 and is logically decoded and output as a horizontal clock.

Similarly, the vertical down counter 32 counts down the horizontal reference signal HPL at a timing based on the vertical synchronizing signal VD, and outputs a VRT signal at a timing when the count value becomes 0, and outputs a VRT signal at the next stage. 33 is driven. The vertical counter 33 counts and outputs the output HRT signal of the horizontal down counter 29 at a timing based on the VRT signal, and the output is logically decoded by the vertical decoder 34 and output as a vertical clock.

Then, the system clock generating circuit 35
Are the horizontal and vertical down counters 29 and 3 together with the clock signal f _VCO , the horizontal reference signal HPL and the vertical synchronization signal VD.
2 to output a system clock.

[0012]

However, in such a conventional liquid crystal driving circuit, the reset interval (output interval of the VRT signal) of the vertical counter directly determines the number of driving lines of the LCD panel. When a signal having a smaller number of scanning lines (n) than the number of driving lines (m) is input, an undriven line portion is formed below the LCD panel, which may damage the LCD element.

Accordingly, the present invention scans all the driving lines of the LCD panel even when a signal having a smaller number of scanning lines (n) than the number of driving lines (m) of the LCD panel is input, and outputs the signals to the LCD elements. It is an object to provide a liquid crystal drive circuit capable of preventing damage before it occurs.

[0014]

SUMMARY OF THE INVENTION According to the present invention, there is provided a liquid crystal driving circuit for driving a liquid crystal display panel by alternating current with a video signal on a field-by-field basis. Between the means for counting the number of horizontal synchronizing signals based on the vertical synchronizing signal of the video signal input in order to obtain
a liquid crystal drive circuit comprising means for detecting the relationship of> n, and means for masking the reset signal input of the counting means based on the vertical synchronization signal during m> n.
The number of horizontal drive lines in the LCD
If it is larger than several m, the input drive exceeding m
Do not display dynamic horizontal lines, and
The number of driving horizontal lines is equal to the total number m of driving lines of the liquid crystal panel.
Is smaller than the driving horizontal line of the input field.
After driving in, drive horizontal line of next field reaches m
Display until the remaining drive horizontal line in the next field
This is achieved by a liquid crystal drive circuit characterized by no display .

In the above configuration, it is desirable to cancel the masking of the reset signal input immediately after the driving of the last line of the liquid crystal panel is completed, and even if the vertical synchronizing signal VD disappears, it is determined by the overflow signal of the counting means. , It is desirable to use provisional field information so as to scan all drive lines.

[0016]

By counting the number of horizontal synchronizing signals on the basis of the vertical synchronizing signal of the input video signal by the counting means, the current driving horizontal line number n can be obtained.
The number of drive lines of the liquid crystal panel is compared with the total number m, and while m> n, the input of the reset signal of the counting means based on the vertical synchronization signal is masked. As a result, when a signal having the number of lines n1 smaller than the number m of display lines of the liquid crystal panel is input, the vertical synchronization signal of the next field is masked and input.
Following the field following the number of lines n1
Is displayed until the total number m of drive lines is reached, and the next field
By not displaying the remaining driving horizontal lines, all the lines of the pseudo liquid crystal panel are driven. After the pseudo drive, if a signal having the number n2 of lines greater than the number m of display lines is input, the number of input drive horizontal lines exceeding m is input.
Since no masking time is displayed and the mask time of the vertical synchronizing signal is minimized, normal driving can be immediately restored.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 4 shows a liquid crystal display device (liquid crystal display) that reproduces a color image by synthesizing red, green, and blue light modulated by each of the liquid crystal display panels for red, green, and blue and projecting them on a screen in an enlarged manner. (Hereinafter, only the liquid crystal display panel for red is shown for convenience of explanation.)

In the figure, the portion excluding the liquid crystal panel denoted by 1 is a liquid crystal drive circuit. The liquid crystal panel 1 is of a TFT active matrix type in which a plurality of pixels are arranged in a matrix in the horizontal and vertical directions, and modulates incident red light according to a video signal (in this case, a red signal among three primary color signals). It works as a light valve.

More specifically, as shown in FIG. 5, the liquid crystal display panel 1 has a plurality of signal electrodes 2, scanning electrodes 3, TFTs 4, and pixel electrodes 5 on a first insulating substrate (not shown) side. A common electrode 6 is formed on the side of a second insulating substrate (not shown) while being formed in a matrix, and each pixel is constituted by a liquid crystal layer interposed between the common electrode 6 and each pixel electrode 5. The display is performed by line-sequential scanning by the signal electrodes 2 and the scanning electrodes 3.

Here, reference numeral 7 denotes an auxiliary capacitor provided in parallel with each pixel. Each TFT 4 has its source on the signal electrode 2 side,
The drain is connected to the pixel electrode 5 side, and the gate is connected to the scanning electrode 3 side. For example, when a scanning voltage is applied to the scanning electrode 3 in the first row, each T in the first row connected to the scanning electrode 3 is connected.
Each of the FTs 4 becomes conductive, each signal electrode 2 is connected to each pixel electrode 5 in the first row, and a signal voltage (that is, a video signal) is applied to each pixel in the first row.

Therefore, by repeating such an application operation in a horizontal cycle for each row sequentially from the first row, a video signal for one field can be displayed on the liquid crystal display panel 1. The image is reproduced by repeating every time, that is, in a vertical cycle.

In FIG. 4, reference numerals 8, 9 and 10, 11 denote left and right vertical scanning driving circuits and upper and lower horizontal scanning driving circuits disposed on the left, right, upper and lower sides of the liquid crystal display panel 1, respectively. The right vertical scanning driving circuits 8 and 9 alternately apply a scanning voltage to each scanning electrode 3 for each row, and the upper and lower horizontal scanning driving circuits 10 and 11 apply a scanning voltage to the signal electrode 2 for each column (for each pixel). ) The video signal is applied alternately.

More specifically, the upper and lower horizontal scanning drive circuits 10 and 11 are operated based on sampling start clocks SPDU and SPDL which are horizontal clocks, and each signal electrode 2 is driven at the timing of the sampling clocks CLDU and CLDL. The left and right vertical scanning driving circuits 8 and 9 output sampling start clocks SPSL, which are vertical clocks, alternately for each pixel.
Activated based on SPSR and sampling (acquisition)
At the timing of the clocks CLSL and CLSR, a scanning voltage is sequentially output to each scanning electrode 3 alternately for each row, and a video signal for each row is taken in. The polarity of the video signal supplied to the liquid crystal display panel 1 is inverted every vertical cycle as shown in FIG. 6, and the liquid crystal display panel 1 is AC-driven.

Reference numeral 21 denotes a vertical synchronizing input terminal to which a vertical synchronizing signal VD is input, 22 denotes a horizontal synchronizing input terminal to which a horizontal synchronizing signal HD is input, and 23 denotes a voltage controlled oscillator (hereinafter referred to as "VC").
O ”), a dividing cycle 25, and a phase comparator 26 (hereinafter,“ PLL (PH
ASE LOCKED LOOP) ")
The LL circuit 23 sets the oscillation output frequency f _VCO of the _VCO 24 to 1
After the phase comparator 26 compares the phase of the frequency- _divided output of the frequency divider 25 _divided by the frequency f _{HPL of} / N with the horizontal synchronization signal HD, the difference output from the phase comparator 26 in accordance with the phase difference. The signal voltage is supplied as a control voltage to the VCO 24 to control its oscillation output, and this operation is repeated until the phase difference disappears, so that an N-times oscillation output synchronized with the horizontal synchronization signal HD is obtained. That is, the PLL circuit 23
In the locked state, when the frequency of the horizontal synchronization signal HD is f _HD , f _HD = f _HPL = f _VCO · (1 / N).

Reference numeral 27 denotes an oscillation output and a horizontal reference signal H.
The horizontal system clock (CL) required for driving the liquid crystal display panel 1 based on the frequency division output as PL and the vertical reference signal VD.
DU, CLDL, SPDU, SPDL), vertical system clock (CLSL, CLSR, SPSL, SPSR), system system clock (ADCK, SSCK, HUCK, HL)
CK) for generating and outputting a clock.

The horizontal clock is V as shown in FIG.
The horizontal reference signal H obtained by phase-synchronizing the oscillation output of the CO 24 (see FIG. 3C) with the horizontal synchronization signal HD (see FIG. 3A).
The upper and lower sampling clocks CLDU and CLDL shown in FIGS. 4D and 4E are created by counting down at a timing based on the PL (see FIG. 4B).
The lower horizontal scanning drive circuits 10 and 11 are shifted by 180 ° from each other so as to alternately output video signals for each pixel, and sampling start clocks SPDU and SPDL shown in FIGS. Are shifted in phase by a half clock (one pixel) of the sampling clock, and all these clocks are phase-synchronized with the horizontal synchronizing signal HD.

As shown in FIG. 8, the vertical clock counts down the signal based on the horizontal reference signal HPL (see FIG. 8B) at the timing based on the vertical reference signal VD (see FIG. 8A). Left and right capture clocks CLSL, CLSR shown in FIGS.
Are shifted by 180 ° from each other so that the left and right vertical scanning driving circuits 8 and 9 alternately take in video signals for each row. The sampling start pulses SPSL and SPSL shown in FIGS. The phase of the SPSR is shifted by a half clock (one row) of the capture clock, and each of these clocks is eventually phase-synchronized with the horizontal synchronization signal HD.

The system clocks are as shown in FIG. 9. FIGS. 9A to 9D show clocks ADCK, SSCK, HUCK, HLC used for signal processing, respectively.
K. Similarly, all these clocks are phase-synchronized with the horizontal synchronization signal HD, so that signal processing synchronized with the input video signal can be performed. The clock generation circuit 27 will be described later in detail. 12 is a video signal (in this case,
A video input terminal to which the red signal of the three primary color signals) is input,
Reference numeral 13 denotes a system clock ADC for inputting the video signal.
An A / D converter 14 which samples from K and converts an analog signal to a digital signal, and 14 converts a digital signal from the A / D converter 13 into a system clock SSC
Signal processing circuit for performing digital signal processing based on K, 1
Reference numerals 5 and 16 denote the processed signals as system clocks H, respectively.
Upper and lower latch circuits, which are alternately latched at the timings of UCK and HLCK and are divided into upper and lower video signals supplied to the upper and lower horizontal scanning drive circuits 10 and 11, respectively, are latches 17 and 18. Upper and lower D / A converters for converting the signals from the circuits 15 and 16 into the original analog signals at the timing of the system clocks HUCK and HLCK, respectively, and 19 and 20 convert the converted analog video signals to the liquid crystal display panel 1. The upper and lower driving circuits 28 output to the upper and lower horizontal scanning driving circuits 10 and 11 respectively with the level and polarity necessary for the driving of the first and second horizontal scanning circuits are phase-synchronized with the vertical synchronizing signal VD output from the clock generating circuit 27. The vertical display position reference signal VRT thus generated is toggle counted, and its output is used as an inverted signal, and the upper and lower horizontal scanning drive circuits 10 and 11 are used.
The polarity of the video signal output from the upper and lower drive circuits 19 and 20 is inverted at a vertical cycle by horizontal binary counters (toggle flip-flops) respectively supplied to.

Specifically, the upper and lower drive circuits 19 and 2
In the configuration shown in FIG. 10, the polarity of the video signal is inverted and output in the vertical cycle in the configuration shown in FIG. 10 (here, since the upper and lower drive circuits 19 and 20 have the same configuration, only the upper side is shown. First, an analog video signal from the upper D / A converter 17 is supplied to the inverting amplifier 41.
The signal is amplified by inverting its polarity to the signal level necessary for driving the liquid crystal display panel 1 and the non-inverting amplifier 42
Are amplified without inverting their polarities up to the signal level necessary for driving the liquid crystal display panel 1, and are respectively switched by the polarity switching circuits 43.
Are supplied to the terminals a and b. The polarity switching circuit 43 has its terminal c alternately connected to the terminals a and b in a horizontal cycle based on the inversion signal, and alternately supplies inverted and non-inverted video signals to the upper horizontal scanning drive circuit 10. Will do.

For example, FIG. 11 shows an upper driving circuit 1 in an NTSC-HD converter system in which the number of horizontal scanning lines in one field is twice (525) the current NTSC broadcasting system.
9 (part of a two-field period), and assuming that the rising edge of the vertical display position reference signal VRT (see FIG. 9A) is the start of each field, VR
The inverted signal obtained by the toggle count of T is inverted between positive and negative in a vertical cycle as shown in FIG. 4B, and when the inverted signal is positive, the terminals bc of the polarity switching circuit 43 are turned on. When the inversion signal is negative, the terminals a and c of the polarity switching circuit 43 are turned ON, and the video signal (see FIG. 3C) supplied to the upper drive circuit 19 is as shown in FIG. The polarity is alternately inverted in the vertical cycle and output. That is, in this case, the polarity of the video signal supplied to the liquid crystal display panel 1 is inverted for each field, and the liquid crystal display panel 1 is driven by an alternating current in which the accumulated voltage is zero.

Next, the clock generation circuit will be described in more detail with reference to the block diagram shown in FIG.

The clock generation circuit 27 has a horizontal down counter 29 for down counting the clock signal f _VCO from the _VCO 24 and a horizontal counter 30 for counting the signal f _VCO , similarly to the conventional clock generation circuit described in detail with reference to FIG. A horizontal decoder 31 that decodes the output from the horizontal counter and uses it as a horizontal clock, a vertical down counter 32 that counts down the horizontal reference signal, and a vertical decoder that counts the output (HRT signal) from the horizontal down counter 29. A counter 33, a vertical decoder 34 which decodes the output from the vertical counter 33 and uses it as a vertical clock, a clock signal f _VCO , a horizontal reference signal HPL,
The system includes a system clock generation circuit 35 to which a vertical synchronization signal VD, a VRT signal, and an output (HRT signal) of a horizontal down counter are input and generates a system clock.

Here, the horizontal system down counter 29 is for adjusting a display start horizontal position with respect to a horizontal synchronizing signal of an image, and an initial value is preset from outside by means (not shown) and reset by a horizontal reference signal ( The countdown is started). Also, the horizontal counter 30
Is used to indicate the current display horizontal position, and is reset (starts counting) by the output (HRT signal) of the horizontal down counter.

On the other hand, the vertical down counter 32 is for adjusting the display start vertical position with respect to the vertical synchronizing signal of the video. The initial value is preset by means not shown from the outside, and reset (down counting) by the vertical synchronizing signal. Started). The vertical counter 33 indicates the current display vertical position (the number of lines).

The clock generation circuit 27 further includes a register 3 for storing the number of drive lines of the liquid crystal display panel.
6. When the VD disappears, the vertical down counter 32 outputs an overflow signal (RCO signal) of the vertical counter 33 in place of the output VS from the vertical down counter 32 as a reset signal of the vertical counter. And an AND gate 38 for masking an output signal VSR from the OR gate 37 to which the output VS of the vertical system counter 33 and the overflow signal of the vertical counter 33 are input.
The number (m) of drive lines of the liquid crystal display panel stored in the register is compared with the output (n) of the vertical counter 33, and the output C is controlled to control the opening and closing of the AND gate 38.
A comparator 39 for supplying OMP to an AND gate 38 and a switch group 40 for presetting the number of drive lines of the liquid crystal display panel in the register 36 are provided.

Here, the output of the AND gate 38 is supplied as a vertical position reference signal VRT to the reset input of the vertical counter 33 and the system clock generation circuit 35, and is also output to the outside as an AC drive switching timing signal.

According to the above configuration, first, the clock signal f
_{The VCO} is _supplied with a horizontal reference signal H by a horizontal down counter 29.
The counter is down-counted at the timing based on the PL, and the HRT signal is output at the timing when the count value becomes 0 to drive the horizontal counter 30 at the next stage. The horizontal counter 30 counts and outputs the clock signal f _VCO at a timing based on the HRT signal, and its output is logically decoded by the horizontal decoder 31 and output as a horizontal clock.

On the other hand, the register 36 stores the SW group 40 (SW
O, SW1, SW2,..., SW9), the value m (the number of driving lines of the liquid crystal display panel) is stored and held. The vertical down counter 32 counts down the horizontal reference signal HPL at a timing based on the input signal VD as in the conventional example, and generates a signal VS at a timing when the count value becomes zero. That is, VD and VS are positive polarity signals having the same period and phase-shifted.

The VS signal is input to the OR gate 37 together with the RCO signal which is an overflow signal of the vertical counter 32. The output signal VSR of the OR gate 37 is input to the AND gate 38 together with the COMP signal output from the comparator 39. The output signal of the AND gate 38 is VR
The signal becomes a T signal, resets the vertical counter 33, and drives the T-FF 28. Further, the vertical counter 33 counts up by the signal HRT down-counted at the timing based on the horizontal reference signal HPL, and outputs the value n to the comparator 39 and the vertical decoder 34. That is, the value n is the current drive line No. on the liquid crystal panel. Will be represented. The comparator 39 receives the value m from the register 36 and the value n from the vertical counter 33, and outputs a COMP signal as shown in Table 1 according to the relationship between these two values.

[0041]

[Table 1]

The operation of each of these signals is shown in FIG. FIG. 3 shows the respective display states.

When the number n of input signal lines is larger than the number m of panel drive lines (n> m overscan) As shown in FIG.
The output signal COMP becomes "H" level after 500 counts due to the count-up of the vertical counter. In this description, for convenience of explanation, the number of panel drive lines:
m = 500. Assuming that the number of lines of the input signal is n / field = 525, the VS signal is not masked by the AND gate 37, and the vertical counter 32 is reset as a VRT signal at a period of 525 / field. Therefore, all the drive lines can be driven as shown in FIG.

When the number n of input signal lines is smaller than the number m of panel drive lines (n <m underscan) As shown in FIG. 2, for example, if the number n of input signal lines / field = 350, the VS signal of the next field Is the minimum number of lines required to drive the panel m
= 500, the mask is masked by the AND gate 37, and the vertical counter 32 continues to count up. After 500 counts, the COMP signal changes from "L" to "H".
And simulately drive the shortage of 150 lines. COM
Since the P signal is at the "H" level, the VS signal of the next field is not masked, the vertical system counter 32 is reset again, and driving can be started from the first line of the panel.
This state is shown in FIG.

Loss of VD signal When the input signal VD is lost, the panel drive system loses the field order. However, as shown in FIG. 2, an RCO signal which is an overflow signal of the vertical counter 32 (for example, 9 bits: 512, 10 bits: 10
24) is output, and is output from the OR gate 36 in place of the VS signal.
Reset at the cycle of the signal. It is needless to say that the period can be determined by the number of bits of the vertical counter 33 or can be operated at an arbitrary period if the counter is replaced by a presettable counter. FIG. 3C shows this state.

In all of the above cases, the video is inverted for each field by the inversion signal generated from the T-FF 28 for toggle counting the VRT signal.

[0047]

As described above, according to the liquid crystal driving circuit of the present invention, the number of driving horizontal lines of the input field is equal to the number of liquid crystal driving lines.
If the total number of panel drive lines is greater than m,
Input drive horizontal lines are not displayed
The number of driven horizontal lines in the field
Is smaller than the total number m of drive lines,
The next field drive following the field drive horizontal line
Display the moving horizontal line until it reaches m, then the next field
By not displaying the remaining drive horizontal lines , the liquid crystal display panel can be driven by all the drive lines, and the liquid crystal can be AC driven, regardless of the relationship between the number n of input signal lines and the minimum number m of lines required for driving the liquid crystal display panel. Further, even if the VD is lost or the field information is lost, the same can be dealt with. In addition, an increase in the vertical synchronization re-locking time which can be considered by masking the VD signal does not cause a problem because the VD mask period is minimized.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of a clock generation circuit used in a liquid crystal drive circuit of the present invention. .

FIG. 2 is a waveform diagram illustrating an operation of the clock generation circuit shown in FIG.

FIG. 3 is a diagram schematically showing a display state when the clock generation circuit shown in FIG. 1 is used.

FIG. 4 is a circuit block diagram of one embodiment of a liquid crystal drive circuit of the present invention.

FIG. 5 is a diagram schematically showing a configuration of a liquid crystal panel.

FIG. 6 is a diagram schematically illustrating an example of video signal inversion AC driving.

FIG. 7 is a timing chart showing a horizontal system clock.

FIG. 8 is a timing chart showing a vertical system clock.

FIG. 9 is a timing chart showing a system clock.

FIG. 10 is a circuit block diagram of a drive circuit.

FIG. 11 is a schematic diagram showing field AC inversion driving.

FIG. 12 is a circuit block diagram of a conventional clock generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 8, 9 Vertical scanning drive circuit 10, 11 Horizontal scanning drive circuit 12 Video input terminal 13 A / D converter 14 Signal processing circuit 15, 16 Latch 17, 18 D / A converter 19, 20 Drive circuit 21 Vertical Synchronization signal input terminal 22 Horizontal synchronization signal input terminal 23 PLL 27 Clock generation circuit 28 Horizontal binary counter 29 Horizontal system down counter 30 Horizontal system counter 31 Horizontal system decoder 32 Vertical system down counter 33 Vertical system counter 34 Vertical system decoder 35 System system Clock generation circuit 36 Register 37 OR gate 38 AND gate 39 Comparator 40 Switch group

Claims (3)

(57) [Claims] 1. A liquid crystal drive circuit for driving a liquid crystal display panel by alternating current with a video signal for each field, wherein a vertical synchronizing signal of a video signal inputted to obtain a current driving horizontal line number n in one field is used as a reference. Means for counting the number of horizontal synchronization signals; means for detecting the relationship m> n between the total number m of drive lines of the liquid crystal panel; and means for counting based on the vertical synchronization signal between m> n. liquid crystal drive circuit and means for masking the input of the reset signal
The number of driving horizontal lines in the input field is
Exceeds m when the total number of drive lines
Of the input horizontal drive line is not displayed and
The number of driving horizontal lines in the field
If the total number of moving lines is less than m,
Next field drive water following the field drive horizontal line
The flat line is displayed until it reaches m, and the rest of the next field is displayed.
A liquid crystal drive circuit characterized in that no horizontal drive lines are displayed . 2. The liquid crystal driving circuit according to claim 1, wherein the reset signal input mask is released immediately after driving the last line of the liquid crystal panel. 3. The liquid crystal drive according to claim 1, wherein even if the vertical synchronizing signal VD is lost, all the driving lines can be scanned by using the overflow signal of the counting means as temporary field information. circuit.