JP3182769B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor applied to an active matrix type liquid crystal display, an image sensor and a three-dimensional integrated circuit.

[0002]

2. Description of the Related Art An example of the structure of a conventional thin film transistor will be described with reference to FIG. This is a cross-sectional view of the structure in the channel direction. The insulating substrate 1 is made of glass, quartz, sapphire, or the like.
A base insulating film 102 made of a silicon oxide film or the like is formed on the substrate 01, and patterns (pads) 103 and 104 made of a silicon thin film such as a polycrystalline silicon are formed thereon. A pattern made of a silicon thin film such as polycrystalline silicon is provided so as to be in contact with the upper side of these pads 103 and 104 and connect them. At this time, the thickness of the silicon thin film pattern is formed smaller than the thickness of the pads 103 and 104. Next, these are entirely covered with a gate insulating film 105 made of an insulating film such as a silicon oxide film.
A gate electrode 106 made of a metal, a transparent conductive film or the like is formed thereon.
Are formed. Here, an impurity serving as a donor or an acceptor is added to the silicon thin film in a self-aligned manner with the gate electrode 16.
08 forms a source region or a drain region together with a pad. Further, a region which is covered with the gate electrode and to which no impurity is added becomes the channel portion 109. Further, the entire structure is covered with an interlayer insulating film 110 made of an insulating film such as a silicon oxide film. A source electrode 111 made of a metal, a transparent conductive film or the like is provided in the source region, and a drain electrode 112 is provided in the drain region.
3 mainly contacts the pads 103 and 104. However, ion implantation is generally used as a method for forming a source region and a drain region by adding an impurity serving as a donor or an acceptor, but this destroys the crystallinity of the silicon thin film. By subsequent thermal annealing or the like, the thick pads 103, 10
Although the crystallinity of No. 4 can be recovered, the crystallinity of the thin film regions 107 and 108 cannot be recovered and becomes a large resistance component. As a result, a new problem such as a decrease in on-current has occurred. As a countermeasure against this, it is effective to reduce the dose at the time of ion implantation, but in this case, it is difficult to connect the source electrode and the source region, and similarly, the drain electrode and the drain region. On the other hand, if the thickness of the thin regions 107 and 108 is increased in order to recover the crystallinity, the thickness of the channel region is also increased, and in this case, it is known that the on-current is significantly reduced. ing. This is particularly serious on the Nch transistor side.

Therefore, a thin film transistor in which only the impurity concentration of the pad portion is increased has been considered. An example of the structure of the thin film transistor will be described with reference to FIG. This is a structural cross-sectional view in the channel direction. A base insulating film 202 made of a silicon oxide film or the like is formed on an insulating substrate 201 made of glass, quartz, sapphire, or the like, on which impurities serving as donors or acceptors are added. Pads 203 and 204 made of a silicon thin film such as polycrystalline silicon are formed. A pattern made of a silicon thin film such as polycrystalline silicon is provided in contact with the upper ends of the pads 203 and 204 so as to connect them. A gate insulating film 205 made of an insulating film such as a silicon oxide film covers the whole of them, and a gate electrode 206 made of a metal, a transparent conductive film, a polycrystalline silicon film doped with impurities, and the like is formed thereon. . Here, an impurity serving as a donor or an acceptor is added to the silicon thin film in a self-aligned manner with the gate electrode 206, and the regions 207, 2
08 forms a source region or a drain region together with a pad. A region to which no impurity is added becomes a channel portion 209. Further, the entire structure is covered with an interlayer insulating film 210 made of an insulating film such as a silicon oxide film. A source electrode 211 made of a metal, a transparent conductive film or the like is provided in the source region, and a drain electrode 212 is provided in the drain region.
3, 204. At this time, the pads 203 and 20
The impurity concentration of No. 4 is set higher than the impurity concentrations of the other source and drain regions 207 and 208. Also, the thickness of the pad portions 203 and 204 is larger than the thickness of the other source region 207 and drain region 208.

A method of forming a CMOS using Nch and Pch thin film transistors having such a structure is described in FIG.
This will be described with reference to the process sectional views of FIG.

[0005] Insulating substrate 3 of glass, quartz, sapphire, etc.
01, a base insulating film 302 made of a silicon oxide film or the like
Is formed, and a silicon thin film such as polycrystalline silicon is deposited thereon, for example, at about 1500. This is selectively etched to form a pattern to be the pads 303 and 304 of the Nch thin film transistor portion and a pattern to be the pads 305 and 306 of the Pch thin film transistor portion. (Refer to FIG. 3A.) Subsequently, a resist pattern 307 is formed by using a light exposure technique, and phosphorus is selectively ion-implanted into the pads 303 and 304 of the Nch transistor portion at about 1 × 10 ¹⁵ cm ⁻² . (Refer to FIG. 3 (b).) Next, the resist pattern 307 is peeled off, and thereafter, a resist pattern 308 is similarly formed by using a light exposure technique.
Boron is selectively ion-implanted into the pads 305 and 306 of the channel transistor portion at about 1 × 10 ¹⁵ cm ⁻² . (See FIG. 3C.) Thereafter, the resist pattern 308 is peeled off, and the pads 303 and 30 of the Nch transistor portion are removed.
4. Pads 305 and 306 of the Pch transistor section are completed. (See FIG. 3D.) Next, the pads 303 and 304 of the Nch transistor portion and the pads 305 and 306 of the Pch transistor portion are in contact with the upper side of the pads, respectively.
Further, patterns 309 and 310 made of a silicon thin film such as about 250 polycrystalline silicon are provided so as to connect the pads. Next, the whole is covered with a gate insulating film 311 made of an insulating film such as a silicon oxide film, and gate electrodes 312 and 313 made of a metal, a transparent conductive film, a polycrystalline silicon film doped with impurities, and the like are formed thereon. . (See FIG. 3 (e).) Subsequently, approximately 2 × 10 ¹⁴ cm ⁻² of phosphorus is selectively ion-implanted into the Nch transistor portion, and the source region and the drain region are self-aligned with the gate electrode 312 of the Nch transistor. To form Similarly, boron is selectively ion-implanted into the Pch transistor portion at about 2 × 10 ¹⁴ cm ⁻² to form a source region and a drain region in self-alignment with the gate electrode 313 of the Pch transistor. At this time, the impurity concentration of the source region and the drain region is N
Both the ch section and the Pch section have thick pad sections 303, 3
For example, about 1 × 10 ²⁰ cm ^{−3 in} 04, 305, and 306;
The thin portions 314, 315, 316, and 317 have a thickness of, for example, about 1 × 10 ¹⁹ cm ⁻³ . At this time, the regions covered with the gate electrodes 312 and 313 and not doped with impurities become channel regions 318 and 319, respectively. (Refer to FIG. 8 (f).) After that, according to a normal process, an interlayer insulating film 320 made of a silicon oxide film, a contact hole 321, a source electrode 32 made of a metal, a transparent conductive film or the like.
2. Similarly, the drain electrode 323 is connected to the source region,
Connected to the drain region. (See FIG. 3 (g))

[0006]

In the above manufacturing method, ion implantation is performed using a resist pattern as a mask.
It is highly likely that this process will not be available in the future. That is, the conventional ion implantation apparatus is provided with a mass analyzer, and only required ions are selected and implanted. However, there is a disadvantage that it takes too much time to perform ion implantation on the entire large substrate. Therefore, an ion implantation apparatus without a mass analyzer is being developed. In that case, it is expected that the resist will not be maintained because the temperature of the substrate becomes considerably high. As a countermeasure, a method of masking with a silicon oxide film or the like instead of a resist is conceivable, but a simple replacement causes a problem as shown in the process cross-sectional view of FIG.

An insulating substrate 4 made of glass, quartz, sapphire, etc.
01, a base insulating film 402 made of a silicon oxide film or the like
Is formed, and a silicon thin film such as polycrystalline silicon is deposited thereon, for example, at about 1500. This is selectively etched to form a pattern to be the pads 403 and 404 of the Nch thin film transistor portion and a pattern to be the pads 405 and 406 of the Pch thin film transistor portion. (See FIG. 4A.) Subsequently, a silicon oxide film 407 is deposited so as to cover the entire surface, a resist pattern 408 is formed by using a light exposure technique, and the silicon oxide film 407 is selectively used by using this as a mask. Etch. (FIG. 4 (b)
However, at this time, a part of the underlying silicon oxide film 402 is also etched, and under the pattern which becomes the pads 403 and 404 of the Nch thin film transistor portion, the undercut occurs, and the silicon thin film, the gate electrode, the wiring, etc. which constitute the channel region thereafter. This has an adverse effect on the processing of the thin film transistor, which in turn affects the reliability of the thin film transistor.

[0008]

According to the present invention, in a method of manufacturing a CMOS semiconductor device, a step of forming a base insulating film on an insulating substrate; a step of forming a silicon thin film on the base insulating film; Forming a silicon oxide film on the thin film, selectively removing the silicon oxide film, implanting ions serving as donors of an Nch thin film transistor into the silicon thin film, and removing the silicon oxide film; Forming a new silicon oxide film on the silicon thin film, selectively removing the new silicon oxide film at a portion different from the portion where the ion is implanted into the silicon thin film;
a step of implanting ions serving as acceptors of the thin film transistor, a step of removing the new silicon oxide film, a step of forming the ion-implanted region of the silicon thin film in an island shape, and a step of forming the island shape. Forming a semiconductor device using the silicon thin film portion as a source / drain region of an Nch or Pch thin film transistor.

[0009]

By adding impurities in advance before forming a pad pattern, etching of the underlying silicon oxide film can be prevented. Accordingly, no scuffing occurs below the pad pattern.

[0010]

(Embodiment 1) The present invention will be described in detail below based on embodiments. FIG. 5 shows Nch and Pc according to the present invention.
1H is an example of a process sectional view showing a method of forming pads of a thin-film transistor.

Insulating substrate 5 of glass, quartz, sapphire, etc.
01, a base insulating film 502 made of a silicon oxide film or the like
To form a silicon thin film 50 of, for example, polycrystalline silicon.
3 is deposited at about 1500 °. Thereafter, a silicon oxide film 504 is deposited, for example, at 2000 .ANG., And a resist pattern 505 is formed by using a light exposure technique. Next, the silicon oxide film 504 is selectively etched using, for example, an ammonium fluoride solution. (Refer to FIG. 5A.) Next, the resist pattern 505 is removed and, for example,
^Implant about ¹⁵ cm ^-2 ions. (See FIG. 5B.) Thereafter, the silicon oxide film 504 is removed, and a new silicon oxide film 506 is deposited at, for example, 2000.degree. Next, a new resist pattern 507 is formed by using a light exposure technique, and the silicon oxide film 506 is selectively etched with an ammonium fluoride solution or the like using this as a mask. (FIG. 5
(See (c).) Next, the resist pattern 507 is removed, and for example, boron is ion-implanted at about 1 × 10 ¹⁵ cm ⁻² . After that, the silicon oxide film 506 is removed. (FIG. 5
(Refer to (d)) Next, a resist pattern for a pad is formed using a light exposure technique, and the silicon thin film is selectively etched using the resist pattern as a mask, and then the resist pattern is removed to remove Nch and Pch thin film transistors. Pad portions 508 and 509 are completed. (Refer to FIG. 5 (e).) Although the subsequent steps are not particularly described here, the formation of the silicon thin film constituting the channel portion, the deposition of the gate insulating film, the formation of the gate electrode, the Al wiring, etc. are performed according to the usual steps. C
The MOS semiconductor device is completed. (Embodiment 2) Another embodiment of the present invention will be described in detail with reference to the process sectional views of FIGS. FIG. 6 is an example of a process sectional view showing a method of forming pads of Nch and Pch thin film transistors.

Insulating substrate 6 of glass, quartz, sapphire, etc.
01, a base insulating film 602 made of a silicon oxide film or the like.
To form a silicon thin film 60 of, for example, polycrystalline silicon.
3 is deposited on the order of 1500. After this, the silicon oxide film 6
For example, a resist pattern 605 is formed by depositing, for example, 2000 of light-emitting elements 04 using a light exposure technique. Next, the silicon oxide film 604 is selectively etched using, for example, an ammonium fluoride solution. (Refer to FIG. 6A.) Next, the resist pattern 605 is removed and, for example, phosphorus is applied to 1 × 10 ¹⁵ c.
^Implant ions of about m ^-2 . (See FIG. 6 (b))
A new silicon oxide film 606 is deposited, for example, by 2000. Next, a new resist pattern 607 is formed by using a light exposure technique, and the silicon oxide films 604 and 606 are selectively etched with an ammonium fluoride solution or the like using this as a mask. (See FIG. 6 (c))
The pattern 607 is removed and, for example, boron is 1 × 10 ¹⁵ c
^Implant ions of about m ^-2 . Thereafter, the silicon oxide film 60
4, 606 are removed. (See FIG. 6 (d).) Next, a resist pattern for a pad is formed by using a light exposure technique, and the silicon thin film is selectively etched using the resist pattern as a mask. And P
The pad portions 608 and 609 of the channel thin film transistor are completed. (Refer to FIG. 6 (e).) Although the subsequent steps are not particularly described here, formation of a silicon thin film constituting a channel portion, deposition of a gate insulating film, formation of a gate electrode, Al wiring, etc. are performed in accordance with ordinary steps. A CMOS semiconductor device is completed. (Embodiment 3) Another embodiment of the present invention will be described in detail with reference to the process sectional view of FIG. FIG. 7 is an example of a process sectional view showing a method of forming pads of Nch and Pch thin film transistors.
This is a method in which the impurity concentration of the pad portion is increased by changing the impurity concentration of the pad and the other source and drain regions only in the channel thin film transistor.

An insulating substrate 7 made of glass, quartz, sapphire, etc.
01, a base insulating film 702 made of a silicon oxide film or the like.
To form a silicon thin film 70 of, for example, polycrystalline silicon.
3 is deposited on the order of 1500. Thereafter, the silicon oxide film 7
The resist pattern 705 is formed by depositing, for example, 2000 of the photoresist 04 and using a light exposure technique. Next, the silicon oxide film 704 is selectively etched using, for example, an ammonium fluoride solution. (Refer to FIG. 7A.) Next, the resist pattern 705 is removed and, for example, phosphorus is applied to 1 × 10 ¹⁵ c.
^Implant ions of about m ^-2 . (See FIG. 7 (b))
The silicon oxide film 704 is removed using an ammonium fluoride solution or the like as a mask. (See FIG. 7 (c).) Next, a resist pattern for a pad is formed using a light exposure technique,
After selectively etching the silicon thin film using this as a mask, the resist pattern is removed and Nch and Pch are removed.
The pad portions 706 and 707 of the thin film transistor are completed. (Refer to FIG. 6 (d).) Although the subsequent steps are not specifically described here, the formation of the silicon thin film constituting the channel portion, the deposition of the gate insulating film, the formation of the gate electrode, the Al wiring, etc. are performed according to the usual steps. A CMOS semiconductor device is completed. Here, the addition of impurities to the source region and the drain region of the Pch thin film transistor is performed collectively in a self-aligned manner with the gate electrode after the formation of the gate electrode, for example.

In the embodiment of the present invention, for example, a silicon oxide film is used as a mask material at the time of ion implantation of an impurity.
Other mask materials do not depart from the spirit of the present invention. In addition, it does not depart from the gist of the present invention whichever is performed first as the order of adding impurities to the silicon thin film forming the pad. As described above in detail, according to the embodiment of the present invention, even if an ion implantation apparatus without a mass spectrometer is used, the underside of the pad caused by the etching of the underlying silicon oxide film does not occur. Therefore, a thin film transistor excellent in cost can be provided.

[0015]

According to the present invention, scouring under the source / drain regions can be prevented, and an excellent method of manufacturing a CMOS semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an example of the structure of a conventional self-aligned thin film transistor.

FIG. 2 is a sectional view showing an example of the structure of an improved self-aligned thin film transistor.

FIG. 3 is a process cross-sectional view showing one example of a manufacturing method when forming a CMOS using the improved self-aligned thin film transistor.

FIG. 4 shows a CMOS using an ion implanter without a mass analyzer and an improved self-aligned thin film transistor.
FIG. 4 is a process cross-sectional view showing a problem in forming a semiconductor device.

FIG. 5 is a diagram showing a first embodiment showing a pad forming method when forming a CMOS according to the present invention.

FIG. 6 is a view showing another embodiment showing a pad forming method when forming a CMOS according to the present invention.

FIG. 7 is a diagram showing another embodiment showing a pad forming method when forming a CMOS according to the present invention.

[Explanation of symbols]

101, 201, 301, 401, 501, 601, 7
01 substrate 102, 202, 302, 402, 502, 602, 7
02 Base insulating film 103, 104, 203, 204, 303, 304, 3
05, 306, 403, 404, 405, 406, 50
8, 509, 608, 609, 706, 707 pads 407, 504, 506, 604, 606, 704 Silicon oxide films 307, 308, 408, 505, 507, 605, 6
07, 705 Resist pattern 309, 310, 503, 603, 703 Silicon thin film 109, 209, 318, 319 Channel region 105, 205, 311 Gate insulating film 106, 206, 312, 313 Gate electrode 110, 210, 320 Interlayer insulation Films 113, 213, 321 Contact holes 111, 211, 322 Source electrodes 112, 212, 323 Drain electrodes 107, 108, 207, 208, 314, 315, 3
16, 317 Regions of doped silicon thin film forming part of source and drain

Claims (1)

(57) [Claims] In a method of manufacturing a CMOS semiconductor device, a step of forming a base insulating film on an insulating substrate, a step of forming a silicon thin film on the base insulating film, and forming a silicon oxide film on the silicon thin film And selectively removing the silicon oxide film so that the silicon thin film has N
a step of implanting ions serving as donors of a channel thin film transistor; a step of removing the silicon oxide film; a step of forming a new silicon oxide film on the silicon thin film; Selectively removing a portion of the new silicon oxide film, implanting ions serving as an acceptor of a Pch thin film transistor into the silicon thin film, removing the new silicon oxide film, Forming a region into which ions are implanted in an island shape; and forming a semiconductor device using the island-shaped silicon thin film portion as a source / drain region of an Nch or Pch thin film transistor. CMOS
A method for manufacturing a semiconductor device.