JP3141613B2 - Method and circuit for driving voltage-driven element - Google Patents
Method and circuit for driving voltage-driven elementInfo
- Publication number
- JP3141613B2 JP3141613B2 JP05073081A JP7308193A JP3141613B2 JP 3141613 B2 JP3141613 B2 JP 3141613B2 JP 05073081 A JP05073081 A JP 05073081A JP 7308193 A JP7308193 A JP 7308193A JP 3141613 B2 JP3141613 B2 JP 3141613B2
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- Japan
- Prior art keywords
- voltage
- gate
- resistance
- terminal
- circuit
- Prior art date
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、電圧駆動形素子の駆動
方法及びその回路に係り、特にターンオフ及びターンオ
ン時の電圧変化ｄＶ／ｄｔ，電流変化ｄｉ／ｄｔを緩和
してノイズ並びにサージ電圧を抑制する駆動方法及び回
路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a circuit for driving a voltage-driven device, and more particularly to a method for reducing noise and surge voltage by reducing voltage change dV / dt and current change di / dt at turn-off and turn-on. The present invention relates to a driving method and a circuit for suppressing.
【０００２】[0002]
【従来の技術】ＭＯＳゲート構造の電界効果形トランジ
スタ（以後、ＭＯＳＦＥＴと呼ぶ）や絶縁ゲート型バイ
ポーラトランジスタ（以後、ＩＧＢＴと呼ぶ）等の電圧
駆動形素子はターンオン、或いはターンオフ時のスイッ
チング速度が速いことが特徴であり、高周波のインバー
タ装置やスイッチング電源に用いられている。近年、こ
れらの素子は大電流化と高速化の進歩が顕著であるが、
反面、高速スイッチングが原因で、サージ電圧による素
子の破壊やノイズによる他の電子機器への妨害という問
題を招いている。こうした問題の対策として、スイッチ
ング時に制御端子（以後、ゲート端子と呼ぶ）への電圧
の印加或いは除去を緩やかに行いスイッチング速度を緩
和することが検討されている。一例として、特開平1−1
83214 号にはターンオフ速度を緩和する方法が述べられ
ており、第１，第２のオフゲート抵抗手段を設け、第１
のオフゲート抵抗手段は低抵抗を、第２のオフゲート抵
抗手段は高抵抗を有している。上記第１，第２のオフゲ
ート抵抗手段はターンオフの開始と同時に働くが、第１
のオフゲート抵抗手段は予め設定された期間のみ働く。
上記構成によって、ターンオフ直後のストレージ期間
（主電流が下降するまでの期間）は第１，第２のオフゲ
ート抵抗手段で大きなゲート電流を流して高速化し、次
に電圧駆動形素子に流れる主電流が下降するフォール期
間は第２のオフゲート抵抗手段のみを働かせて小さなゲ
ート電流を流し、電流の下降時間を長くして電流の変化
ｄｉ／ｄｔを緩和している。2. Description of the Related Art A voltage-driven device such as a field effect transistor (hereinafter referred to as a MOSFET) having a MOS gate structure or an insulated gate bipolar transistor (hereinafter referred to as an IGBT) has a high switching speed when turned on or turned off. It is used for high frequency inverter devices and switching power supplies. In recent years, these devices have made remarkable progress in increasing current and increasing speed.
On the other hand, high-speed switching causes a problem that a surge voltage causes destruction of an element and noise causes interference with other electronic devices. As a countermeasure against such a problem, studies have been made to moderately apply or remove a voltage to a control terminal (hereinafter, referred to as a gate terminal) during switching to reduce the switching speed. As an example, see JP-A-1-1
No. 83214 describes a method of reducing the turn-off speed, in which first and second off-gate resistance means are provided, and
The off-gate resistance means has a low resistance, and the second off-gate resistance means has a high resistance. The first and second off-gate resistance means work simultaneously with the start of turn-off,
The off-gate resistance means works only for a preset period.
According to the above configuration, the storage period immediately after the turn-off (the period until the main current falls) is accelerated by supplying a large gate current by the first and second off-gate resistance means, and then the main current flowing through the voltage-driven element is reduced. During the falling fall period, a small gate current is caused to flow by operating only the second off-gate resistance means, and the current falling time is lengthened to reduce the current change di / dt.
【０００３】また、ターンオン時のサージ電圧を低減す
る方法の例が特開平3−93457号に述べられている。この
方法は、ターンオン直後はゲート電圧の大きさを時間的
に切り替え、ゲート電圧の印加を制限して電圧駆動形素
子に流れる電流の変化ｄｉ／ｄｔを緩和するものであ
る。本例では、ゲート電圧がツェナーダイオードで決ま
る電圧まで達したら、上記制限を止めてゲート電圧を最
高値まで上昇させる。Further, an example of a method for reducing a surge voltage at the time of turn-on is described in Japanese Patent Application Laid-Open No. 3-93457. In this method, immediately after the turn-on, the magnitude of the gate voltage is temporally switched, and the application of the gate voltage is limited to reduce the change di / dt of the current flowing through the voltage-driven element. In this example, when the gate voltage reaches a voltage determined by the Zener diode, the above restriction is stopped and the gate voltage is raised to the maximum value.
【０００４】[0004]
【発明が解決しようとする課題】上記２例で、前者は第
１のオフゲート抵抗手段の働く期間を抵抗とコンデンサ
で決まる時定数の時間として予め設定しており、後者は
ゲート電圧の印加を制限する期間をツェナーダイオード
とコンデンサ及び抵抗で設定している。しかしながら、
いずれの方法においても電圧駆動形素子は電流容量に依
存してゲート部の静電容量が増加することから、両方法
では駆動すべき電圧駆動形素子の電流容量に応じて、そ
れぞれ最適な抵抗とコンデンサの値に変更する必要があ
る。また、前者の駆動方法を用いると、電流容量が同じ
素子であってもモータ制御のように素子を流れる電流が
時間的に変化する場合には、第１のオフゲート抵抗手段
の働く期間を電流値に応じて変えることが望ましく、１
つの最適値を選ぶことは容易でない。In the above two examples, the former sets the period during which the first off-gate resistance means works as a time constant determined by a resistor and a capacitor, and the latter limits the application of the gate voltage. Is set by a Zener diode, a capacitor and a resistor. However,
In either method, the capacitance of the gate portion of the voltage-driven element increases depending on the current capacity. Therefore, in both methods, the optimum resistance and resistance are adjusted according to the current capacity of the voltage-driven element to be driven. It is necessary to change to the value of the capacitor. In addition, when the former driving method is used, even if the current capacity of the element is the same, the current flowing through the element varies with time as in the case of motor control. It is desirable to change according to
Choosing the two optimal values is not easy.
【０００５】一方、同一の電圧駆動形素子に対してスイ
ッチング時に発生するサージ電圧やノイズの影響は電流
値に依存して大きくなる。また、上記従来例のような方
法でスイッチング時間を遅くすると、スイッチング損失
の増加が問題となる。そこで、フォール、又はライズ期
間のゲート抵抗条件を電流に応じて変えるか、或いは電
流がノイズ等の問題になる電流値以上でのみｄｉ／ｄｔ
を抑制することが望ましい。上記２例はいずれもこうし
た電流値に応じたスイッチング速度の緩和については考
慮していない。On the other hand, the influence of surge voltage and noise generated at the time of switching on the same voltage-driven element increases depending on the current value. Further, if the switching time is delayed by the method as in the above-described conventional example, an increase in switching loss becomes a problem. Therefore, the gate resistance condition during the fall or rise period is changed according to the current, or di / dt is set only when the current is equal to or larger than a current value causing a problem such as noise.
Is desirably suppressed. Neither of the above two examples considers the mitigation of the switching speed according to such a current value.
【０００６】本発明の目的は、上記各問題点を除去する
ものであって、その目的は電圧駆動形素子のゲート容
量、或いは電流値に応じてゲート容量の充放電速度を緩
和しスイッチング時に生じるサージ電圧及びノイズを抑
制することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems, and an object of the present invention is to reduce the charge / discharge speed of the gate capacitance according to the gate capacitance or current value of the voltage-driven element and to cause switching. It is to suppress surge voltage and noise.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
本発明は、主電流の入出力に係る第１，第２端子と絶縁
ゲート構造を有するゲート端子を備えた電圧駆動形素子
の前記第２端子と前記ゲート端子間に、前記第２端子と
前記ゲート端子間に第１のスイッチ手段及び第１の抵抗
手段を介して前記ゲート電圧を除去する回路と、外部制
御電源より第２のスイッチ手段及び第２の抵抗手段を介
してゲート電圧を印加する回路とからなる電圧駆動形素
子の駆動回路において、前記第１，第２端子間の電圧を
検出する電圧検出手段と、前記第１または第２の抵抗手
段の少なくともいずれかは前記電圧検出手段からの電圧
検出信号に基づいて抵抗値を変化させる抵抗可変手段を
備えることにより、前記ゲート電圧を増加或いは減少さ
せる速度を遅くすることを特徴とする。According to the present invention, there is provided a voltage-driven device having first and second terminals for input and output of a main current and a gate terminal having an insulated gate structure. A circuit for removing the gate voltage between the second terminal and the gate terminal between the second terminal and the gate terminal via a first switch means and a first resistance means, and a second switch from an external control power supply And a circuit for applying a gate voltage via a second resistor means, a voltage detecting means for detecting a voltage between the first and second terminals; At least one of the second resistance units includes a resistance variable unit that changes a resistance value based on a voltage detection signal from the voltage detection unit, thereby reducing a speed of increasing or decreasing the gate voltage. It is characterized in.
【０００８】さらに、上記回路において、前記第２端子
と前記ゲート端子間のゲート電圧を検出するゲート電圧
検出手段と、該ゲート電圧検出手段からのゲート電圧検
出信号に基づいて前記第１の抵抗手段における抵抗値を
変化させる抵抗可変手段を備えるか、または、前記主電
流の大きさを検出する電流検出手段と、該電流検出手段
からの電流検出信号に基づいて前記第１の抵抗手段にお
ける抵抗値を変化させる抵抗可変手段を備えたことを特
徴とする。Further, in the above circuit, a gate voltage detecting means for detecting a gate voltage between the second terminal and the gate terminal, and the first resistance means based on a gate voltage detection signal from the gate voltage detecting means. Or a current detection means for detecting the magnitude of the main current, and a resistance value of the first resistance means based on a current detection signal from the current detection means. Characterized in that it is provided with a variable resistance means for changing the resistance.
【０００９】[0009]
【作用】上記によれば、第１，第２端子間の電圧を検出
する手段の出力からターンオン或いはターンオフ時に、
フォール期間の開始或いはライズ期間の終了を判別し、
この期間には抵抗手段を高抵抗化してゲート電圧の減少
或いは増加速度を緩和し、電流の下降或いは上昇に関す
るｄｉ／ｄｔを抑制する。ここで、上記電圧検出手段は
電圧駆動形素子のフォール期間の開始とライズ期間の終
了では、第１，第２端子間の電圧が急激に変化をする特
性を持つことを利用して、ライズ期間の終了とフォール
期間の開始を検出する。According to the above, at the time of turning on or turning off from the output of the means for detecting the voltage between the first and second terminals,
Determine the start of the fall period or the end of the rise period,
During this period, the resistance of the resistance means is increased to reduce the rate of decrease or increase of the gate voltage, and di / dt related to the decrease or increase of the current is suppressed. Here, the voltage detecting means utilizes the characteristic that the voltage between the first and second terminals changes abruptly at the start of the fall period and at the end of the rise period of the voltage-driven element. And the end of the fall period are detected.
【００１０】また、上記構成で高抵抗手段に半導体素子
を使用し、ゲート電圧或いは主電流の一方の値に応じて
上記半導体素子の内部抵抗を変化させる制御信号を出力
する制御信号出力手段を備えることによって、フォール
期間とライズ期間におけるｄｉ／ｄｔの抑制程度を電流
値に応じて調整することが可能である。In the above-mentioned structure, the semiconductor device is used as the high resistance means, and control signal output means for outputting a control signal for changing the internal resistance of the semiconductor element according to one of the gate voltage and the main current is provided. This makes it possible to adjust the degree of di / dt suppression in the fall period and the rise period according to the current value.
【００１１】更に、上記構成でゲート電圧を検出する手
段を備えたことにより、第１，第２端子間の電圧が所定
の値に達した時点においてゲート電圧が予め設定した値
以上の場合には、前記抵抗手段の抵抗値を低抵抗から高
抵抗に切り替えると共に、前記所定の値に達した時点の
前記ゲート電圧が前記予め設定した値未満の場合には、
前記抵抗手段の抵抗値を低抵抗のまま維持することでノ
イズ等の問題になる電流値以上でのみｄｉ／ｄｔを抑制
することができ、スイッチング損失の不要な増加を押さ
えることが出来る。ここで、上記ゲート電圧の検出によ
る電流値の判断は、電圧駆動形素子のゲート電圧と飽和
電流値の関係を利用している。即ち、第１，第２端子間
の電圧検出手段から素子が飽和領域に入ったことを、ま
た、ゲート電圧の検出手段からゲート電圧が所望する電
流値に対する設定値（言い換えれば、ゲート電圧が前記
予め設定した値における飽和電流は検出すべき電流値に
相当する）であるかを検出し、両電圧検出手段の結果か
ら電流が検出すべき値以上であるかどうかを識別する。In the above-mentioned structure, a means for detecting a gate voltage is provided, so that when the voltage between the first and second terminals reaches a predetermined value, the gate voltage is higher than a predetermined value. Switching the resistance value of the resistance means from low resistance to high resistance, and when the gate voltage at the time when the predetermined value is reached is less than the preset value,
By maintaining the resistance value of the resistance means as a low resistance, di / dt can be suppressed only at a current value or more that causes a problem such as noise, and an unnecessary increase in switching loss can be suppressed. Here, the determination of the current value by detecting the gate voltage utilizes the relationship between the gate voltage of the voltage-driven element and the saturation current value. That is, the fact that the element has entered the saturation region from the voltage detection means between the first and second terminals, and the setting value for the desired current value of the gate voltage from the gate voltage detection means (in other words, the gate voltage (The saturation current at a preset value corresponds to the current value to be detected), and whether the current is equal to or greater than the value to be detected is identified from the results of the two voltage detection means.
【００１２】[0012]
【実施例】以下、本発明の実施例を図面を用いて説明す
る。図１は、本発明の第１の実施例を示す電圧駆動形素
子の駆動回路の基本ブロック図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a basic block diagram of a drive circuit of a voltage drive type device according to a first embodiment of the present invention.
【００１３】図１において、Ｑ１は電圧駆動形素子のＩ
ＧＢＴであり、電流を入力するコレクタ端子（記号
ｃ），電流を出力するエミッタ端子（ｅ）、及び制御電
圧を印加するゲート端子（ｇ）を備える。Ｑ１は負荷２
を介して主電源ＶＥと閉回路を構成する。本実施例では
負荷２は誘導性であるものと仮定し、負荷には逆並列に
フリーホイールダイオードＤを設けている。ここで、イ
ンダクタンスＬｅは負荷２とＱ１を接続する配線のイン
ダクタンス成分を表したものである。次にＳＷ１，ＳＷ
２はそれぞれスイッチ手段であり制御回路１からの入力
信号Ｓｏｆｆ、及びＳｏｎによってオン，オフ動作させ
る。ここで、本実施例ではＳｏｆｆ、及びＳｏｎはいず
れも図に示す制御回路１の出力信号Ｓで共通であり、ハ
イレベル（Ｈ）或いはローレベル（Ｌ）の二値化された
信号とする。Ｑ１のゲート端子とＳＷ１の間に接続した
３は第１の抵抗手段であり、Ｑ１のゲート端子間とＳＷ
２の間に接続した４は第２の抵抗手段である。In FIG. 1, Q1 is the voltage-driven element I
The GBT includes a collector terminal (symbol c) for inputting a current, an emitter terminal (e) for outputting a current, and a gate terminal (g) for applying a control voltage. Q1 is load 2
To form a closed circuit with the main power supply VE. In this embodiment, it is assumed that the load 2 is inductive, and the load is provided with a freewheel diode D in antiparallel. Here, the inductance Le represents the inductance component of the wiring connecting the load 2 and Q1. Next, SW1, SW
Reference numerals 2 denote switch means, which are turned on and off by input signals Soff and Son from the control circuit 1, respectively. Here, in the present embodiment, both Soff and Son are common to the output signal S of the control circuit 1 shown in the figure, and are binarized signals of high level (H) or low level (L). 3 connected between the gate terminal of Q1 and SW1 is first resistance means, and is connected between the gate terminal of Q1 and SW1.
4 connected between 2 is a second resistance means.
【００１４】制御回路１からＳＷ１に入力信号Ｓｏｆｆ
が供与されると、ＳＷ１はオンし第１の抵抗手段３を介
してＱ１のゲート端子とエミッタ端子間のゲート容量Ｃ
ｇｅに充電された電荷を放電し、Ｑ１をターンオフす
る。また、制御回路１からSW2に入力信号Ｓｏｎが供与
されると、ＳＷ２はオンし第２の抵抗手段４を介して制
御電源Ｖｃｃからゲート容量Ｃｇｅに電荷を充電し、Ｑ
１をターンオンする。ここで、第１，第２の抵抗手段３
及び４はそれぞれ、Ｑ１のコレクタ端子とエミッタ端子
間の電圧（以下コレクタ電圧と呼ぶ）を検出する電圧検
出手段５の出力に応じて抵抗値を変化させる。即ち、コ
レクタ電圧が所定の値未満では、第１，第２の抵抗手段
３及び４の抵抗値は低抵抗，コレクタ電圧が所定の値以
上では、第１，第２の抵抗手段３及び４の抵抗値は高抵
抗に変化させるものとする。この結果、上記Ｑ１のター
ンオフ，ターンオンの期間中にコレクタ電圧が変化する
ことによって第１，第２の抵抗手段３及び４の抵抗値が
変化し、ゲート容量Ｃｇｅから電荷を放電、或いは充電
する速度が変化する。ターンオフ時においてはコレクタ
電圧は増加することから、第１の抵抗手段が低抵抗から
高抵抗に変化しＣｇｅからの電荷の放電は遅くなる。一
方、ターンオン時においてはコレクタ電圧は減少するこ
とから、第２の抵抗手段が高抵抗から低抵抗に変化しＣ
ｇｅへの電荷の充電は、始めは遅く、コレクタ電圧が所
定値以上の期間からは速くなる。An input signal Soff is sent from the control circuit 1 to SW1.
Is supplied, SW1 turns on and the gate capacitance C1 between the gate terminal and the emitter terminal of Q1 via the first resistance means 3.
Discharge the electric charge charged in the ge, and turn off Q1. Further, when the input signal Son is supplied from the control circuit 1 to SW2, SW2 is turned on and charges the gate capacitance Cge from the control power supply Vcc through the second resistance means 4 to charge Q2.
Turn 1 on. Here, the first and second resistance means 3
And 4 change the resistance value according to the output of the voltage detecting means 5 for detecting the voltage between the collector terminal and the emitter terminal of Q1 (hereinafter referred to as the collector voltage). That is, when the collector voltage is lower than the predetermined value, the resistance values of the first and second resistance means 3 and 4 are low resistance. When the collector voltage is higher than the predetermined value, the resistance value of the first and second resistance means 3 and 4 is low. The resistance value is changed to a high resistance. As a result, when the collector voltage changes during the turn-off and turn-on periods of Q1, the resistance values of the first and second resistance means 3 and 4 change, and the speed at which charges are discharged or charged from the gate capacitance Cge. Changes. At the time of turn-off, the collector voltage increases, so that the first resistance means changes from low resistance to high resistance, and the discharge of charges from Cge is delayed. On the other hand, at turn-on, since the collector voltage decreases, the second resistance means changes from high resistance to low resistance and C
The charge of the charge to the ge is slow at the beginning, and becomes faster from the period when the collector voltage is equal to or higher than the predetermined value.
【００１５】次に、本実施例に関する具体的な回路構成
の一例を図２に示す。図２で破線で囲んだ領域３，４，
５はそれぞれ、図１に示した第１の抵抗手段３，第２の
抵抗手段４、及び電圧検出手段５に関する具体的な回路
構成の一例を示している。第１の抵抗手段３としては、
ＳＷ１とＱ１のエミッタ端子の間にＰチャンネルＭＯＳ
ＦＥＴ Ｍ１を備え、Ｍ１に対して並列に抵抗Ｒ１を備
える。第２の抵抗手段４としては、制御電源Ｖｃｃの正
極とＳＷ２の間にＰチャンネルMOSFET M2を備え、Ｍ２
に対して並列に抵抗Ｒ２を備える。ここで、Ｍ１，Ｍ２
は電圧検出手段５の出力に応じて内部抵抗が変化するこ
とから可変抵抗手段として用いている。また、Ｒ１の抵
抗値はＭ１のオン時の内部抵抗に比べて十分大きく、同
様にＲ２の抵抗値はＭ２のオン時の内部抵抗に比べて十
分大きいものを選ぶ。尚、本実施例ではスイッチ手段Ｓ
Ｗ１，ＳＷ２としてｐｎｐ、及びｎｐｎのバイポーラト
ランジスタを用いているが、これらのスイッチ素子はＭ
ＯＳＦＥＴでも良い。同様にＭ１，Ｍ２にはＭＯＳＦＥ
Ｔを用いているがこれらはバイポーラトランジスタを用
いても良い。次に、コレクタ電圧Ｖｃを検出する電圧検
出手段５としては、制御電源Ｖｃｃの正極と負極間に直
列に接続した抵抗Ｒ５とＲ６を備え、Ｒ５とＲ６の接続
部（以後、Ａ点と呼ぶ）にアノード端子を、また、Ｑ１
のコレクタ端子にカソード端子をそれぞれ接続したダイ
オードＤ１を備える。スイッチ手段ＳＷ１，ＳＷ２を入
力信号Ｓに応じてオン，オフする手段として抵抗Ｒ３，
Ｒ４及びｎｐｎトランジスタＱ２を備えており、Ｓがロ
ーレベルの場合にはＱ２がオフして、Ｒ３とＲ４の接続
部の電圧は上昇し、ＳＷ２はベース電流を供給されてオ
ン，ＳＷ１はベースが逆バイアスされてオフ状態とな
る。逆に、Ｓがハイレベルの場合にはＱ２がオンして、
Ｒ３とＲ４の接続部の電圧は減少し、ＳＷ２はベースが
逆バイアスされてオフ，ＳＷ１はベース電流を供給され
てオン状態となる。Next, FIG. 2 shows an example of a specific circuit configuration relating to the present embodiment. Regions 3, 4, surrounded by broken lines in FIG.
Reference numeral 5 denotes an example of a specific circuit configuration relating to the first resistance means 3, the second resistance means 4, and the voltage detection means 5 shown in FIG. As the first resistance means 3,
P channel MOS between the emitter terminal of SW1 and Q1
An FET M1 is provided, and a resistor R1 is provided in parallel with M1. As the second resistance means 4, a P-channel MOSFET M2 is provided between the positive electrode of the control power supply Vcc and SW2.
, A resistor R2 is provided in parallel. Here, M1, M2
Are used as variable resistance means because the internal resistance changes according to the output of the voltage detection means 5. Further, the resistance value of R1 is selected to be sufficiently larger than the internal resistance of M1 when it is turned on, and similarly, the resistance value of R2 is selected to be sufficiently larger than the internal resistance of M2 when it is turned on. In this embodiment, the switch means S
Although pnp and npn bipolar transistors are used as W1 and SW2, these switch elements are M
OSFET may be used. Similarly, MFE and M2 have MOSFE
Although T is used, bipolar transistors may be used. Next, the voltage detecting means 5 for detecting the collector voltage Vc includes resistors R5 and R6 connected in series between the positive electrode and the negative electrode of the control power supply Vcc, and a connection portion between R5 and R6 (hereinafter referred to as a point A). To the anode terminal and Q1
And a diode D1 in which the cathode terminal is connected to the collector terminal. As means for turning on and off the switch means SW1 and SW2 according to the input signal S, a resistor R3
R4 and an npn transistor Q2 are provided. When S is at a low level, Q2 turns off, the voltage at the connection between R3 and R4 rises, SW2 is supplied with a base current, and SW1 is turned on. It is reverse biased and turned off. Conversely, when S is at a high level, Q2 turns on,
The voltage at the connection between R3 and R4 decreases, the base of SW2 is reverse-biased and turned off, and the base of SW1 is supplied with a base current and turned on.
【００１６】次に、電圧検出手段５で検出する電圧レベ
ル（前述した所定の電圧）について説明する。まず、電
圧検出手段５でＡ点の電圧は、Ｑ１がオン状態にある場
合にはそのオン電圧にＤ１の順方向電圧降下を加えた値
に等しく約３Ｖ程度であり、信号の基準電位をＶｃｃの
負極を基準電位とすると、論理信号としてはローレベル
（Ｌ）に相当する。次に、スイッチングの過渡時でＱ１
の電圧がＶｃｃより高くなると、Ｄ１が逆バイアスされ
オフ状態になるため、Ａ点の電圧はＲ５とＲ６の分圧比
で決まる値となり、Ｒ５に対してＲ６の抵抗値を十分大
きい値に選ぶと、ほぼＶｃｃに等しい電圧となる（論理
信号としてはハイレベルに相当しＨで表す）。この時の
コレクタ電圧の値は上述のようにＶｃｃにほぼ等しい
が、この値をＶｃ１と定義する。Ｖｃ１はコレクタとゲ
ート間の静電容量Ｃｃｇが電圧依存性のため急激に変化
（ＶｃがＶｃ１以上ではＣｃｇは急減する）する際の電
圧にほぼ等しい。また、Ｃｃｇが急激に変化する時刻は
ライズ期間の終了、或いはフォール期間の開始に相当す
る。即ち、電圧検出手段５はＱ１のコレクタ電圧がＶｃ
１以上かどうかを検出し、Ａ点の電圧を出力としてＬ又
はＨの二値化した出力を発生する機能を有する。Next, the voltage level (predetermined voltage described above) detected by the voltage detecting means 5 will be described. First, the voltage at the point A in the voltage detecting means 5 is about 3 V, which is equal to the value obtained by adding the forward voltage drop of D1 to the ON voltage when Q1 is in the ON state, and the reference potential of the signal is Vcc. When the negative electrode of is used as a reference potential, the logic signal corresponds to a low level (L). Next, during the transition of switching, Q1
Is higher than Vcc, D1 is reverse-biased and turned off. Therefore, the voltage at point A becomes a value determined by the voltage dividing ratio of R5 and R6, and if the resistance value of R6 is selected to be a sufficiently large value with respect to R5. , A voltage substantially equal to Vcc (corresponding to a high level as a logic signal and represented by H). The value of the collector voltage at this time is substantially equal to Vcc as described above, and this value is defined as Vc1. Vc1 is substantially equal to the voltage at which the capacitance Ccg between the collector and the gate rapidly changes due to the voltage dependency (Ccg rapidly decreases when Vc is equal to or higher than Vc1). The time at which Ccg changes abruptly corresponds to the end of the rise period or the start of the fall period. That is, the voltage detecting means 5 determines that the collector voltage of Q1 is Vc
It has a function of detecting whether it is 1 or more and generating a binary output of L or H using the voltage at point A as an output.
【００１７】上記構成による駆動回路で、本発明の狙い
であるターンオフ及びターンオン時におけるｄＶ／ｄ
ｔ，ｄｉ／ｄｔ及びサージ電圧の抑制の動作を次の図３
を用いて述べる。In the drive circuit having the above configuration, dV / d at the time of turn-off and turn-on, which is the object of the present invention,
The operation of suppressing t, di / dt and surge voltage is shown in FIG.
It is described using.
【００１８】図３は、図２に示した駆動回路の動作説明
図である。同図（ａ）はターンオン時、同図（ｂ）はタ
ーンオフ時の動作をそれぞれ表している。同図（ａ)，
(ｂ）はいずれも駆動信号Ｓ，第２或いは第１の抵抗手
段の抵抗値，Ｑ１のゲート電圧Ｖｇ，Ｑ１のコレクタ電
圧Ｖｃ，Ｑ１のコレクタとゲート間の静電容量Ｃｃｇ、
及びＱ１を流れるコレクタ電流Ｉｃに関して時間的な変
化を示している。FIG. 3 is an explanatory diagram of the operation of the drive circuit shown in FIG. FIG. 10A shows the operation at the time of turn-on, and FIG. 10B shows the operation at the time of turn-off. FIG.
(b) shows the drive signal S, the resistance value of the second or first resistance means, the gate voltage Vg of Q1, the collector voltage Vc of Q1, the capacitance Ccg between the collector and gate of Q1,
5 shows a temporal change with respect to the collector current Ic flowing through Q1.
【００１９】図３(ａ)のターンオン時には、駆動信号Ｓ
がローレベルになると図２のＳＷ２がオンする。ここ
で、Ｓが印加された直後にはＶｃの値は前述のＣｃｇが
急減する際の電圧（Ｖｃ１）に比べて十分大きく、Ａ点
の電圧はハイレベル（Ｈ）である。そこで、Ｍ２はオフ
状態であり、第２の抵抗手段の抵抗値はＲ２の値とな
り、ゲート電圧はゲート容量ＣｇｅとＲ２の積で決まる
時定数でゆっくりと増加する。また、コレクタ電流Ｉｃ
は上記ゲート電圧に対する飽和電流が流れ、Ｖｇの増加
に依存して上昇する。このため、コレクタ電流の時間的
変化ｄｉ／ｄｔは上記時定数に応じたゆっくりしたもの
になり、コレクタ電圧がＶｃ１に達するまでの期間ｔ1
では電流上昇の時間変化ｄｉ／ｄｔを抑制することがで
きる。Ｉｃが負荷電流の定常値（Ｉｃ１）に達すると、
それまで飽和の状態にあったＱ１が非飽和の状態に移行
する。この結果、コレクタ電圧Ｖｃが減少してＶｃ１の
レベルに達する。ＶｃがＶｃ１未満になると電圧検出手
段５の働きでＡ点の電圧がハイレベルからローレベル
（Ｌ）に変化する。また、同時にＣｃｇはＶｃに対する
電圧依存性によって急激に増加する。Ａ点の電圧がＬに
変化した以降の期間（ｔ2と定義する）ではＭ２がオン
する。この結果、第２の抵抗手段の抵抗値はＲ２の高抵
抗からＭ２のオン抵抗（Ｒｏｎ（Ｍ２）と表す）の低抵
抗に変わり、Ｃｃｇに蓄積された電荷の放電は急速に行
われる。また、ゲート電圧も急速に増加する。At the time of turn-on shown in FIG.
Becomes low level, SW2 in FIG. 2 is turned on. Here, immediately after S is applied, the value of Vc is sufficiently higher than the voltage (Vc1) when Ccg suddenly decreases, and the voltage at point A is at the high level (H). Then, M2 is in the off state, the resistance value of the second resistance means becomes the value of R2, and the gate voltage slowly increases with a time constant determined by the product of the gate capacitance Cge and R2. Also, the collector current Ic
, A saturation current with respect to the gate voltage flows, and increases with an increase in Vg. For this reason, the temporal change di / dt of the collector current becomes slow according to the time constant, and the period t 1 until the collector voltage reaches Vc1.
Thus, the time change di / dt of the current rise can be suppressed. When Ic reaches the steady-state value (Ic1) of the load current,
Q1 which has been in a saturated state until then shifts to a non-saturated state. As a result, the collector voltage Vc decreases and reaches the level of Vc1. When Vc becomes lower than Vc1, the voltage at point A changes from a high level to a low level (L) by the operation of the voltage detection means 5. At the same time, Ccg sharply increases due to voltage dependency on Vc. In the period after which the voltage at point A is changed to L (defined as t 2) M2 is turned on. As a result, the resistance value of the second resistance means changes from the high resistance of R2 to the low resistance of the on resistance of M2 (referred to as Ron (M2)), and the charge stored in Ccg is rapidly discharged. Also, the gate voltage increases rapidly.
【００２０】次に、図３（ｂ）のターンオフ時の動作に
ついて述べる。駆動信号ＳがハイレベルになるとＳＷ２
はオフし、変わってＳＷ１がオンする。Ｓのハイレベル
が印加された直後にはＶｃの値はＶｃ１に比べて十分小
さく、Ａ点の電圧はＬである。そこでＶｃがＶｃ１以下
の期間ｔ3 においてはＭ１がオンし、第１の抵抗手段の
抵抗値はＭ１のオン抵抗（Ｒｏｎ（Ｍ１）と表す）の低
抵抗であることから、Ｃｇｅに蓄積された電荷の放電は
急速に行われる。Ｖｇの減少が進むとやがてＱ１は非飽
和から飽和へと移行する。この過程においてＶｃが増加
し、Ｖｃ１に達するとＡ点の電圧がＨレベルに変化す
る。この結果Ｍ１はオフし、第１の抵抗手段の抵抗値は
低抵抗Ｒｏｎ（Ｍ１）からＲ１の高抵抗に変わり、ゲー
ト電圧はゲート容量ＣｇｅとＲ１で決まる時定数でゆっ
くりと減少する。ＶｃがＶｃ１以上の期間ｔ4 において
はＱ１は飽和動作に入り、コレクタ電圧が増加すること
によって飽和電流を流し、定常時の負荷電流を維持す
る。コレクタ電圧が増加する期間ではゲート電圧の減少
を抑制しても、コレクタ電圧がＶｃ１から主電源電圧Ｖ
Ｅに達するまでの電圧変化ｄＶ／ｄｔを緩和する効果は
少ない。ｄＶ／ｄｔを抑制するのはむしろコレクタ電圧
がＶＥに達した以後の期間である。コレクタ電圧がＶＥ
に達すると、もはやコレクタ電流Ｉｃを維持することは
できず、Ｉｃは減少過程にあるＶｇの飽和電流として徐
々に減少する。その時間的変化ｄｉ／ｄｔはＣｇｅとＲ
１の積の時定数に応じたゆっくりしたものになる。この
時、Ｑ１のコレクタ電圧としては主電源電圧ＶＥに加え
て配線インダクタンスＬｅと上記ｄｉ／ｄｔの積で決ま
るサージ電圧が重畳されるが、ゲート電圧の減少を緩和
していることによりｄｉ／ｄｔは小さく押さえることが
でき、サージ電圧（同図（ｂ）中のＶｓｐ）もわずかに
なる。従来の駆動回路ではターンオフの過程において電
流下降期間中のｄＶ／ｄｔが最も大きいが、本実施例に
よればｄｉ／ｄｔの緩和によりｄＶ／ｄｔも抑制するこ
とが出来る。Next, the operation at the time of turn-off in FIG. 3B will be described. When the drive signal S becomes high level, SW2
Turns off and SW1 turns on. Immediately after the high level of S is applied, the value of Vc is sufficiently smaller than Vc1, and the voltage at point A is L. Therefore Vc is M1 is turned on during the period t 3 of Vc1 below, the resistance value of the first resistor means because it is low resistance in the on-resistance of M1 (denoted Ron (M1)), stored in Cge The discharge of the charge occurs rapidly. As Vg decreases, Q1 shifts from non-saturation to saturation. In this process, Vc increases, and when it reaches Vc1, the voltage at point A changes to H level. As a result, M1 is turned off, the resistance value of the first resistance means changes from the low resistance Ron (M1) to the high resistance of R1, and the gate voltage decreases slowly with a time constant determined by the gate capacitance Cge and R1. Vc in Q1 the period t 4 of Vc1 or enters the saturation operation, passing a saturation current by the collector voltage increases to maintain the load current at steady state. During the period when the collector voltage increases, the collector voltage is reduced from Vc1 to the main power supply voltage V
The effect of relaxing the voltage change dV / dt until the voltage reaches E is small. Rather, dV / dt is suppressed during the period after the collector voltage reaches VE. Collector voltage is VE
, The collector current Ic can no longer be maintained, and Ic gradually decreases as the saturation current of Vg in the course of reduction. The time change di / dt is Cge and R
It becomes slow according to the time constant of the product of one. At this time, in addition to the main power supply voltage VE, a surge voltage determined by the product of the wiring inductance Le and the above-mentioned di / dt is superimposed on the collector voltage of Q1, but di / dt is reduced because the decrease in the gate voltage is reduced. Can be kept small, and the surge voltage (Vsp in FIG. 4B) becomes small. In the conventional drive circuit, dV / dt during the current fall period is the largest during the turn-off process. However, according to the present embodiment, dV / dt can be suppressed by relaxing di / dt.
【００２１】以上のように本駆動回路によれば、ターン
オフ過程で電流下降時のｄｉ／ｄｔ，ｄＶ／ｄｔを抑制
できるほか、配線インダクタンスの影響で生じるサージ
電圧も軽減する効果がある。As described above, according to the present drive circuit, di / dt and dV / dt at the time of a current drop during the turn-off process can be suppressed, and the surge voltage caused by the influence of the wiring inductance can be reduced.
【００２２】尚、上記図２の実施例においては高抵抗Ｒ
１を固定値としたが、この値を可変抵抗化する方法も有
効である。即ち、ｄｉ／ｄｔはＣｇｅとＲ１の積の時定
数に応じた変化を示すことから、電流Ｉｃが大きい場合
にはＲ１の抵抗値をより大きくすることで、電流値に応
じたｄｉ／ｄｔの抑制を行うことが出来る。In the embodiment shown in FIG. 2, the high resistance R
Although 1 is a fixed value, a method of changing this value to a variable resistance is also effective. That is, since di / dt indicates a change in accordance with the time constant of the product of Cge and R1, when the current Ic is large, the resistance value of R1 is increased to increase the value of di / dt according to the current value. Suppression can be performed.
【００２３】図４は、本発明の他の実施例を示す駆動回
路の基本ブロック図である。ここで、図４においては、
前述の図１と同じ構成要素には同一の記号を付してお
り、説明は省略する。同図で６はゲート電圧の検出手段
であり、この出力に応じて第１の抵抗手段における高抵
抗を可変抵抗化する。図４の実施例の具体的な回路例を
図５に示す。図５で図２の回路と構成が異なるのは第１
の抵抗手段３とゲート電圧検出手段６であり、他の部分
は図２と同じであることから説明は省略する。図５で第
１の抵抗手段は図２のＭ１及びＲ１に並列にＮチャンネ
ルＭＯＳＦＥＴＭ３を備えている。また、ゲート電圧検
出手段６はＶｃｃの正極と負極間にＰチャンネルＭＯＳ
ＦＥＴ Ｍ４と抵抗Ｒ７の直列接続を備え、Ｍ４のソー
ス端子とゲート端子間には抵抗Ｒ８をまたＭ４のゲート
端子とＱ１のゲート端子間にツェナーダイオードＺＤを
備える。そして、Ｍ４とＲ７の接続部から出力Ｂを取り
出し、この信号をＭ３の制御信号として供与する。上記
構成のゲート電圧検出手段６はＱ１のゲート電圧が減少
し、Ｖｃｃの正極とＱ１のゲート端子間の電圧がＺＤの
降服電圧以上になると、Ｍ４のゲートにバイアス電圧が
与えられ、Ｍ４はオンする。また、Ｍ４のオンによって
出力Ｂの電圧値は，Ｖｃｃの電圧をＭ４のオン抵抗とＲ
７で分圧した値となり、この電圧がＭ３のしきい値電圧
より大きければＭ３もオン状態となる。以後、Ｑ１のゲ
ート電圧の減少に依存してＭ４，Ｍ３のゲートバイアス
電圧は増加して行く。このため、Ｍ３のオン抵抗は時間
的に減少する。ここで、図３（ｂ）に示したように、Ｖ
ｃがＶｃ１の値に達した時点(ｔ3とｔ4の境界)における
ゲート電圧は、以下に述べるように平坦化しており、そ
の値は定常時の電流Ｉｃ１に依存して大きくなる。図３
（ｂ）図において、ｔ3 期間では前述のようにＶｇの減
少が進み、Ｑ１は非飽和から飽和へと移行する。この過
程においてＶｃは増加し、第１の抵抗手段とＳＷ１はＱ
１のゲート容量の放電電流と同時にＣｃｇの充電電流を
流すが、Ｖｃが増加を始めるとＣｃｇが大きいためゲー
ト電流はほとんどがＣｃｇの充電電流に充てられる。こ
のため、Ｖｇの減少は一旦休止し電圧が平坦になる期間
が生じる。FIG. 4 is a basic block diagram of a drive circuit showing another embodiment of the present invention. Here, in FIG.
The same components as those in FIG. 1 described above are denoted by the same reference numerals, and description thereof will be omitted. In the figure, reference numeral 6 denotes a gate voltage detecting means for changing the high resistance of the first resistance means into a variable resistance according to the output. FIG. 5 shows a specific circuit example of the embodiment of FIG. 5 is different from the circuit of FIG.
The other parts are the same as those in FIG. 2 and the description is omitted. In FIG. 5, the first resistance means includes an N-channel MOSFET M3 in parallel with M1 and R1 in FIG. The gate voltage detecting means 6 is a P-channel MOS between a positive electrode and a negative electrode of Vcc.
It comprises a series connection of an FET M4 and a resistor R7, a resistor R8 between the source terminal and the gate terminal of M4, and a Zener diode ZD between the gate terminal of M4 and the gate terminal of Q1. Then, the output B is taken out from the connection between M4 and R7, and this signal is provided as a control signal for M3. When the gate voltage of Q1 decreases and the voltage between the positive electrode of Vcc and the gate terminal of Q1 becomes equal to or higher than the breakdown voltage of ZD, the bias voltage is applied to the gate of M4, and M4 is turned on. I do. Further, when M4 is turned on, the voltage value of the output B is changed from the voltage of Vcc to the on resistance of M4 and R.
When the voltage is higher than the threshold voltage of M3, M3 is also turned on. Thereafter, the gate bias voltages of M4 and M3 increase depending on the decrease of the gate voltage of Q1. Therefore, the on-resistance of M3 decreases with time. Here, as shown in FIG.
The gate voltage at the time c has reached the value of Vc1 (boundary t 3 and t 4) is flattened as described below, its value increases depending on a current Ic1 in the steady state. FIG.
(B) In the figure, during period t 3 , Vg decreases as described above, and Q1 shifts from non-saturation to saturation. In this process, Vc increases, and the first resistance means and SW1 become Q
The charge current of Ccg flows at the same time as the discharge current of the gate capacitance of 1. However, when Vc starts to increase, Ccg is large, and most of the gate current is used for the charge current of Ccg. For this reason, the period in which the decrease of Vg temporarily stops and the voltage becomes flat occurs.
【００２４】次に、平坦化した際のゲート電圧とＱ１の
電流値の関係について説明する。図６（ａ）はゲート電
圧をパラメータとした場合のＱ１のコレクタ電圧Ｖｃと
コレクタ電流Ｉｃの関係であり、この図でコレクタ電圧
Ｖｃ１の状態を飽和領域とすれば、印加したゲート電圧
（Ｖｇ１〜Ｖｇ４）に対してコレクタ電流はＩｃ１〜Ｉ
ｃ４の飽和電流として一義的に決まる。Ｑ１がオン時の
電流がＩｃ２の場合を例とすると、ｔ3 の期間では図６
（ａ）の１〜３に示すようにＱ１の動作点が変化してコ
レクタ電圧が増加する。この結果、電圧が平坦化する際
の値はＩｃ２を飽和電流とするゲート電圧Ｖｇ２にな
る。図６（ａ）からコレクタ電流の飽和値とゲート電圧
の関係を表した図が（ｂ）であり、電流値に依存して平
坦化する際のゲート電圧も大きくなることを示す。図５
の構成に用いたツェナーダイオードの降服電圧をＶｚと
すると、ｔ4 の期間開始時におけるＭ３のオン抵抗は、
電流値が大きいほど上記平坦化したゲート電圧が高く、
Ｍ４及びＭ３に印加されるゲートバイアス電圧は小さ
い。このためにＭ３のオン抵抗は高くなる。次に、Ｍ３
のオン抵抗が高いほど、Ｍ３のオン抵抗とＣｇｅとで決
まる時定数が長くなり、Ｖｇの時間的な減少も遅くな
る。そして、Ｖｇの減少が遅いほどＭ３のオン抵抗の減
少も遅くなり、ｄｉ／ｄｔもこれに依存して抑制され
る。図５の実施例によるターンオフ時のゲート電圧，コ
レクタ電流及びコレクタ電流の特性を図７に示す。この
図で、コレクタ電流が大きいほどｔ4 の期間におけるゲ
ート電圧の減少が緩和することを示している。Next, the relationship between the gate voltage when flattened and the current value of Q1 will be described. FIG. 6A shows the relationship between the collector voltage Vc of Q1 and the collector current Ic when the gate voltage is used as a parameter. In this figure, if the state of the collector voltage Vc1 is a saturation region, the applied gate voltages (Vg1 to Vg1) Vg4), the collector currents are Ic1 to Ic1.
It is uniquely determined as the saturation current of c4. When Q1 current during ON as an example the case of Ic2, figures in period t 3 6
As shown in (a) to (c), the operating point of Q1 changes and the collector voltage increases. As a result, the value when the voltage is flattened is the gate voltage Vg2 having Ic2 as the saturation current. FIG. 6B shows the relationship between the saturation value of the collector current and the gate voltage from FIG. 6A, and shows that the gate voltage at the time of flattening increases depending on the current value. FIG.
Assuming that the breakdown voltage of the Zener diode used in the above configuration is Vz, the on-resistance of M3 at the start of the period of t 4 is
The larger the current value is, the higher the flattened gate voltage is,
The gate bias voltage applied to M4 and M3 is small. Therefore, the ON resistance of M3 increases. Next, M3
, The time constant determined by the on-resistance of M3 and Cge becomes longer, and the temporal decrease of Vg also becomes slower. The slower the decrease in Vg, the slower the decrease in the on-resistance of M3, and the lower the di / dt. FIG. 7 shows the characteristics of the gate voltage, the collector current and the collector current at the time of turn-off according to the embodiment of FIG. This figure shows that the larger the collector current is, the more the reduction of the gate voltage during the period of t 4 is eased.
【００２５】図５の実施例では電流に応じてＭ３の抵抗
を変化させる手段としてゲート電圧検出６を用いたが、
この機能に関する他の実施例を図８に示す。図８で破線
で囲む領域７は電流を直接検出してＭ３のゲートバイア
ス電圧を変化させる手段であり、電流検出手段と呼ぶこ
とにする。尚、領域７以外は図５と同じであり、説明は
省略する。電流検出手段７はＱ１に電流検出端子を備え
た素子を用い、電流検出端子に流れる電流をＱ３とＱ４
からなるカレントミラー手段で取り出し、Ｑ１のエミッ
タ端子を流れる主電流に応じて変化する微小電流をＱ４
とこれに直列に接続した抵抗Ｒ１０に流す。尚、Ｑ４に
は並列に抵抗Ｒ９を接続し、Ｑ４がオフ時にはＲ９とＲ
１０の比で出力Ｂの電圧が決まるようにしている。上記
構成によると、主電流が大きいほどＲ１０両端の電圧降
下が大きくなり、出力Ｂの電圧（即ち、Ｍ３のゲートバ
イアス電圧）は低下するためＭ３のオン抵抗は高くな
る。このため、図５のゲート電圧検出手段と同様に、電
流に応じたｄｉ／ｄｔの抑制が行える。In the embodiment of FIG. 5, the gate voltage detector 6 is used as means for changing the resistance of M3 according to the current.
FIG. 8 shows another embodiment relating to this function. A region 7 surrounded by a broken line in FIG. 8 is a unit for directly detecting a current to change the gate bias voltage of M3, and will be referred to as a current detection unit. Except for the area 7, the configuration is the same as that of FIG. The current detecting means 7 uses an element having a current detecting terminal for Q1, and detects the current flowing through the current detecting terminal as Q3 and Q4.
And a minute current that changes according to the main current flowing through the emitter terminal of Q1 is extracted by Q4.
And a resistor R10 connected in series to this. A resistor R9 is connected in parallel to Q4, and when Q4 is off, R9 and R9 are connected.
The output B voltage is determined by the ratio of 10. According to the above configuration, as the main current increases, the voltage drop across R10 increases, and the voltage of the output B (ie, the gate bias voltage of M3) decreases, so that the on-resistance of M3 increases. Therefore, similarly to the gate voltage detecting means of FIG. 5, di / dt can be suppressed in accordance with the current.
【００２６】次に、電流値に応じたｄｉ／ｄｔ抑制の選
択機能を備えた実施例について図９を用いて説明する。
図９でｄｉ／ｄｔ抑制の選択手段８を除くと、残りの構
成は図２或いは図５と同じであり説明は省略する。但
し、本実施例ではターンオフ時のｄｉ／ｄｔ抑制につい
てのみ説明するため、第２の抵抗手段４は抵抗Ｒ２で一
定とした。また、図２に示したＭ１と異なり、第１の抵
抗手段内のトランジスタＭ１にはＮチャンネルＭＯＳＦ
ＥＴを用いている。Next, an embodiment having a function of selecting di / dt suppression according to the current value will be described with reference to FIG.
Except for the di / dt suppression selecting means 8 in FIG. 9, the remaining configuration is the same as that in FIG. 2 or FIG. However, in this embodiment, since only di / dt suppression at the time of turn-off is described, the second resistance means 4 is fixed at the resistance R2. Further, unlike the transistor M1 shown in FIG. 2, the transistor M1 in the first resistance means has an N-channel MOSF.
ET is used.
【００２７】ｄｉ／ｄｔ抑制の選択手段８としては、ゲ
ート電圧検出手段６の出力Ｂをロジックインバータ９−
１を介して２入力ＮＡＮＤ回路１０−１に入力し、ＮＡ
ＮＤ回路１０−１の他の入力端子にはコレクタ電圧検出
手段５の出力Ａを入力する。ＮＡＮＤ回路１０−１の出
力をフリップフロップ手段１１のセット端子に入力す
る。駆動信号Ｓをロジックインバータ９−２に入力し、
その出力をＮＡＮＤ回路１０−２の一方の入力端子に入
力する。また、ロジックインバータ９−２の出力を分岐
してロジックインバータ９−３に入力し、９−３の出力
を抵抗Ｒ１１とコンデンサＣ１からなる遅延手段を介し
た後、ＮＡＮＤ回路１０−２の他方の入力端子に入力す
る。ＮＡＮＤ回路１０−２の出力はフリップフロップ手
段１１のリセット端子に入力する。ここで、フリップフ
ロップ手段１１の論理はセット端子にローレベルの信号
を入力すると出力Ｑがハイレベルになり、リセット端子
にローレベルの信号を入力すると出力Ｑはローレベルに
なる。また、上記フリップフロップ手段１１の出力をＣ
とすると、信号Ｃをロジックインバータ９−４を介して
ＡＮＤ回路１０−３の一方の入力端子に入力し、１０−
３の他方の入力端子には駆動信号Ｓを入力する。ＡＮＤ
回路１０−３の出力信号は第１の抵抗手段３内部のＭ１
に制御信号Ｓｏｆｆ２として出力する。As the di / dt suppression selecting means 8, the output B of the gate voltage detecting means 6 is used as the logic inverter 9-
1 to the 2-input NAND circuit 10-1 via the
The output A of the collector voltage detecting means 5 is input to another input terminal of the ND circuit 10-1. The output of the NAND circuit 10-1 is input to the set terminal of the flip-flop means 11. The drive signal S is input to the logic inverter 9-2,
The output is input to one input terminal of the NAND circuit 10-2. Further, the output of the logic inverter 9-2 is branched and input to the logic inverter 9-3, and the output of the logic inverter 9-3 is passed through delay means including a resistor R11 and a capacitor C1. Input to the input terminal. The output of the NAND circuit 10-2 is input to the reset terminal of the flip-flop unit 11. Here, the logic of the flip-flop means 11 is such that when a low level signal is input to the set terminal, the output Q becomes high level, and when a low level signal is input to the reset terminal, the output Q becomes low level. Also, the output of the flip-flop means 11 is C
Then, the signal C is input to one input terminal of the AND circuit 10-3 via the logic inverter 9-4,
The drive signal S is input to the other input terminal of the third terminal. AND
The output signal of the circuit 10-3 is M1 in the first resistance means 3.
As a control signal Soff2.
【００２８】上記構成による駆動方法はターンオフの期
間中にコレクタ電圧検出手段５及びゲート電圧検出手段
６の結果から、前述の平坦化したゲート電圧を検出し、
このゲート電圧に対応するコレクタ電流が設定値以上で
あればｄｉ／ｄｔを抑制することが特徴である。この動
作を次の図１０を用いて述べる。The driving method according to the above configuration detects the flattened gate voltage from the results of the collector voltage detecting means 5 and the gate voltage detecting means 6 during the turn-off period.
If the collector current corresponding to the gate voltage is equal to or higher than a set value, di / dt is suppressed. This operation will be described with reference to FIG.
【００２９】図１０は、図９に示した駆動回路でターン
オフ時の動作説明図である。図１０（ａ）はＱ１を流れ
る電流が設定値未満の場合（小電流時と記す）、図１０
は電流が設定値レベル以上の場合（大電流時と記す）で
ある。図１０(ａ）と(ｂ）において、ｔ3(或いは
ｔ3′）の期間とｔ4(或いはｔ4′）の期間の境界では前
述のようにゲート電圧が平坦化し、その値は定常時のコ
レクタ電流に応じて大きくなる。電流値がＩｃ２以上に
おいて抑制を行う場合を例とすると、上記ゲート電圧は
図６（ｂ）からＶｇ２となる。そこで、電流がＩｃ２以
上の場合にｄｉ／ｄｔを抑制するためには、図９のツェ
ナーダイオードＺＤには、(Ｖｃｃ−Ｖｇ２）の値を降
服電圧とする素子を選ぶ。FIG. 10 is an explanatory diagram of the operation at the time of turn-off in the drive circuit shown in FIG. FIG. 10A shows a case where the current flowing through Q1 is smaller than the set value (hereinafter referred to as a small current).
Indicates a case where the current is equal to or higher than the set value level (indicated as a large current). In FIGS. 10A and 10B, at the boundary between the period of t 3 (or t 3 ′) and the period of t 4 (or t 4 ′), the gate voltage is flat as described above, Becomes larger according to the collector current. Taking the case where suppression is performed at a current value equal to or higher than Ic2 as an example, the gate voltage becomes Vg2 from FIG. 6B. Therefore, in order to suppress di / dt when the current is equal to or greater than Ic2, an element having a value of (Vcc-Vg2) as the breakdown voltage is selected as the Zener diode ZD in FIG.
【００３０】図１０（ｂ）の場合には駆動信号Ｓに応じ
たｔ3′ 期間の開始直後から第１の抵抗手段内のＭ１が
オンする。Ｓの印加直後にはＱ１のコレクタ電圧はＶｃ
１以下であるため、第１の電圧検出手段の出力ＡはＬで
ある。このためＮＡＮＤ回路１０−１の出力はＨであ
り、フリップフロップ手段の出力ＣはＬとなるためＳｏ
ｆｆ２はＨとなりＭ１をオンさせてＱ１のゲート容量を
急速に放電する。In the case of FIG. 10B, M1 in the first resistance means is turned on immediately after the start of the period t 3 'according to the drive signal S. Immediately after the application of S, the collector voltage of Q1 is Vc
Since it is 1 or less, the output A of the first voltage detecting means is L. Therefore, the output of the NAND circuit 10-1 is H, and the output C of the flip-flop means is L,
ff2 becomes H, turning on M1 and rapidly discharging the gate capacitance of Q1.
【００３１】ｔ3′ の期間の最終に達すると、Ｑ１のコ
レクタ電圧はＶｃ１に達し、出力ＡはＨに変化する。こ
の時、平坦化したゲート電圧が検出すべきＶｇ２以上で
あれば、ＺＤ１は降服せず、Ｍ４にはゲートバイアス電
圧が印加されないためオフであり、Ｂ点の電圧はＬであ
る。出力ＡがＨ，出力ＢがＬの条件が揃うとＮＡＮＤ回
路１０−１の出力はＬに変化し、フリップフロップ手段
の出力ＣもＨに変わる。この結果、Ｓｏｆｆ２はＬとな
りＭ１はオフして以後の期間ｔ4′ では、第１の抵抗手
段の抵抗値はＲ１の高抵抗になり、ゲート電圧の減少を
遅くして電流変化ｄｉ／ｄｔは抑制される。図９(ａ）
の場合にはｔ3の期間の最終で出力ＡはＨに変化した
際、平坦化したゲート電圧は検出すべきＶｇ２より小さ
いため、ＺＤ１は降服しＭ４はオン状態となってＢ点の
電圧はＨになる。この結果、フリップフロップ手段の出
力ＣはＬを維持するため、ターンオフの終了までＭ１の
オンも維持され、ｔ4 期間でのｄｉ／ｄｔ抑制は行われ
ない。At the end of the period t 3 ′, the collector voltage of Q1 reaches Vc1, and the output A changes to H. At this time, if the flattened gate voltage is equal to or higher than Vg2 to be detected, ZD1 does not drop and M4 is off because no gate bias voltage is applied, and the voltage at point B is L. When the conditions of the output A being H and the output B being L are met, the output of the NAND circuit 10-1 is changed to L, and the output C of the flip-flop is also changed to H. As a result, Soff2 becomes L and M1 is turned off, and in the subsequent period t 4 ′, the resistance value of the first resistance means becomes a high resistance of R1, and the reduction of the gate voltage is slowed down, and the current change di / dt becomes Is suppressed. FIG. 9 (a)
In the case of ( 3) , when the output A changes to H at the end of the period of t3, the flattened gate voltage is smaller than Vg2 to be detected, so that ZD1 drops off, M4 turns on, and the voltage at point B becomes H. As a result, the output C of the flip-flop means for maintaining L, and the on-end to M1 turn-off is also maintained, di / dt suppression in t 4 period is not performed.
【００３２】[0032]
【発明の効果】以上の説明から理解されるように、本発
明によれば電圧駆動形素子に適したサージ電圧及びノイ
ズの抑制が可能となり、素子にサージ電圧防止のスナバ
回路が不要になる他、スイッチング時のノイズが他の電
子機器へ影響を及ぼし誤動作を招く問題を解消すること
ができるという効果がある。As will be understood from the above description, according to the present invention, it is possible to suppress a surge voltage and a noise suitable for a voltage-driven element, and it becomes unnecessary to provide a snubber circuit for preventing a surge voltage in the element. In addition, there is an effect that a problem that noise at the time of switching affects other electronic devices and causes a malfunction can be solved.
【図１】本発明の一実施例を示す電圧駆動形素子の駆動
回路の基本ブロック図である。FIG. 1 is a basic block diagram of a drive circuit of a voltage-driven element showing one embodiment of the present invention.
【図２】図１の一実施例の具体的な回路構成図である。FIG. 2 is a specific circuit configuration diagram of the embodiment of FIG.
【図３】図２の実施例の動作を説明するための動作波形
である。FIG. 3 is an operation waveform for explaining the operation of the embodiment in FIG. 2;
【図４】本発明の他の実施例を示す電圧駆動形素子の駆
動回路の基本ブロック図である。FIG. 4 is a basic block diagram of a drive circuit of a voltage-driven element showing another embodiment of the present invention.
【図５】図４の実施例の具体的な回路構成図である。FIG. 5 is a specific circuit configuration diagram of the embodiment of FIG. 4;
【図６】図５の実施例の動作を説明するための動作波形
である。FIG. 6 is an operation waveform for explaining the operation of the embodiment in FIG. 5;
【図７】電圧駆動形素子の素子特性を説明する図であ
る。FIG. 7 is a diagram illustrating element characteristics of a voltage-driven element.
【図８】図４の実施例の他の具体的な回路構成図であ
る。8 is another specific circuit configuration diagram of the embodiment of FIG.
【図９】本発明に係るｄｉ／ｄｔ抑制を選択する駆動方
法の実施例である。FIG. 9 is an embodiment of a driving method for selecting di / dt suppression according to the present invention.
【図１０】図９の実施例の動作を説明するための動作波
形である。FIG. 10 is an operation waveform for explaining the operation of the embodiment in FIG. 9;
１…制御回路手段、２…負荷、３…第１の抵抗手段、４
…第２の抵抗手段、５…コレクタ電圧検出手段、ＳＷ
１，ＳＷ２…スイッチ手段、Ｑ１…電圧駆動形素子、Ｖ
ｃｃ…制御電源、ＶＥ…主電源、６…ゲート電圧検出手
段、７…電流検出手段。DESCRIPTION OF SYMBOLS 1 ... Control circuit means, 2 ... Load, 3 ... First resistance means, 4
... second resistance means, 5 ... collector voltage detection means, SW
1, SW2: switch means, Q1: voltage-driven element, V
cc: control power supply, VE: main power supply, 6: gate voltage detection means, 7: current detection means.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−299990（ＪＰ，Ａ) 特開 平４−141230（ＪＰ，Ａ) 特開 平４−241511（ＪＰ，Ａ) 実開 平２−103927（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H03K 17/00 - 17/70 H02M 1/00 - 1/30 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-299990 (JP, A) JP-A-4-141230 (JP, A) JP-A-4-241511 (JP, A) 103927 (JP, U) (58) Fields investigated (Int. Cl. 7 , DB name) H03K 17/00-17/70 H02M 1/00-1/30
Claims (7)
絶縁ゲート構造を有するゲート端子を具備する電圧駆動
形素子と、駆動信号に応じて前記電圧駆動形素子のゲー
ト電圧を減少させるオフゲート回路と、前記駆動信号に
応じて外部制御電源より前記ゲート端子に電圧を供給す
るオンゲート回路を備えた電圧駆動形素子の駆動回路に
おいて、 前記電圧駆動形素子のオフ時に前記第１，第２端子間の
電圧を検出し、該電圧を前記制御電源の電圧値以下の基
準電圧値と比較する電圧検出手段と、前記第１，第２端
子間の電圧が前記基準電圧値を超えた場合に前記オフゲ
ート回路の抵抗値を増加させて前記第１，第２端子間の
電圧の変化速度を抑制する可変抵抗手段とを備えたこと
を特徴とする電圧駆動形素子の駆動回路。The related input and output of 1. A main current 1, the voltage-driven element having a gate terminal having a second terminal insulating gate structure, the gate of said voltage driving type device in accordance with a drive signal
An off-gate circuit for reducing the driving voltage;
Supply a voltage to the gate terminal from an external control power supply
A voltage-driven element driving circuit having an on- gate circuit that detects a voltage between the first and second terminals when the voltage-driven element is turned off, and detects the voltage between the first and second terminals . Base below voltage
Voltage detecting means for comparing with a quasi-voltage value, the first and second terminals
When the voltage between the terminals exceeds the reference voltage value,
Over preparative said first to increase the resistance of the circuit, the driving circuit of the voltage drive element characterized in that a suppressing variable resistance means the change speed of the voltage between the second terminal.
絶縁ゲート構造を有するゲート端子を具備する電圧駆動
形素子と、駆動信号に応じて前記電圧駆動形素子のゲー
ト電圧を減少させるオフゲート回路と、前記駆動信号に
応じて外部制御電源より前記ゲート端子に電圧を供給す
るオンゲート回路を備えた電圧駆動形素子の駆動回路に
おいて、 前記電圧駆動形素子のオン時に前記第１，第２端子間の
電圧を検出し、該電圧を前記制御電源の電圧値以下の基
準電圧値と比較する電圧検出手段と、前記第１，第２端
子間の電圧が前記基準電圧値以下となる場合に前記オフ
ゲート回路の抵抗値を減少させて前記第１，第２端子間
の電圧の変化速度を速くする可変抵抗手段とを備えたこ
とを特徴とする電圧駆動形素子の駆動回路。 2. A voltage-driven element having first and second terminals related to input and output of a main current and a gate terminal having an insulated gate structure, and a gate of the voltage-driven element in response to a drive signal.
An off-gate circuit for reducing the driving voltage;
Supply a voltage to the gate terminal from an external control power supply
A voltage-driven element driving circuit having an on- gate circuit , wherein when the voltage-driven element is turned on, a voltage between the first and second terminals is detected, and the voltage is detected by the control power supply. Base below voltage
Voltage detecting means for comparing with a quasi-voltage value, the first and second terminals
When the voltage between the slaves is lower than the reference voltage value,
The first reduces the resistance value of the gate circuit, the driving circuit of this <br/> and voltage drive element characterized with a variable resistance means to increase the rate of change of the voltage between the second terminal.
絶縁ゲート構造を有するゲート端子を具備する電圧駆動
形素子における前記第２端子と前記ゲート端子間に接続
され第１のスイッチ手段及び該第１のスイッチ手段に直
列あるいは並列な第１の抵抗手段を備えるオフゲート回
路と、外部制御電源より第２のスイッチ手段及び該第２
のスイッチ手段に直列あるいは並列な第２の抵抗手段を
介して前記ゲート端子にゲート電圧を印加するオンゲー
ト回路を備える電圧駆動形素子の駆動回路において、 前記第１，第２端子間の電圧を検出する電圧検出手段
と、前記電圧駆動形素子のオン時あるいはオフ時に、前
記第１あるいは第２の抵抗手段の少なくともいずれかは
前記電圧検出手段からの電圧検出信号に基づいて抵抗値
を変化させる抵抗可変手段を備えることを特徴とする電
圧駆動形素子の駆動回路。3. A first switch connected between said second terminal and said gate terminal in a voltage-driven device having first and second terminals involved in input and output of a main current and a gate terminal having an insulated gate structure. Means and an off-gate circuit comprising a first resistance means connected in series or parallel to the first switch means, and a second switch means and the second
A voltage driving element comprising an on-gate circuit for applying a gate voltage to the gate terminal via a second resistor means in series or parallel with the switch means, wherein a voltage between the first and second terminals is detected. At least one of the first and second resistance means changes a resistance value based on a voltage detection signal from the voltage detection means when the voltage-driven element is turned on or off. A driving circuit for a voltage-driven element, comprising a variable means.
絶縁ゲート構造を有するゲート端子具備する電圧駆動形
素子と、駆動信号に応じて前記電圧駆動形素子のゲート
電圧を減少させるオフゲート回路と、前記駆動信号に応
じて外部制御電源より前記ゲート端子に電圧を供給する
オンゲート回路を備えた電圧駆動形素子の駆動回路にお
いて、 前記電圧駆動形素子のオン時あるいはオフ時に前記ゲー
ト端子と前記第２端子間の電圧を検出し、該電圧を前記
制御電源の電圧値以下の基準電圧値と比較する第１の電
圧検出手段と、前記ゲート電圧を検出する第２の電圧検
出手段と、前記第１，第２の電圧検出手段の出力に応じ
て前記オフゲート回路の抵抗値を変化させ前記第１，第
２端子間電圧の変化速度を抑制する可変抵抗手段とを備
えたことを特徴とする電圧駆動形素子の駆動回路。 4. A voltage-driven element having first and second terminals related to input and output of a main current and a gate terminal having an insulated gate structure, and a gate of the voltage-driven element according to a drive signal.
An off-gate circuit for reducing the voltage;
Supply a voltage to the gate terminal from an external control power supply
And have you <br/> the drive circuit of the voltage drive device having a on-gate circuit, detecting a voltage between the gate <br/> preparative terminal and the second terminal when on-time or off of the voltage drive element And the voltage is
A first power source for comparison with a reference voltage value equal to or lower than the control power source voltage value;
Voltage detecting means, and a second voltage detecting means for detecting the gate voltage.
Output means and an output of the first and second voltage detecting means.
Variable resistance means for changing a resistance value of the off-gate circuit to suppress a changing speed of the voltage between the first and second terminals.
Driving circuit of the voltage drive element characterized in that there was e.
第２端子間のゲート電圧検出手段と、該ゲート電圧検出
手段からのゲート電圧検出信号に基づいて、前記第１あ
るいは第２の抵抗手段の少なくともいずれかの抵抗値を
変化させる抵抗可変手段を備えたことを特徴とする電圧
駆動形素子の駆動回路。5. The first or second resistance means according to claim 3, wherein a gate voltage detection means between said gate terminal and said second terminal, and a gate voltage detection signal from said gate voltage detection means. A driving circuit for a voltage-driven element, comprising: a resistance variable means for changing at least one of the resistance values.
電流の大きさを検出する電流検出手段と、該電流検出手
段からの電流検出信号に基づいて前記第１の抵抗手段に
おける抵抗値を変化させる抵抗可変手段を備えたことを
特微とする電圧駆動形素子の駆動回路。6. A current detecting means according to claim 3 or 5, wherein a resistance value of said first resistance means is determined based on a current detection signal from said current detecting means. A driving circuit for a voltage-driven element, characterized by comprising a variable resistance means for changing the resistance.
絶縁ゲート構造を有するゲート端子を具備する電圧駆動
形素子と、前記電圧駆動形素子の第１，２端子間に接続
される主電源及び負荷と、前記第２端子と前記ゲート端
子間に接続され第１のスイッチ手段及び該第１のスイッ
チ手段に直列あるいは並列な第１の抵抗手段を備えるオ
フゲート回路と、外部制御電源より第２のスイッチ手段
及び該第２のスイッチ手段に直列あるいは並列な第２の
抵抗手段を介して前記ゲート端子にゲート電圧を印加す
るオンゲート回路と、前記第１および第２のスイッチ手
段をオン・オフする制御回路と、前記第１，第２端子間
の電圧を検出する電圧検出手段と、を備え、 前記電圧駆動形素子のオン時あるいはオフ時に、前記第
１あるいは第２の抵抗手段の少なくともいずれかは前記
電圧検出手段からの電圧検出信号に基づいて抵抗値を変
化させる抵抗可変手段を備えることを特徴とする電圧駆
動形素子の駆動回路。7. A voltage-driven element having first and second terminals related to input and output of a main current and a gate terminal having an insulated gate structure, and connected between the first and second terminals of the voltage-driven element. An off-gate circuit connected between the second terminal and the gate terminal, comprising a first switch means and a first resistance means connected in series or parallel to the first switch means; and an external control power supply. An on-gate circuit for applying a gate voltage to the gate terminal via a second switch means and a second resistor means in series or parallel with the second switch means, and turning on the first and second switch means; A control circuit for turning off, and voltage detecting means for detecting a voltage between the first and second terminals, wherein the first or second resistance means is turned on or off when the voltage-driven element is turned on or off. At least one of them includes a resistance variable means for changing a resistance value based on a voltage detection signal from the voltage detection means, and a driving circuit for a voltage-driven element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05073081A JP3141613B2 (en) | 1993-03-31 | 1993-03-31 | Method and circuit for driving voltage-driven element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05073081A JP3141613B2 (en) | 1993-03-31 | 1993-03-31 | Method and circuit for driving voltage-driven element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06291631A JPH06291631A (en) | 1994-10-18 |
| JP3141613B2 true JP3141613B2 (en) | 2001-03-05 |
Family
ID=13508031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05073081A Expired - Fee Related JP3141613B2 (en) | 1993-03-31 | 1993-03-31 | Method and circuit for driving voltage-driven element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3141613B2 (en) |
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|---|---|
| JPH06291631A (en) | 1994-10-18 |
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