JP2000295834A - Power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive downsizing by enabling the capacity of a snubber capacity to be reduced. SOLUTION: A gate voltage detector 10 detects the voltage of a gate G, and an element voltage detector 20 detects the voltage Vce of an element, and a comparator 22 for detection of overvoltage compares this element voltage Vce with the element voltage at off position stored in a peak value detecting circuit 18, and when the detected element voltage Vce gets over the element voltage Vce at off position, it detects the occurrence of overvoltage. Consequently, in a signal holding circuit 23, the first AND circuit 24, the first voltage application part 40, a pulse generator 50, and the second voltage application part 60, when the turn off is detected by a turn off detector 16, they supply the gate G of an insulated gate type of bipolar transistor(IGBT) with an ON signal at low voltage, and, when overvoltage is detected by the comparator 22 for detection of overvoltage, they stop the supply of ON signals at low voltage. This way, IGBT1 is half turned on at the time of turn off, and a dV/dt is controlled separately from a CRD-type snubber circuit S1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter having a plurality of power switching elements, and more particularly, to suppressing the overvoltage at the time of turn-off, reducing the capacitor capacity of a snubber circuit, and achieving downsizing. The present invention relates to an obtained power converter.

[0002]

2. Description of the Related Art Generally, in power conversion devices such as inverters and converters, power MOSFETs, IGBTs (insulated gate bipolar transistors), SITs (static induction transistors) or IITs are used as power switching elements.
A MOS gate input type semiconductor element such as an EGT (Electron Injection Promoting Transistor) is used.

[0003] This type of semiconductor device has the advantage of shortening the switching time and the like, as well as controlling the gate signal.
This has the advantage that the switching state can be changed relatively easily.

In addition, this type of semiconductor device has a CRD type snubber circuit or a clamp type snubber having a snubber capacitance value that can be arbitrarily designed in order to protect against an overvoltage or a voltage rise rate dVce / dt applied at the time of turn-off. A circuit is used. In general, a CRD snubber circuit is used when a small-capacity converter or a power element is connected in series, and a clamp-type snubber circuit is used for a medium-capacity converter.

FIG. 13 is a circuit diagram showing a configuration of a power conversion device in which such a CRD type snubber circuit is applied to upper and lower arm main circuits. FIG. 14 is a circuit diagram showing a configuration of a power conversion device in which a clamp type snubber circuit is applied to a main circuit of an upper / lower arm.

As a common main circuit to which each snubber circuit is applied, for example, the upper arm includes a positive power supply Ea1 and a positive switch Sa1, and a negative power supply Eb1 and a negative switch Sb1.
A gate drive circuit that applies a positive or negative gate voltage to a gate G via a gate resistor Rg1 in accordance with a gate pulse GP given to both switches Sa1 and Sb1;
ON / OFF depending on the gate voltage applied to the gate drive circuit
It is composed of a main switching element IGBT1 of a MOS gate input type in an off state, and a free wheel diode Df1 connected in anti-parallel between the collector C and the emitter E of the main switching element IGBT1.

On the other hand, the lower arm is configured similarly to the upper arm. Main switching element IGB of upper arm
The emitter E of T1 is connected to the collector C of the main switching element IGBT2 of the lower arm.

As shown in FIG. 13, in the CRD type snubber circuit, a series circuit of snubber diodes D1 and D2 and snubber capacitors C1 and C2 is provided for each main switching element IGBT1 and IGBT2. Connected in parallel,
And resistors R1 and R2 for snubber are diodes D1,
D2 is connected in parallel.

In the CRD type snubber circuit, at the time of turn-off, the energy stored in the wiring inductance is discharged, and when an instantaneous overvoltage higher than the circuit voltage is applied to the main switching element IGBT1, the capacitors C1, C
2 has a function of suppressing an overvoltage by accumulating (overcharging) electric charges. This operation occurs every turn-off. However, there is a disadvantage that the resistors R1 and R2 generate a large amount of heat.

On the other hand, in the clamp type snubber circuit, as shown in FIG. 14, a series circuit of snubber capacitors C1 and C2 and snubber diodes D1 and D2 is connected in parallel to each main switching element IGBT1 and IGBT2. Connected to
One end of snubber resistors R1 and R2 is connected to capacitors C1 and C2.
2 and diodes D1 and D2, and a resistor R
The other end of R1,2 is connected to the emitter side or collector side of the other IGBT2,1.

That is, the clamp type snubber circuit has a configuration in which the capacitors C1 and C2 are wired crosswise, and the capacitors C1 and C2 are charged up to the circuit voltage in advance.
When applied to the BTs 1 and 2, the capacitors C1 and C2 have a function of clamping an overvoltage by accumulating (overcharging) charges in the capacitors C1 and C2. This operation occurs every turn-off.

The clamp type snubber circuit has an advantage that the loss energy is smaller than that of the non-charge type snubber circuit because the loss energy corresponds to the overcharge of the electric charge.

FIG. 15 shows a configuration in which main circuits with snubbers shown in FIG. 13 are connected in series.
, The configuration of a power conversion device in which voltage-dividing resistors Rb1, Rb2,..., Rbj are connected in parallel.

By the way, these power converters require physical switching such as when the main switching elements IGBT1 and IGBT2 are connected in series or when the main switching elements IGBT1 and IGBT2 are connected in series. For some reason, there is a tendency that the wiring length of the main circuit is inevitably lengthened and the wiring inductance L is increased.

The increase in the wiring inductance L of the main circuit is as follows.
Overvoltage at the time of turn-off is increased, and a large electric stress is caused to the main switching elements IGBT1 and IGBT2. Therefore, the electrical stress can be reduced and the main switching element I
From the viewpoint of averaging the voltage sharing by filling in the characteristic difference (accumulation time difference) of each element when the GBTs 1 and 2 are connected in series, it is necessary to suppress the rise rate dVce / dt of the element voltage.

When suppressing dVce / dt, generally, a CRD type snubber circuit uses a main switching element IGBT.
It is mounted close to 1,2. At this time, the capacitances and volumes of the snubber capacitors C1 and C2 are determined by the magnitude of the main circuit inductance and the working voltage. Therefore, as the slope of dVce / dt to be suppressed increases, a large snubber capacitor capacity is required. Therefore, the size of the CRD snubber circuit is increased, and the size of the power converter is increased.

On the other hand, the clamp type snubber circuit has a main switching element IGBT having a relatively large dVce / dt.
In 1 and 2, the present invention is applied to a main circuit that suppresses only overvoltage. In this clamp type snubber circuit, the snubber capacitor capacity can be set small, and the effect of suppressing overvoltage and EMI (electromagnetic interference) is high. However, as can be seen from FIG. 14, the clamp type snubber circuit has a main switching element IGB.
It is difficult to obtain a clamp potential for the series connection of T1 and T2 and cannot be adopted.

The clamp type snubber circuit cannot be applied to a circuit in which two or more main switching elements IGBT1 and IGBT2 are connected in series with one arm due to cross wiring.

Therefore, as shown in FIG. 15, in a high-voltage power converter in which a number of main switching elements IGBT1 to IGBTj are connected in series, there is no usable low-loss snubber circuit. A CRD type snubber with a large loss is used.

However, power converters are required to be smaller and lighter from the viewpoint of competitiveness or cost. In particular, in a high-withstand-voltage power converter in which a plurality of main switching elements IGBT1 and IGBT2 are connected in series, there is a strong demand for reduction in size and weight.

Therefore, in the power converter for high voltage, a snubber circuit system that can connect the main switching elements IGBT1 and IGBT2 in series and has an overvoltage suppression capability similar to that of the clamp type snubber circuit is desired.

[0022]

As described above, in the conventional power converter, the main switching element I having a high withstand voltage is used.
When the GBTs 1 and 2 are used, a high overvoltage is generated at the time of turn-off, but since there is no snubber circuit with a small capacitor capacity, a large-capacity snubber circuit is attached and the weight increases.

In particular, three or more main switching elements IG
When BT1 to IGBTj are connected in series, it is extremely difficult to realize a reduction in size and weight because a clamp-type snubber circuit that can reduce the capacitance of a capacitor cannot be applied.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power conversion device capable of reducing the snubber capacitor capacity and reducing the size and weight.

[0025]

According to a first aspect of the present invention, there is provided a MOS gate input type switching element having a collector terminal, an emitter terminal, and a gate terminal, and provided between the collector terminal and the emitter terminal. A power conversion device comprising: a CRD type snubber circuit having a capacitance lower than a capacitance required for suppressing dV / dt at the time of turn-off; and a gate drive circuit for supplying an ON signal or an OFF signal to the gate terminal. ON / OFF detection means for detecting an ON signal and an OFF signal applied to a gate terminal, element voltage detection means for detecting an element voltage between the collector terminal and the emitter terminal, and the element voltage detection The device voltage detected by the means is compared with a predetermined voltage, and when the device voltage exceeds the predetermined voltage, occurrence of an overvoltage is detected. When a change from the ON signal to the OFF signal is detected by the voltage detecting means and the ON / OFF detecting means, an ON signal having a lower voltage than the ON signal is supplied to the gate terminal, and the overvoltage detecting means is provided. And dV / dt suppressing means for stopping the supply of the low-voltage ON signal when an overvoltage is detected.

According to a second aspect of the present invention, in the power converter according to the first aspect, an overvoltage is detected by the overvoltage detection means instead of the on / off detection means and the dV / dt suppression means. The power converter includes overvoltage clamping means for supplying an ON signal having a lower voltage than the ON signal to the gate terminal when the signal is turned on.

According to a third aspect of the present invention, in the power converter according to the first or second aspect, the gate drive circuit has a value higher than an absolute value of an on signal as the off signal. And a negative potential having an absolute value of?

According to a fourth aspect of the present invention, in the power converter according to the first aspect, when an overvoltage is detected by the overvoltage detecting means, the low voltage ON signal is supplied to the gate terminal. It is a power converter provided with overvoltage suppression means.

Further, according to a fifth aspect of the present invention, there is provided a MOS transistor having a collector terminal, an emitter terminal, and a gate terminal.
C is provided between the gate input type switching element and the collector terminal and the emitter terminal, and has a lower capacitance than the capacitance required for suppressing dV / dt at the time of turn-off.
A plurality of arm structures each including an RD-type snubber circuit and a gate driving circuit that supplies a positive potential on signal or a negative potential off signal having an absolute value higher than the absolute value of the on signal to the gate terminal are provided. A power conversion device arranged so as to connect the switching elements in series with each other, wherein each of the arm structures includes element voltage detection means for detecting an element voltage between the collector terminal and the emitter terminal. Comparing the element voltage detected by the element voltage detection means with a predetermined voltage, and detecting the occurrence of an overvoltage when the detected element voltage exceeds the predetermined voltage; and the overvoltage detection means And an overvoltage suppressing unit that supplies an on signal having a voltage lower than the on signal to the gate terminal when an overvoltage is detected by the power converter.

(Operation) Therefore, the invention corresponding to claim 1 takes the above-described means, whereby the on / off detection means detects the on signal and the off signal applied to the gate terminal, and the element voltage The detecting means detects an element voltage between the collector terminal and the emitter terminal, and the overvoltage detecting means compares the element voltage detected by the element voltage detecting means with a predetermined voltage, and the element voltage exceeds the predetermined voltage. When the occurrence of overvoltage is detected, and the dV / dt suppressing means detects a change from the on signal to the off signal by the on / off detecting means, it supplies an on signal of a voltage lower than the on signal to the gate terminal. Then, when the overvoltage is detected by the overvoltage detection means, the supply of the low-voltage ON signal is stopped, so that the switching element is turned on halfway at the time of turn-off, and d
Since V / dt is suppressed separately from the CRD type snubber circuit,
Soft interruption and suppression of overvoltage can be realized with a small snubber capacitance value, so that the snubber capacitor capacitance can be reduced.
The size and weight can be reduced.

The invention corresponding to claim 2 is an on / off switch.
Instead of the off detection means and the dV / dt suppression means, the overvoltage clamp means supplies an on signal of a lower voltage than the on signal to the gate terminal when the overvoltage is detected by the overvoltage detection means. By clamping the clamp of the overvoltage instead of the suppression, the same operation as the operation according to claim 1 can be achieved.

Further, in the invention corresponding to claim 3, the gate drive circuit applies a negative potential having an absolute value higher than the absolute value of the on signal to the gate terminal as the off signal. In addition, in addition to the operation corresponding to claim 2, when a normal power switching element is configured as a single-phase or three-phase bridge, delay times with other phases can be matched, dead time can be minimized, and distortion can be reduced. Output waveform can be obtained.

According to a fourth aspect of the present invention, when an overvoltage is detected by the overvoltage detecting means, an overvoltage suppressing means for supplying a low-voltage ON signal to the gate terminal is added. In addition to action, overvoltage can be clamped.

Further, in the invention corresponding to claim 5, since each arm structure having the same configuration as that of claim 3 corresponding to claim 2 is arranged so as to connect the switching elements in series with each other, claim 2 In addition to the same operation as in claim 3, the storage time is reduced to 1 / n of the normal by driving the voltage-driven gate drive circuit, and the delay time due to the difference in storage time of each switching element is minimized. Therefore, the voltage distribution applied to each switching element can be equalized, so that even in a configuration in which the switching elements are connected in series,
Unlike the related art, an overvoltage can be suppressed by using a CRD type snubber circuit, as in the case where a clamp type snubber is applied.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a main circuit in a unit of one arm of a power converter according to a first embodiment of the present invention. Reference numerals are used and detailed description is omitted, and different portions are mainly described here. In the following respective embodiments, the duplicated description will be omitted in the same manner. Also, C1, R1,
The CRD-type snubber circuit S1 composed of D1 is designed with a lower capacitor capacitance than the conventional one, although the sign is the same as that of the conventional one because dVce / dt is suppressed by the method of the present invention described later.

In this embodiment, the overvoltage is suppressed by suppressing the voltage rise rate dVce / dt at the time of turn-off. More specifically, as shown in FIG.
0, on / off detection comparator 14, turn-off detection unit 1
6, turn-on detection unit 17, peak value detection circuit 18, element voltage detection unit 20, overvoltage detection comparator 22, signal holding circuit 23, first AND circuit 24, detection control unit 30, off period detection comparator 33, A first voltage application unit 40, a pulse generation unit 50, and a second voltage application unit 60 are provided.

The gate voltage detector 10 detects the voltage between the gate G and the emitter E and outputs the voltage to the on / off detection comparator 14 and the detection controller 30. Two resistors 11 and 12 connected in series between the gate G and the emitter E;
A buffer amplifier 13 that amplifies the voltage between the two and outputs the amplified voltage to the on / off detection comparator 14 and the detection control unit 30 is used.

The on / off detection comparator 14 detects the on / off state from the detection result of the gate voltage detection unit 10 and outputs the on / off state to the turn-off detection unit 16 and the turn-on detection unit 17. It has a function of generating an output by comparison with the power supply 15 and providing the output to the turn-off detection unit 16 and the turn-on detection unit 17. In the on / off detection comparator 14, a diode (not shown) is inserted in the output side in the forward direction because the output is digitally processed, and the output when off is set to zero potential (the output when on is positive. Potential). This diode (not shown) is similarly inserted in all the other comparators 22 and 33 in this specification.

The turn-off detection section 16 generates a pulse signal when the output of the on-off detection comparator 14 is turned off and supplies the pulse signal to the signal holding circuit 23.

The turn-on detecting section 17 generates a pulse signal when the output of the on-off detecting comparator 14 is turned on and supplies the pulse signal to the peak value detecting circuit 18.

The element voltage detecting section 20 detects the element voltage Vce of the main switching element IGBT1 and outputs it to the peak value detecting circuit 18, the overvoltage detecting comparator 22, and the detection control section 30. CRD type snubber circuit S
1, two series resistors Rb1 and Rb2 connected in parallel to
The voltage between the two resistors Rb1 and Rb2 is amplified and the peak value detection circuit 18, the overvoltage detection comparator 22, and the detection control unit 30 are amplified.
And a buffer amplifier 21 that outputs the data to the memory.

When the switch 18a receives the pulse signal of the turn-on detecting section 16, the peak value detecting circuit 18 detects the peak value (off-state element voltage) of the element voltage Vce output from the element voltage detecting section 20. And is connected to a parallel circuit of a switch 18a and a capacitor 18b.

The overvoltage detecting comparator 22 compares the output of the element voltage detecting section 20 with the output of the peak value detecting circuit 18 and outputs the output of the element voltage detecting section 20 to the peak value detecting circuit 18.
When the output of the signal holding circuit 23 exceeds
To be sent.

The signal holding circuit 23 is for detecting a period from the start of turn-off to the time when the element voltage at the time of first turn-off is reached.
The output signal is shifted to the positive potential side by the pulse signal of No. 6,
When the output of the overvoltage detection comparator 22 shifts to zero potential,
The output signal is shifted to zero potential, and the output signal is held and applied to the first AND circuit 24.

The detection control unit 30 includes the comparator 2 for overvoltage detection.
2, the output side of the element voltage detection unit 20 is separated from the input side of the off period detection comparator 33 when the detection result of the gate voltage detection unit 10 indicates the ON state, When the detection result of No. 10 indicates the off state, the output side of the element voltage detecting unit 20 is set to the off period detecting comparator 2
2, and specifically, an inversion circuit 31 for inverting the detection voltage of the gate voltage detection unit 10.
And the element voltage detector 20 and the subsequent off-period detection comparator 33 are separated (opened) according to the output of the inverting circuit 31.
/ Connecting switch 32.

The off-period detection comparator 33 outputs the output of the element voltage detection unit 20 (the element voltage V
ce) is compared with a reference voltage from the reference power supply 34. When the element voltage Vce exceeds the reference voltage, a positive potential output signal is supplied to the first AND circuit 24.

The first AND circuit 24 includes a signal holding circuit 23
And the output of the off-period detection comparator 33 and outputs the result to the first voltage application unit 40 and the pulse generation unit 50.

The first voltage application section 40 is provided with the first AND circuit 2
4, a positive voltage is applied to the gate terminal G. Specifically, a positive switch E of the gate drive circuit is applied.
It comprises a series circuit consisting of a resistor 41 and a switch 42 connected in parallel to a1.

The pulse generator 50 generates a pulse train of a predetermined cycle, and supplies the pulse train to the second voltage applying unit 60 during the output period of the first AND circuit 24. Pulse number counter 52, volume 53, V / F conversion circuit 54, setting switch 55, 2A
The ND circuit 56 is provided.

When the output of the first AND circuit 24 changes from zero potential to the positive potential side, the starter 51 presets the set value of the setting switch 55 to the pulse number counter 52.

The pulse number counter 52 counts the clock signal received from the V / F conversion circuit 54, and outputs the count result (F) to the second AND circuit 56 in accordance with the setting content (n) of the setting switch 53 (F / F). n)
For example, an F / n frequency divider can be used.

The volume 53 has a predetermined voltage V
To the V / F conversion circuit 54, and for example, a variable resistor connected to a power supply can be used. Note that the set voltage V of the volume 53 is the voltage rise rate dVce / after subtracting the amount absorbed by the snubber circuit S1.
Based on dt, it is set according to the degree to which this dVce / dt is further reduced.

The V / F conversion circuit 54 converts the voltage V supplied from the volume 53 into a clock signal having a frequency F and supplies the clock signal to the pulse number counter 52.

The setting switch 55 allows an arbitrary numerical value n to be set in order to control the output of the pulse number counter (F / n frequency divider) 52 to 1 / n of the count value F. The switch is enabled.

The second AND circuit 56 is connected to the first AND circuit 2
The logical product of the output of the pulse number counter 52 and the output of the pulse number counter 52 is given to the second voltage applying unit 60.

The second voltage applying section 60 is connected to the second AND circuit 5
6, for applying a positive voltage to the gate terminal G in accordance with the output of the gate drive circuit 6. Specifically, it is connected in parallel to a series circuit including a positive power supply Ea1, a positive switch Sa1, and a gate resistor Rg1 of a gate drive circuit. , Two positive-side power supplies 61,
It comprises a series circuit consisting of a resistor 62, a resistor 63 and a switch 64. Here, the switch 64 is connected to the output side of the second AND circuit 56.

The first and second voltage applying sections 40 and 60
Is such a value that it is not detected as turned on by the on / off detection comparator 14, and is lower than the voltage of the reference power supply 15 of the comparator 14.

Next, the operation of the power converter configured as described above will be described with reference to the time chart of FIG.

Now, C of the main switching element IGBT1
It is assumed that a DC voltage Vce is applied between E and E. At this time, it is assumed that the on / off detection comparator 14 outputs an off state signal indicating an off state as shown in FIG. 2A (time t0). That is, it is assumed that the current state is the off state.

Next, the turn-on process of shifting from the off state to the on state will be described. Now, when the negative switch Eb1 of the gate drive circuit is turned off and the positive switch Ea1 is turned on, the main switching element IGB
The gate voltage between GE at T1 shifts from the negative potential to the positive potential side (time t1). Thereby, the gate voltage detection unit 1
The 0 buffer amplifier 13 supplies an output signal that shifts from the negative potential to the positive potential side to the on / off detection comparator 14 and the detection control unit 30.

When the detection control unit 30 receives the output signal which shifts to the positive potential side, the inversion circuit 31 inverts the output signal and supplies the switch 32 with an output signal which shifts to the negative potential side.
By turning off the switch 32, the element voltage detection unit 2
0 and the off-period detection comparator 33 are separated.

On the other hand, when the output of the buffer amplifier 13 exceeds the potential of the reference power supply when the output of the buffer amplifier 13 shifts to the positive potential side, as shown in FIG. Instead, an on-state signal is given to the turn-off detector 16 and the turn-on detector 17 (time t1).

The turn-off detector 16 ignores the on-state signal, but when the turn-on detector 17 receives the on-state signal, it generates a pulse signal of a predetermined width as shown in FIG. This is given to the peak value detection circuit 18 (time t1).

When activated by this pulse signal, the peak value detecting circuit 18 stores the peak value of the element voltage Vce provided from the element voltage detecting section 20 (time t2). The stored device voltage Vce is the device voltage immediately after the device is turned on, that is, the device voltage V in a stable state when the device is turned off.
ce.

As described above, the turn-on process is completed (time t3). Next, a turn-off process of shifting from the on-state to the off-state will be described. The negative switch Eb1 of the gate drive circuit is turned on and the positive switch Ea1 is turned on.
Is turned off (time t4), the buffer amplifier 13 of the gate voltage detection unit 10 outputs the output signal that shifts from the positive potential to the negative potential side to the on-off detection comparator 14 and the detection control unit 3.
Give to 0.

When receiving the output signal which shifts to the negative potential side, the detection control section 30 turns on the switch 32 via the inverting circuit 31 to turn on the output side of the element voltage detection section 30 and the off period detection comparator 33. Connect to the input side of.

When the output of the element voltage detection section 20 received via the detection control section 30 exceeds the reference voltage of the reference power supply 34, the off-period detection comparator 33 outputs an output signal indicating the presence of the element voltage Vce to zero potential. To the positive potential and the first AND
To the circuit 24.

On the other hand, when the output of the buffer amplifier 13 falls below the potential of the reference power supply 15 when the output of the buffer amplifier 13 shifts to the negative potential side, as shown in FIG. An off-state signal is supplied to the turn-off detector 16 and the turn-on detector 17 instead of the signal (time t5).

The turn-on detection section 17 ignores the off-state signal, but when the turn-off detection section 16 receives the off-state signal, it generates a pulse signal having a predetermined width as shown in FIG. Given to the signal holding circuit 23 (time t
5).

The signal holding circuit 23 is set by the pulse signal, changes the output signal from zero potential to positive potential, and supplies the output signal to the first AND circuit 24. When the first AND circuit 24 receives the output signal of the positive potential from the signal holding circuit 23 and the comparator 33 for detecting the OFF period, respectively, the first AND circuit 24 outputs the output signal of the positive potential to the first voltage applying unit as shown in FIG. 40 and the pulse generator 50 (time t5).

The first voltage application section 40 turns on the switch 42 in response to the output signal, connects the positive power supply Ea1 to the gate G of the main switching element IGBT via the resistor 41, and changes the gate voltage from the turn-off state to the main state. The potential is maintained at a predetermined potential lower than the threshold value of the switching element IGBT. This predetermined potential is set by the resistor 41.

On the other hand, in the pulse generation section 50, the first AND
In response to the output of the circuit 24, the activation unit 51 presets the setting value of the setting switch 55 in the pulse number counter 52. Thereby, the pulse number counter 52 counts the clock signal received from the V / F conversion circuit 54 according to the set voltage of the volume 53, and outputs the count result to the setting switch 55.
Is converted into a pulse signal in accordance with the setting contents of the above, and a pulse train composed of the pulse signal is output to the second AND circuit 56.

As shown in FIG. 2 (f), when the second AND circuit 56 receives a positive potential output signal from the first AND circuit 24, it passes the pulse train output from the pulse number counter 52 to apply the second voltage. (Time t5)
~).

The second voltage applying section 60 turns on the switch 64 in accordance with the pulse train, and switches the positive voltages from the positive power supplies 61 and 62 via the resistor 63 to the main switching as shown in FIG. The voltage is applied to the gate G of the element IGBT1 (time t6).

Thus, main switching element IGBT
1 is controlled to be in an on state during the turn-off from the start of the turn-off, so that the voltage rise rate dVce / dt can be reduced.

Subsequently, when the element voltage Vce rises and exceeds the OFF-state steady value due to overshoot (at time t).
7), the overvoltage detection comparator 22 shifts the output signal from the positive potential to the zero potential side and supplies it to the signal holding circuit 23. The signal holding circuit 23 is reset by the output signal shifted to the negative potential side, The output signal is shifted from the positive potential to the zero potential side and applied to the first AND circuit 24.

As a result, the first AND circuit 24 operates as shown in FIG.
As shown in (e), the output signal is shifted to zero potential and applied to the first voltage application unit 40 and the pulse generation unit 50 (at time t).
7) Stop applying the gate voltage by the first voltage application unit 40 and the second voltage application unit 60.

Hereinafter, the main switching element IGBT1 is
The dVce / dt overshoots at a value lower than dVce / dt (indicated by a broken line) when there is no control, and then shifts to the off-state element voltage Vce. Thus, the turn-off process is completed (time t8).

As described above, according to the first embodiment,
The gate voltage detector 10 detects a gate voltage (ON signal and OFF signal) applied to the gate terminal G, and the element voltage detector 20 detects an element voltage Vce between the collector terminal C and the emitter terminal E. , The overvoltage detection comparator 22
The device voltage Vce detected by the device voltage detection unit 20 is compared with the device voltage in the off state stored in the peak value detection circuit 18, and the detected device voltage Vce is compared with the device voltage V in the off state.
When ce is exceeded, the occurrence of overvoltage is detected.

Thus, the signal holding circuit 23, the first AN
In the D circuit 24, the first voltage application unit 40, the pulse generation unit 50, and the second voltage application unit 60, when the change from the ON signal to the OFF signal is detected by the turn-off detection unit 16, the gate terminal of the main switching element IGBT1 is used. G is supplied with an ON signal having a lower voltage than the ON signal, and the overvoltage detection comparator 2
When an overvoltage is detected by step 2, the supply of the low-voltage ON signal is stopped, so that the switching element is turned on halfway at the time of turn-off, and dV / dt is suppressed separately from the CRD type snubber circuit S1.

For this reason, soft interruption and suppression of overvoltage can be realized with a small snubber capacitance value, so that the snubber capacitor capacitance can be reduced and the size and weight can be reduced.

Further, by controlling the low voltage ON signal with a plurality of pulse signals at the time of turn-off, dVce / dt
Can be freely suppressed.

Further, since the overvoltage can be suppressed by controlling the low-voltage ON signal, it is not necessary to take any special measures against the low inductance of the main circuit.

(Second Embodiment) FIG. 3 is a circuit diagram showing a configuration of a main circuit in one arm unit of a power converter according to a second embodiment of the present invention.

This embodiment is a modification of the first embodiment, and aims to speed up the charging and discharging of the input capacitance of the gate. Specifically, this embodiment is several times to several tens times as large as normal. The resistance 63 in the second voltage applying unit 60 is set so that a gate current flows.
In this configuration, the values of L and the power supplies 61x and 62x, and the values of the positive power supply Ea1x, the negative power supply Eb1x, and the gate resistance Rg1L of the gate drive circuit are changed.

That is, the resistors 63L and Rg1L are connected to the first
The power supplies Ea1x, Eb1x, 61x, and 62x have lower resistance values than those of the first embodiment, and have higher voltages than those of the first embodiment.

With the above-described configuration, in addition to the effect of the first embodiment, a gate current several times to several tens times that of a normal gate current flows, and as shown in FIG. And the speed of switching of the main switching element can be increased.

In particular, the storage time t _stg is 1 / m of the normal drive.
In the converter or inverter in which the main switching element is configured as a single-phase or three-phase bridge, the relationship of the switching state with other phases can be easily grasped, and the dead time can be minimized. Output can be obtained.

(Third Embodiment) FIG. 5 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a third embodiment of the present invention.

This embodiment is a modification of the first embodiment, and aims to clamp an overvoltage instead of suppressing dVce / dt.
6 and the pulse generator 50 are omitted, and the first and second
The control of the switches 42 and 64 of the voltage applying units 40 and 60 is shared, and a holding circuit 71 and a reset signal generating circuit 72 are provided instead of the signal holding circuit 23.

Here, when the output of the overvoltage detection comparator 22 falls from the positive potential to the zero potential, the holding circuit 71 shifts the output signal from the zero potential to the positive potential side and supplies the output signal to the first AND circuit 24. When a reset signal is received from the reset signal generation circuit 71, the output signal is reset to a negative potential.

The reset signal generation circuit 72 supplies a reset signal to the holding circuit 71 when the output of the overvoltage detection comparator 22 rises from zero potential to positive potential.

With the above configuration, at the time of turn-on (time t0), as described above, the steady-state element voltage Vce in the off-state is held in the peak value detection circuit 18 (time t2), and the turn-on process is performed. Is completed (time t3).

On the other hand, at the time of turn-off (time t11
), When the overvoltage detection comparator 22 detects an overvoltage (time t12, FIG. 2D), the output signal of the holding circuit 71 is set to a positive potential (FIG. 2E), The output signal passes through the first AND circuit 24 (see FIG. 2).
(G)) The switches 42 and 64 of the first and second voltage applying units 40 and 60 are controlled to be in an on state, and the main switching element IGBT1 is partially turned on.

Thus, overvoltage is suppressed. Also,
When the overvoltage detecting comparator 22 detects the disappearance of the overvoltage (time t13), the holding circuit 71 is reset by the reset signal generation circuit 72 (FIG. 2F), and the output of the first AND circuit 24 becomes zero potential. The switches of the first and second voltage applying units 40 and 60 are controlled to be off, and the main switching element IGBT1 is turned off. This allows
The turn-off process is completed (time t14).

That is, according to the present embodiment, at the time of turn-off, the main switching element IGBT1 of overvoltage due to overshoot is guided to the half-on state (at time t1).
2 to t13), the occurrence of overvoltage can be suppressed.

(Fourth Embodiment) FIG. 7 is a circuit diagram showing a configuration of a main circuit in one arm unit of a power converter according to a fourth embodiment of the present invention.

This embodiment is a modification of the third embodiment, and aims at speeding up the charging and discharging of the input capacitance of the gate. Specifically, the present embodiment is several times to several tens times of the normal. The resistance 63 in the second voltage applying unit 60 is set so that a gate current flows.
In this configuration, the values of L and the power supplies 61x and 62x, and the values of the positive power supply Ea1x, the negative power supply Eb1x, and the gate resistance Rg1L of the gate drive circuit are changed.

That is, the resistors 63L and Rg1L are connected to the third
The power supplies Ea1x, Eb1x, 61x, and 62x have lower resistance values than those of the third embodiment, and have higher voltages than those of the third embodiment.

With the above configuration, in addition to the effect of the third embodiment, a gate current several times to several tens times that of a normal gate current flows. Therefore, as shown in FIG. And the speed of switching of the main switching element can be increased.

In particular, the accumulation time t _{stg is set} to 1 / m of the normal driving.
Since the minimum switching time can be doubled, switching with another phase can be easily matched in a converter or inverter in which the main switching element is configured as a single-phase or three-phase bridge.

(Fifth Embodiment) FIG. 9 is a circuit diagram showing a configuration of a main circuit in a unit of one arm of a power converter according to a fifth embodiment.

The present embodiment is a form in which the first and third embodiments are combined with each other, and aims at simultaneous suppression of dVce / dt and clamping of overvoltage. The dVce / dt suppression unit including the signal holding circuit 23, the first AND circuit 24, the pulse generation unit 50, the first and second voltage application units 40 and 60 in the first embodiment, and the holding circuit in the third embodiment In this configuration, a reset signal generation circuit 72, a first AND circuit 24, and an overvoltage clamp section including first and second voltage application sections 40 and 60 are electrically connected in parallel.

In the present embodiment, the first AND circuit 24 is connected to the first AND circuits 24a and 24a for convenience of the parallel configuration.
Two are provided as 4b. Further, the first and second voltage applying units 40 and 60 are shared by the dVce / dt suppressing unit and the overvoltage clamping unit. The output of the first AND circuit 24a of the dVce / dt suppression unit and the output of the first AND circuit 24b of the overvoltage clamp unit are OR circuits 7 respectively.
3 is connected to the switch 42 of the first voltage applying unit 40.

Similarly, the output of (the second AND circuit 56 of) the pulse generating section 50 of the dVce / dt suppressing section and the output of the first AND circuit 24b of the overvoltage clamping section are each 3A.
The switch 6 of the second voltage applying unit 60 via the ND circuit 74
4 is connected.

With the above configuration, as shown in FIG. 10, at the time of rising from immediately after the turn-off to the detection of the overvoltage (from t4), the effect of suppressing the dVce / dt by the dVce / dt suppressing unit of the first embodiment. (Time t6
To t7), at the time of overshoot from overvoltage detection to overvoltage disappearance, the overvoltage suppression effect of the overvoltage clamp unit of the third embodiment can be obtained (time t7 to t1).
3a).

That is, according to the present embodiment, the effects of the first and third embodiments can be simultaneously obtained.
By using both the suppression of dVce / dt and the suppression of overvoltage, electrical stress such as a main switching element and a load with low dVce / dt can be eliminated.

(Sixth Embodiment) FIG. 11 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a sixth embodiment.

This embodiment is a modification of the fourth embodiment, and shows a configuration of an arm unit in which main switching elements IGBT1 and IGBT2 are connected in series, and includes a plurality of main switching elements connected in series to each other. As for the IGBTs 1 and 2, an overvoltage clamp section is individually provided for each of the main switching elements IGBT1 and IGBT2. In addition, the subscript of the code | symbol has shown the equipment position.

With the above configuration, even when the main switching elements IGBT1 and IGBT2 are connected in series, as shown in FIG. 12, the clamp type snubber is applied using the CRD type snubber circuits S1 and S2. As in the case described above, overvoltage can be suppressed easily and effectively, and a compact, low-cost, high-reliability, high-voltage power converter can be realized.

(Other Embodiments) In the above embodiments, M
IGBT as main switching element of OS gate input type
However, the present invention is not limited to this, and instead of the IGBT, a power MOSFET, IGBT, SIT or I
Even if EGT or the like is used as the main switching element, the present invention can be implemented in the same manner and the same effect can be obtained.

The present invention can be variously modified and implemented without departing from the gist thereof.

[0113]

As described above, according to the present invention, it is possible to provide a power converter capable of reducing the snubber capacitor capacity and achieving a reduction in size and weight.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining an operation in the embodiment.

FIG. 3 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a second embodiment of the present invention.

FIG. 4 is a time chart for explaining an operation in the embodiment.

FIG. 5 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a third embodiment of the present invention.

FIG. 6 is a time chart for explaining the operation in the embodiment;

FIG. 7 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a fourth embodiment of the present invention.

FIG. 8 is a time chart for explaining the operation in the embodiment.

FIG. 9 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a fifth embodiment of the present invention.

FIG. 10 is a time chart for explaining the operation in the embodiment;

FIG. 11 is a circuit diagram showing a configuration of a main circuit in a unit of one arm in a power converter according to a sixth embodiment of the present invention.

FIG. 12 is a time chart for explaining the operation in the embodiment;

FIG. 13 is a circuit diagram showing a configuration of a power conversion device in which a conventional CRD type snubber circuit is applied to upper and lower arm main circuits.

FIG. 14 is a circuit diagram showing a configuration of a power converter in which a conventional clamp-type snubber circuit is applied to an upper / lower arm main circuit.

FIG. 15 is a circuit diagram showing a configuration of a conventional power converter in which main circuits with snubbers are connected in series and voltage-dividing resistors are connected in parallel.

[Explanation of symbols]

Ea1-2, Ea1x-2x, Eb1-2, Eb1x-
2x, 61, 61x, 62, 62x ... power supplies Sa1-2, Sb1-2, 18a, 32, 42, 63,
63L switch Rg1-2, R1-2, 11-12, Rb1-2,41
... Resistance IGBT1 ~ 2 ... Main switching element Df1-2 ... Reflux diode D1-2 ... Diode C1-2,18b ... Capacitor S1-2 ... CRD type snubber circuit 10 ... Gate voltage detection unit 13,21 ... Buffer amplifier 14 ... On / off Detection comparators 15, 34 Reference power supply 16 Turn-off detection unit 17 Turn-on detection unit 18 Peak value detection circuit 20 Element voltage detection unit 22 Overvoltage detection comparator 23 Signal holding circuit 24, 24a, 24b 1st AND circuit 30 ... Detection control unit 31 ... Inversion circuit 33 ... Comparator for OFF period detection 40 ... First voltage application unit 50 ... Pulse generation unit 51 ... Activation unit 52 ... Pulse number counter 53 ... Volume 54 ... V / F conversion Circuit 55 Setting switch 56 Second AND circuit 60 Second voltage applying unit 71 Holding circuit 72 Reset DOO signal generating circuit 73 ... OR circuit 74 ... first 3AND circuit

Claims (5)

[Claims] 1. A MOS gate input type switching element having a collector terminal, an emitter terminal, and a gate terminal, and a capacitor provided between the collector terminal and the emitter terminal for suppressing dV / dt during turn-off. A power conversion device comprising a CRD type snubber circuit having a lower capacity and a gate drive circuit for providing an ON signal or an OFF signal to the gate terminal, wherein an ON signal and an OFF signal applied to the gate terminal are detected. On / off detecting means for detecting the element voltage between the collector terminal and the emitter terminal, and comparing the element voltage detected by the element voltage detecting means with a predetermined voltage. An overvoltage detecting means for detecting occurrence of an overvoltage when the element voltage exceeds the predetermined voltage; When a change from the ON signal to the OFF signal is detected by the above, an ON signal having a lower voltage than the ON signal is supplied to the gate terminal, and when an overvoltage is detected by the overvoltage detecting means, the low voltage is supplied. And dV / dt suppressing means for stopping supply of the ON signal. 2. The power conversion device according to claim 1, wherein the over-voltage detection unit detects the over-voltage instead of the on / off detection unit and the dV / dt suppression unit, and outputs the voltage to the gate terminal. A power conversion device comprising overvoltage clamping means for supplying an ON signal having a lower voltage than the ON signal. 3. The power conversion device according to claim 1, wherein the gate drive circuit sets the gate to a negative potential having a higher absolute value than an ON signal as the OFF signal. A power converter, which is provided to terminals. 4. The power converter according to claim 1, further comprising: an overvoltage suppressing unit that supplies the low-voltage ON signal to the gate terminal when the overvoltage is detected by the overvoltage detecting unit. Power converter. 5. A MOS gate input type switching element having a collector terminal, an emitter terminal, and a gate terminal, and a capacitor provided between the collector terminal and the emitter terminal for suppressing dV / dt during turn-off. A CRD type snubber circuit having a lower capacitance and a gate drive circuit for supplying a positive potential ON signal or a negative potential OFF signal having an absolute value higher than the absolute value of the ON signal to the gate terminal. A power converter in which a plurality of arm structures are arranged so as to connect the switching elements in series with each other, wherein each of the arm structures is an element for detecting an element voltage between the collector terminal and the emitter terminal. Voltage detecting means, comparing the element voltage detected by the element voltage detecting means with a predetermined voltage, and comparing the detected element voltage with the predetermined voltage. An overvoltage detecting means for detecting occurrence of an overvoltage when the constant voltage is exceeded, and an overvoltage suppressing means for supplying an on signal of a lower voltage than the on signal to the gate terminal when the overvoltage is detected by the overvoltage detecting means. A power conversion device comprising: