GB2533677A

GB2533677A - Semiconductor drive unit and power converter using the same

Info

Publication number: GB2533677A
Application number: GB1517910.4A
Authority: GB
Inventors: Onda Kohei; Sakano Junichi; Ishikawa Katsumi; Kouno Yasuhiko; Konishide Masaomi
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2014-10-24
Filing date: 2015-10-09
Publication date: 2016-06-29
Anticipated expiration: 2035-10-09
Also published as: JP6362996B2; CN105553235B; GB201517910D0; GB2533677B; DE102015220594A1; JP2016086490A; CN105553235A

Abstract

A semiconductor drive unit for controlling the on/off state of a semiconductor switching element Q0, such as a MOSFET or IGBT, and providing overvoltage protection. The semiconductor drive unit comprises a control signal output stage for supplying a control signal to the gate terminal G of the switching element, a voltage clamp circuit connected between the input terminal of the switching element and its gate terminal, and a detection circuit for detecting a voltage between the drive unit output and the gate control terminal of the switching element. Feedback may also be provided by detecting the gate control terminal current or charge. The output impedance of the control signal stage may initially be increased during the turn off period but is then lowered based on the feedback signal SF from the detection circuit, where the given comparison voltage may be set based on Vge at the end of the Miller effect period.

Description

SEMICONDUCTOR DRIVE UNIT AND POWER CONVERTER USING

THE SAME

Background of the Invention

Field of the Invention

The present invention relates to a semiconductor drive unit equipped with an overvoltage protecting function, and a power converter using such semiconductor drive unit.

Description of the Related Art

Inverters and other power converters realize power conversion by the switching operation of a semiconductor switching element. A voltage-driven semiconductor element such as a MOS-FET or an IGBT is widely used as a typical example of such semiconductor switching element. Especially, an IGBT enabling high-speed switching and capable of controlling a large amount of power is used in a wide technical area, from small-capacity inverters for household electric appliances to large-scale inverters for railway vehicles and the like.

In order to control such semiconductor switching element, a semiconductor drive unit is required. In general, a drive unit of a voltage driven semiconductor has a function to control the state of conduction of the element by applying voltage to a gate of the semiconductor switching element. Further, the semiconductor drive unit has a function to prevent overvoltage of the operating semiconductor switching element.

Fig. 10 shows a prior art example of a drive unit for an IGBT module composed of an IGBT and a diode. Based on a gate signal, the module applies an appropriate voltage to a gate G of an IGBT 1, and controls a collector current lc conducted between a collector P and an emitter N of the IGBT 1.

Here, gate resistances 6 and 7 are for adjusting a rate of change of voltage Vge between the gate G and an emitter E by restricting a current Irg flowing to the gate G. Thereby, a switching rate of the IGBT 1, that is, the rate of change of the collector current lc and the rate of change of voltage Vce between a collector C and the emitter E, can be specified appropriately.

A system in which a voltage clamp element 3 such as a constant voltage diode is connected between the collector C and the gate G of the IGBT 1 is adopted widely as an overvoltage preventing function. According to such system, when collector voltage becomes excessive, such as when the IGBT 1 is turned off, the constant voltage diode yields and current flows to the gate, turning the IGBT on transiently and clamping the collector voltage constantly. Generally, overvoltage protection diode 9 is provided between gate -emitter to prevent overvoltage of the gate of the IGBT 1.

Fig. 11 shows a waveform diagram of a collector current lc, a collector -emitter voltage Vce, a gate current Irg and a gate -emitter voltage Vge when the IGBT is turned off in the configuration of Fig. 10. During the period of time when the collector -emitter voltage Vce and the collector current lc of the IGBT is transited, a turn-off loss occurs in the IGBT. Further, during this transition period, a terrace called a mirror period is known to appear in the gate voltage waveform.

Fig. 12 is a waveform diagram of the respective currents and voltages of a case where a collector surge voltage of the IGBT becomes excessive and the voltage clamp element 3 performs clamp operation. During the period of time when overvoltage occurs between collector -emitter, the voltage clamp element 3 connected between the collector and the gate breaks down, by which current Id flows to the clamp circuit, and by having the gate voltage raised to or over an on-threshold voltage Vth, the IGBT is turned on, and the overvoltage between the collector and the emitter can be prevented. On the other hand, since the turn-off action period is elongated by the voltage clamp, a side effect occurs where the turn-off loss is increased.

Here, if the off-gate voltage of the semiconductor drive unit is represented by Vm and the off-gate resistance is represented by Rgl, the clamp circuit current Id must satisfy the following relationship.

Id (Vth -Vm) / Rgl... (Expression 1) Accordingly, the increase of the off-gate resistance Rg1 contributes to reducing the clamp current Id, and therefore, contributes to enhancing the clamping effect. On the other hand, it causes further increase of turn-off loss.

Summary of Invention

As a different method for enhancing the clamping effect, Japanese Patent Application Laid-Open Publication No. 2005-328668 (Patent Literature 1) shows a method for maintaining an output voltage of a gate drive circuit to a positive voltage smaller than a threshold voltage Vth during a given period of time within the switching operation period. According to the disclosed method for maintaining the gate voltage to a positive voltage, the positive and negative power supplies of a drive circuit are connected via a resistance, so that there is a need to maintain the voltage by high impedance in order to prevent excessive heating of the resistance. Therefore, the fluctuation of potential when noise is mixed into the gate becomes significant, and a risk occurs of having the gate turned on erroneously and generating excessive loss. Further, this method is a feed-forward control in which the period for maintaining the above-mentioned positive voltage is determined in advance, but since the necessary clamp period Tcl (refer to Fig. 12) changes according to the state of the generated surge, there is a need to ensure a sufficient margin when setting the clamp period Td. Therefore, such method has a drawback in that excessive turn-off delay and increased loss occurs.

On the other hand, Japanese Patent Application Laid-Open Publication No. 2013-126278 (Patent Literature 2) discloses a method of delaying switching operation and suppressing surge voltage by increasing the off-resistance of a next output stage circuit when a clamp circuit is operated. According to such method, it is expected that a feedback control detecting the operation of the clamp circuit enables to optimize the period of time for increasing the off resistance, and suppress the excessive increase of turn-off loss. However, according to this method, there is a need to lay a feedback wiring from the clamp circuit to the output stage circuit. Therefore, not only the number of wirings required to connect the semiconductor drive unit and the IGBT is increased, but noise is superposed in the laid wirings, so there is fear that the output stage circuit may operate erroneously, possibly causing problems such as increase of turn-off loss and short circuit of arms.

In order to solve the problems mentioned above, the present invention provides a semiconductor drive unit for controlling an on-off state of a semiconductor switching element, the semiconductor drive unit comprising a control signal output stage circuit for transmitting a control signal to a gate control terminal of the switching element, a voltage clamp circuit connected between an input terminal and the gate control terminal of the switching element, and a detection circuit for detecting a voltage between an output terminal and the gate control terminal of the switching element or a gate control terminal current, wherein the control signal output stage circuit lowers an impedance of an output stage of the control signal output stage circuit based on a result of detection of the detection circuit during a turn-off period of the semiconductor switching element.

The semiconductor switching element according to the present invention can be applied to elements such as IGBTs and MOSFETs, wherein the input terminal corresponds to a collector terminal of the IGBT and a drain terminal of the MOSFET, and the output terminal corresponds to an emitter terminal of the IGBT and a source terminal of the MOSFET.

According to the present invention, the timing for switching the impedance of the control circuit is detected using the voltage or the current of the control terminal, so that control corresponding to clamp operation period Tcl can be realized, the increase of turn-off loss can be suppressed to a minimum, and the length of the signal line from the point of detection of voltage or current to the impedance switching section can be shortened to suppress the overlapping of noise in the signal lines.

Brief Description of the Drawings

Fig. 1 is a block diagram illustrating a basic configuration of a semiconductor drive unit according to Embodiment I of the present invention.

Fig. 2 is a first operation waveform diagram of a semiconductor drive unit according to Embodiment 1 of the present invention.

Fig. 3 is a second operation waveform diagram of the semiconductor drive unit according to Embodiment 1 of the present invention.

Fig. 4 is a block diagram illustrating a specific example of an output stage circuit of the semiconductor drive unit according to Embodiment 1 of the present invention.

Fig. 5 is a block diagram according to a first specific example of a voltage clamp circuit of the semiconductor drive unit according to Embodiment 1 of the present invention.

Fig. 6 is a block diagram illustrating a second specific example of a voltage clamp circuit of the semiconductor drive unit according to Embodiment 1 of the present invention.

Fig. 7 is a block diagram illustrating a third specific example of a voltage clamp circuit of the semiconductor drive unit according to Embodiment 1 of the present invention.

Fig. 8 is a block diagram illustrating a basic configuration of a semiconductor drive unit according to Embodiment 2 of the present invention.

Fig. 9 is a block diagram illustrating a basic configuration of a power converter according to Embodiment 3 of the present invention.

Fig. 10 is a block diagram showing a prior art configuration of a semiconductor drive circuit having an active clamp function.

Fig. 11 is a turn-off waveform diagram of a semiconductor switching element according to a prior art configuration.

Fig. 12 is a turn-off waveform diagram of a semiconductor switching element according to a prior art configuration, specifically showing a case where an active clamp function of a semiconductor drive unit has been activated due to high surge voltage.

Description of Preferred Embodiments

Now, preferred embodiments 1 through 3 for carrying out the present invention will be described with reference to the drawings. In the following description, an IGBT is taken as an example of a semiconductor, but the present invention is not restricted to the example, and can be applied to drive units of other general semiconductors.

Embodiment 1 <Configuration of semiconductor drive unit> Fig. 1 is a block diagram showing a basic configuration of a semiconductor drive unit according to Embodiment 1 of the present invention. The present embodiment assumes a case where both a gate control terminal G of an IGBT and a gate control terminal Gd of the semiconductor drive unit, and an emitter control terminal Ea of the IGBT and an emitter control terminal Ed of the semiconductor drive unit, are respectively connected via a twisted wire and the like. A voltage clamp circuit is connected between a collector sense terminal Ca and a gate terminal G at an IGBT module side, so as to prevent overvoltage of an IGBT electrode. Further, the gate control terminal G and the emitter control terminal Ea of the IGBT are connected via avalanche diodes Dz1 and Dz2, which are constant voltage diodes. The avalanche diodes Dz1 and Dz2 conduct current from the gate control terminal to the emitter control terminal when the gate voltage exceeds a given voltage, so as to prevent the voltage output from the semiconductor drive unit and the voltage output from the voltage clamp circuit from exceeding a withstand voltage of a gate of a semiconductor switching element. The semiconductor drive unit causes an output stage circuit capable of varying impedance to apply a voltage to an IGBT gate in response to a drive command SIN received from a command section. According to a method for varying the impedance of the output stage circuit adopted in the present embodiment, the impedance is controlled based on a result of detection of the voltage detection circuit monitoring the gate-emitter voltage.

<Operation of Semiconductor Drive Unit> Fig. 2 is an operation waveform diagram of a semiconductor drive unit according to a first operation example of Embodiment 1 of the present invention. When a gate-emitter voltage Vge is lowered by receiving a gate-off drive command SIN, a collector voltage Vce starts to increase (t1). Thereafter, during interruption of a high current and the like, when the collector voltage is further increased and the collector-gate voltage reaches an operation voltage level of the voltage clamp circuit (t2), current is flown from the collector side to the gate side via the voltage clamp circuit. Thereby, the gate voltage is raised to a gate threshold voltage Vth or higher, the IGBT is turned on, and the collector voltage is clamped to a steady voltage Vcl. Here, since the impedance of the output stage circuit is set in advance to a high value Z1, the clamp current required to satisfy Expression 1 can be suppressed to a small value.

Thereafter, when the surge is moderated (t3), the gate voltage is lowered by the reduction of the clamp current. When the voltage detection circuit detects that a mirror period has ended and the gate -emitter voltage has been lowered to a specified voltage value or smaller (t4 of Fig. 4), the voltage detection circuit generates a gate determination signal SF and transmits the signal to a control signal output stage circuit. Based on this gate determination signal SF, the output stage circuit lowers a gate output impedance to Z2, and accelerates the turn-off action. Here, the specified voltage value should be set to the gate-emitter voltage of the time when the mirror period is ended.

Fig. 3 is an operation waveform diagram of a semiconductor drive unit according to a second operation example of Embodiment 1 of the present invention. The present example differs from Fig. 2 in that an impedance Z3 of the gate output stage prior to ti when the gate voltage Vge starts to reduce is smaller than impedance Z1 during the clamp period. In other words, in the present example, the impedance is raised from 73 from 74 at a timing t1 described above, and the impedance is lowered from 74 to 75 at a timing t4 described above. The timing for lowering the impedance can be similarly realized using the above-mentioned voltage detection circuit, so that the detailed description thereof is omitted. In the present example, Z3 is set to a value greater than Z5 and smaller than Z4.

Fig. 3 has illustrated an example where three impedances Z3 through Z5 are switched linearly, but it is clear that the present invention can be applied to multi-stage control, nonlinear control, low-current control and so on. According to a specific example of performing multi-stage control, the voltage detection circuit has multiple specified voltage values, and each time the voltage detection value Vge between the emitter terminal and the gate control terminal becomes equal to or smaller than each given voltage value, gate determination signals are output for multiple times to the control signal output stage circuit, and the control signal output stage circuit switches the impedance of the output stage of the control signal output stage circuit for multiple times based on the gate determination signals received for multiple times from the detection circuit, to thereby lower the impedance gradually.

<Effect of Embodiment 1> The semiconductor drive unit provided by the present invention enables to set a high output stage impedance during clamp operation, so that the gate voltage can be started immediately during clamp operation. Therefore, the current Id of the voltage clamp circuit in charge of performing overvoltage protection of the semiconductor drive unit can be reduced, and the circuit can be downsized due to the application of a small-sized clamp element. Moreover, the rising of collector voltage during the clamp period can be suppressed by enhancing the clamp function, the clamp voltage can be set even higher, so that the frequency of occurrence of active clamp operation can be reduced, and the self-heating of the switching element can be reduced.

Even further, the timing for lowering the output stage impedance of the semiconductor drive unit can be accommodated to a clamp operation period Tcl based on the result of detection of the gate voltage, so that the increase of turn-off loss can be suppressed to a minimum amount. The prior art techniques adopted a feed-forward control causing increase of turn-off loss (Patent Literature 1) or feedback control requiring an excessive detection signal line (Patent Literature 2), whereas the present invention adopts a quasi-feedback control for indirectly detecting the operation of the voltage clamp circuit using an existing gate wiring connecting the IGBT module and the semiconductor drive unit, according to which the operation of the voltage clamp circuit can be detected indirectly at a position closer to the semiconductor drive unit, so that the present invention enables to shorten the length of the detection signal wire compared to the aforementioned prior art techniques and to enable stable control being less influenced by noise.

<Specific Example of Output Stage Circuit of Embodiment 1> A specific example of an output stage circuit according to Embodiment 1 will be described with reference to Fig. 4. The output stage circuit is composed of two output stages Ti and 12, three gate resistances Rg1, Rg2 and Rg3, a speed-up capacitor Cg1, and a resistance switching control unit switching the output resistance based on the gate determination signal SF.

The output stage Ti outputs either a high-pressure side voltage Vp or a low-pressure side voltage Vm based on the received drive command SIN. The output side of the output stage Ti is connected via a resistance Rg1 and a resistance Rg2 connected in series to a gate control terminal Gd. A speed-up capacitor Cg1 is connected in parallel to the resistance Rg1. Further, the resistance switch control unit operates the output stage T2 based on the received gate determination signal SF, and either outputs the low-pressure side voltage Vm or breaks the circuit. The output side of the output stage T2 is connected via a resistance Rg3 to the gate control terminal Gd. Further, the midpoint potential of two voltage sources Vp and Vm is connected to an emitter control terminal Ed.

During the time before ti in Fig. 3, the gate current bypasses the seed-up capacitor Cg1 connected in parallel to Rg1, so that the off-gate resistance of the output stage Ti will be Rg2 (73). Now, by selecting the capacity of the speed-up capacitor Cg1 so that charging is ended at timing t1 when the mirror period is reached, the off-gate resistance of t1 and thereafter in Fig. 3 is increased to [Rg1 + Rg2] (Z4). On the other hand, when the mirror period is ended and the gate voltage is lowered (t4 of Fig. 3), if the gate determination signal SF showing that the gate voltage is reduced to a specified value or smaller is entered from the voltage detection circuit, the resistance switching control unit turns on the output stage 12, connects the low-pressure side voltage Vm and the resistance Rg3, forms a parallel circuit formed of Rg3 and Rg1 + Rg2, and lowers the off-gate resistance to 75. Here, Rg3 is smaller than Rg1 + Rg2, so that turn-off after time t4 is accelerated to suppress increase of switching loss.

In Fig. 4, a configuration equipped with the seed-up capacitor Cg1 has been described so as to realize the second operation example shown in Fig. 3, but by providing a configuration excluding the speed-up capacitor Cg1 from Fig. 2, the first operation example illustrated in Fig. 2 can be realized.

Here, the off-gate resistance (Z1, Z4) determined by the resistance Rg1 + Rg2 should be set to a resistance value equal to or greater than "agate threshold -voltage Vth] -[low-pressure side voltage Vm]) / [current Id of voltage clamp circuit]", and preferably set to the same level as this resistance value.

<First Specific Example of Voltage Clamp Circuit of Embodiment 1> Fig. 5 shows a first specific example of a voltage clamp circuit according to the present embodiment. This circuit is configured by connecting a plurality of avalanche diodes Dz3 through Dz8 in series, and has the simplest configuration.

<Second Specific Example of Voltage Clamp Circuit of Embodiment 1> Fig. 6 shows a second specific example of a voltage clamp circuit according to the present embodiment. This circuit is configured by further connecting a capacitor Cz1 in series to the multiple avalanche diodes Dz3 through Dz8 connected in series. By adding a capacitor for cutting DC currents to the arrangement of Fig. 5, even if the collector voltage Vce exceeds the clamp voltage VcI by the increase of power source voltage of the main circuit, it becomes possible to prevent current from flowing persistently to the voltage clamp circuit.

<Third Specific Example of Voltage Clamp Circuit of Embodiment 1> Fig. 7 shows a third specific example of a voltage clamp circuit according to the present embodiment. This circuit is formed by connecting a MOSFET in parallel with a portion of the plurality of avalanche diodes Dz3 through Dz8 connected in series. The MOSFET gate is connected between a connecting point of the plurality of avalanche diodes and the gate control terminal, and constitutes a circuit where a portion of the avalanche diodes is bypassed by the MOSFET when the voltage or current of the avalanche diodes connected in parallel is increased and exceeds the on voltage of the MOSFET. In this specific example, even in a case where the collector voltage Vce continues to increase even if the voltage clamp circuit is operated, the MOSFET is turned on to lower the clamp voltage VcI and prevent overvoltage of the element.

Embodiment 2 Fig. 8 is a block diagram showing a basic configuration of a semiconductor drive unit according to Embodiment 2 of the present invention. The present embodiment differs from Embodiment 1 in that control is performed based on the result of detection of a current detection circuit monitoring the gate current as the method for changing the impedance of the output stage circuit. The specific examples of the control sequence and circuit are the same as Embodiment 1, so that they will not be described. When the absolute value of the gate current is reduced and becomes equal to or smaller than a specified current value (t4 of Fig. 3), the current detection circuit outputs a gate determination signal SF. As another example, a configuration can be adopted where the circuit outputs the gate determination signal SF when an absolute value of a gate charge Qg having integrated the detected gate currents becomes equal to or smaller than a specified value. The specified current value or the specified electric charge described here should be set to an absolute value of the gate current or gate charge of the time when the mirror period ends.

According to the present embodiment, similar to Embodiment 1, the timing for lowering the output stage impedance of the semiconductor drive unit can be adapted to the clamp operation period Tcl based on the result of detection of the gate current, so that the increase of turn-off loss can be suppressed to a minimum value.

As a specific example of performing multi-stage control, the current detection circuit is equipped with a plurality of specified current values, and each time the current detection value Irg of the gate control terminal or the integrated value Zg thereof becomes equal to or smaller than the respective given values, the circuit outputs gate determination signals for multiple times to the control signal output stage circuit, and the control signal output stage circuit switches the impedance of the output stage of the control signal output stage circuit for multiple times based on the gate determination signals received for multiple times from the detection circuit, that the impedance is gradually lowered.

Embodiment 3 Fig. 9 is a view showing a power converter to which the semiconductor drive unit of the present invention is applied as Embodiment 3. A power converter according to Embodiment 3 applies the semiconductor drive unit according to aforementioned Embodiments 1 or 2 as a drive unit of a semiconductor switching element in a power converter.

As shown in Fig. 9, a power converter 600 according to Embodiment 3 is equipped with semiconductor switching elements 011 through 016, diodes D11 through D16, diodes Dll through D16, semiconductor drive units GD11 through GD16, voltage clamp circuits AC11 through AC16, and a high-order logical unit L1 generating drive command signals, which are signals for controlling switching operation, to semiconductor switching elements Q11 through 016. The power converter 600 according to Embodiment 3 is an inverter device for converting DC power from a DC power source 601 of voltage Vdc to AC power.

Further, the semiconductor switching elements Q11 through 016 in Embodiment 3 useIGBTs, but are not restricted to IGBTs, and they can be configured using other switching elements, such as MOSFETs.

The power converter 600 has three sets of upper and lower arms connected in series between positive and negative terminals of the DC power source 601 connecting the two semiconductor switching elements (011 and 012, 013 and 014, and 015 and 016) with their polarities aligned. Further, diodes Dll through D16 for reflowing a load current are respectively connected with reverse polarity and in parallel with the semiconductor switching element between the emitter and the collector of the respective semiconductor switching elements Q11 through 016. Moreover, voltage clamp circuits AC11 through AC16 are connected between the collector sense terminals and the gate terminals of the respective semiconductor switching elements Q11 through 016. Semiconductor drive units GD11 through GD16 for outputting switching drive command signals are respectively connected to the gate control terminal. Further, the connecting points of the two semiconductor switching elements (Q11 and 012, 013 and 014, and 015 and 016) connected in series each server as AC output terminals, and are connected to a three-phase AC motor M1 being the load.

The power converter 600 controls the switching operation of the semiconductor switching elements 011 through 016 via semiconductor drive units GD11 through GD16 by the high-order logical unit L1, and supplies AC power to the three-phase AC motor M1 connected to the AC terminal. The power converter 600 generates drive command signals to the respective semiconductor switching elements Q11 through Q16 via the high-order logical unit Ll, and performs power conversion operation by transmitting the drive command signals through the semiconductor drive units GD11 through GD16 to the gate terminals (control terminals) of the semiconductor switching elements Q11 through Q16.

Now, when surge voltage occurs during a large current interruption and the like in the power converter 600, the gate of the semiconductor switching element is turned on by the voltage clamp circuit, according to which the collector voltage can be clamped constantly. When the clamp operation is ended, the change of gate voltage or gate current is detected immediately, the impedance of the output stage circuit is lowered, so as to suppress the increase of turn-off loss can be suppressed.

Embodiment 3 has illustrated an inverter device as an example of having the semiconductor drive unit of the present invention applied to a power converter, but the present invention is not restricted to such example, and can be applied to other power converts, such as DC-DC converters and AC-DC converters.

Claims

CLAIMS1. A semiconductor drive unit for controlling an on-off state of a semiconductor switching element, the semiconductor drive unit comprising: a control signal output stage circuit for transmitting a control signal to a gate control terminal of the switching element; a voltage clamp circuit connected between an input terminal and the gate control terminal of the switching element; and a detection circuit for detecting a voltage between an output terminal and the gate control terminal of the switching element or a gate control terminal current; wherein the control signal output stage circuit lowers an impedance of an output stage of the control signal output stage circuit based on a result of detection of the detection circuit during a turn-off period of the semiconductor switching element.
2. The semiconductor drive unit according to Claim 1, wherein the control signal output stage circuit increases the impedance of an output stage of the control signal output stage circuit during a turn-off period of the semiconductor switching element, and thereafter, based on a detection result of the detection circuit, reduces the impedance of the output stage of the control signal output stage circuit.
3. The semiconductor drive unit according to Claim 2, wherein the control signal output stage circuit has a resistor connected in series with the output stage of the control signal output signal stage circuit, and a speed-up capacitor connected in parallel with the resistor; and by having the speed-up capacitor charged during a turn-off period of the semiconductor switching element, the resistor increases the impedance of the output stage of the control signal output stage circuit.
4. The semiconductor drive unit according to any one of Claims 1 through 3, wherein when a voltage detection value between an output terminal of the switching element and the gate control terminal becomes equal to or smaller than a given voltage value, or when an absolute value of a current detection value of the gate control terminal becomes equal to or smaller than a given current value, or when an integrated value of the current detection value becomes equal to or smaller than a given electric charge, the detection circuit outputs a gate determination signal to the control signal output stage circuit; and when the gate determination signal is received, the control signal output stage circuit lowers the impedance of the output stage of the control signal output stage circuit.
5. The semiconductor drive unit according to Claim 4, wherein the given voltage value is set to a voltage value between the output terminal and the gate control terminal of the switching element when a mirror period during turnoff is ended; the given current value is set to a current absolute value of the gate control terminal when the mirror period during turn-off is ended; and the given electric charge is set to a gate electric charge of the switching element when the mirror period during turn-off is ended.
6. The semiconductor drive unit according to Claim 4 or Claim 5, wherein the detection circuit has multiple values of each of the given voltage value or the given current value or the given electric charge, and each time a voltage detection value between the output terminal and the gate control terminal of the switching element becomes equal to or smaller than the respective given voltage values, the detection circuit outputs the gate determination signal for multiple times to the control signal output stage circuit, or each time the absolute value of the current detection value of the gate control terminal becomes equal to or smaller than the respective given current values, the detection circuit outputs the gate determination signal for multiple times to the control signal output stage circuit, or each time the integrated value of the current detection value of the gate control terminal becomes equal to or smaller than the respective given electric charges, the detection circuit outputs the gate determination signal for multiple times to the control signal output stage circuit; and based on the gate determination signals received for multiple times from the detection circuit, the control signal output stage circuit switches the impedance of the output stage of the control signal output stage circuit for multiple times and gradually lowers the impedance.wherein
7. The semiconductor drive unit according to any one of Claims 1 through 6, the voltage clamp circuit has a voltage clamp diode.wherein
8. The semiconductor drive unit according to any one of Claims 1 through 7, the voltage clamp circuit has a voltage clamp diode, and a capacitor connected in series with the voltage clamp diode.
9. The semiconductor drive unit according to any one of Claims 1 through 8, wherein the voltage clamp circuit has a plurality of voltage clamp diodes connected in series, and a switching element connected in parallel with a portion of the plurality of voltage clamp diodes and turned on and off based on a current or a voltage of the voltage clamp diode.
10. A power converter comprising: a plurality of upper and lower arms formed by connecting a plurality of semiconductor switching elements in series; and a plurality of semiconductor drive units for controlling on and off of each of the plurality of semiconductor switching elements, wherein the plurality of semiconductor drive units are configured of the semiconductor drive unit according to any one of Claims 1 through 9.