JPH1075164A - Gate drive circuit for voltage control-type switching element - Google Patents

Gate drive circuit for voltage control-type switching element

Info

Publication number
JPH1075164A
JPH1075164A JP8231545A JP23154596A JPH1075164A JP H1075164 A JPH1075164 A JP H1075164A JP 8231545 A JP8231545 A JP 8231545A JP 23154596 A JP23154596 A JP 23154596A JP H1075164 A JPH1075164 A JP H1075164A
Authority
JP
Japan
Prior art keywords
turn
gate
circuit
voltage
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8231545A
Other languages
Japanese (ja)
Other versions
JP3564893B2 (en
Inventor
Akifumi Ichihara
昌文 市原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP23154596A priority Critical patent/JP3564893B2/en
Publication of JPH1075164A publication Critical patent/JPH1075164A/en
Application granted granted Critical
Publication of JP3564893B2 publication Critical patent/JP3564893B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide the gate driving circuit of a voltage control-type switching element in a simple constitution which can be turned off with a small loss and a low surge voltage. SOLUTION: The gate signal supplying circuit of an IGBT1 constituting a main circuit of a power converter is provided as a duplex constitution of two circuits. The gate signal supplying circuit is composed of a switching circuit for control 3-1 (3-2) for switching a gate voltage for turn-on and a gate voltage for turn-off, and a gate resistance 2-1 (2-2). At the time of turn-off, after an turn-off operation of one switching circuit for control 3-1, a turn-off operation of the other switching circuit for control 3-2 is executed after the lapse of a fixed time. Thus, a gate charge decreasing speed just after the start of a turn-off when the surge voltage is the maximum can be slowed, and the gate charge decreasing speed can be increased after a circulating diode has been turned on, and the main cause of the generation of a surge voltage is reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電圧制御形スイッ
チング素子(IGBTなど)のゲート駆動回路、特にタ
ーンオフ時のサージ電圧低減技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit for a voltage-controlled switching element (such as an IGBT), and more particularly to a technique for reducing a surge voltage at turn-off.

【0002】[0002]

【従来の技術】電圧制御形スイッチング素子、例えばI
GBTを用いた電力変換器では、IGBTがターンオフ
する際に生じるサージ電圧が使用電圧の低下やスイッチ
ング損失の増加などの問題を引き起こす。このサージ電
圧を軽減するためには、以下のような対策が取り入れら
れている。
2. Description of the Related Art A voltage-controlled switching element such as I
In a power converter using a GBT, a surge voltage generated when the IGBT is turned off causes problems such as a decrease in operating voltage and an increase in switching loss. In order to reduce the surge voltage, the following measures are taken.

【0003】(A)スイッチング速度を遅くする.IG
BTのゲート周辺回路を図6に、これに相当するゲート
駆動回路を図7にそれぞれ示す。図中、1はIGBT、
2はゲート抵抗、3はターンオン・ターンオフ制御用ス
イッチング回路、4はターンオン用電源(電圧+Vc
c)、5はターンオフ用電源(電圧−Vee)である。
ターンオン・ターンオフ制御用スイッチング回路3は、
例えばトランジスタTR1,TR2を直列に接続し、そ
の接続点にゲート抵抗2を、ベースに+Vcc接続ドラ
イバDR1,−Vee接続ドライバDR2をそれぞれ接
続した構成としている。
(A) To reduce the switching speed. IG
FIG. 6 shows a BT gate peripheral circuit, and FIG. 7 shows a corresponding gate drive circuit. In the figure, 1 is an IGBT,
2 is a gate resistor, 3 is a switching circuit for turn-on / turn-off control, and 4 is a power supply for turn-on (voltage + Vc).
c) Reference numeral 5 denotes a turn-off power supply (voltage -Vee).
The switching circuit 3 for turn-on / turn-off control includes:
For example, transistors TR1 and TR2 are connected in series, a gate resistor 2 is connected to the connection point, and a + Vcc connection driver DR1 and a -Vee connection driver DR2 are connected to the base.

【0004】IGBT1のゲートは、駆動するドライバ
側から見ると、コンデンサ(図6に示すゲート容量C
g)として見える。これは、ゲート抵抗2の抵抗値Rg
を小さくすればコンデンサの電荷を素早く出し入れでき
ることを意味する。従って、抵抗値Rgを小さくすれば
スイッチング速度が速くなり、逆に、抵抗値Rgを大き
くすればスイッチング速度は遅くなる。即ち、ゲート抵
抗2によってIGBT1のスイッチング速度を調整する
ことができる。
When viewed from the driving driver side, the gate of the IGBT 1 is a capacitor (gate capacitance C shown in FIG. 6).
g). This is the resistance value Rg of the gate resistor 2.
A smaller value means that the charge of the capacitor can be quickly taken in and out. Therefore, the switching speed increases as the resistance value Rg decreases, and conversely, the switching speed decreases as the resistance value Rg increases. That is, the switching speed of the IGBT 1 can be adjusted by the gate resistor 2.

【0005】サージ電圧はIGBT1が急速にターンオ
フすることによって生じる電圧であるため、ゲート抵抗
2を大きくすること、つまりスイッチング速度を遅くす
ることにより、サージ電圧を低く抑えられる。
Since the surge voltage is a voltage generated when the IGBT 1 is rapidly turned off, the surge voltage can be suppressed low by increasing the gate resistance 2, that is, by reducing the switching speed.

【0006】(B)サージ電圧を吸収するスナバ回路を
付加する.サージ電圧はIGBT主回路の浮遊インダク
タンス(配線インダクタンス)に蓄えられたエネルギー
によって発生する。よって、IGBTにスナバ回路を付
設し、このスナバ回路にエネルギーを吸収すれば、サー
ジ電圧を低く抑えることができる。図8、図9に代表的
なスナバ回路を示す。
(B) A snubber circuit for absorbing a surge voltage is added. The surge voltage is generated by the energy stored in the floating inductance (wiring inductance) of the IGBT main circuit. Therefore, if a snubber circuit is attached to the IGBT and energy is absorbed in the snubber circuit, the surge voltage can be suppressed low. 8 and 9 show typical snubber circuits.

【0007】図8のスナバ回路21は抵抗Rsとコンデ
ンサCsを直列に接続した構成、図9のスナバ回路22
は過渡的な等価抵抗を小さくするために抵抗Rs´と並
列にダイオードDsを接続した構成であり、IGBT1
に並列に接続している。
The snubber circuit 21 shown in FIG. 8 has a configuration in which a resistor Rs and a capacitor Cs are connected in series, and the snubber circuit 22 shown in FIG.
Is a configuration in which a diode Ds is connected in parallel with the resistor Rs' to reduce the transient equivalent resistance.
Are connected in parallel.

【0008】[0008]

【発明が解決しようとする課題】上記の対策には次のよ
うな問題点がある。
The above measures have the following problems.

【0009】(A)の問題点 スイッチング速度を遅くすると、サージ電圧は低下する
が、スイッチングに要する時間が長くなる。スイッチン
グ時間の増加は、スイッチング素子(IGBT1)のタ
ーンオフ損失の増加につながるため、素子の冷却に問題
が移行するが、素子の冷却は特性上肝要であり、むやみ
にスイッチング速度を遅くすることはできない。
Problem (A) When the switching speed is reduced, the surge voltage is reduced, but the time required for switching is increased. Since an increase in the switching time leads to an increase in the turn-off loss of the switching element (IGBT1), the problem shifts to the cooling of the element. However, the cooling of the element is important in characteristics, and the switching speed cannot be unnecessarily reduced. .

【0010】(B)の問題点 スナバ回路21(または22)を付設した場合は、回路
構成が複雑になり、部品点数、工数の増加につながる。
また、最近のIGBTのスイッチング速度はかなり高速
であるため、図8(図9)に示すスナバ回路21(2
2)自体の持つ配線インダクタンスLdを無視すること
(スナバ回路の配線長を短くするのには限界がある)が
できず、スナバ回路の効果には限界がある。特に、IG
BTの場合は十分な効果が期待できない。
Problem (B) When the snubber circuit 21 (or 22) is additionally provided, the circuit configuration becomes complicated, which leads to an increase in the number of parts and man-hours.
Also, since the switching speed of recent IGBTs is quite high, the snubber circuit 21 (2) shown in FIG.
2) The wiring inductance Ld of the device itself cannot be ignored (there is no limit in shortening the wiring length of the snubber circuit), and the effect of the snubber circuit is limited. In particular, IG
In the case of BT, a sufficient effect cannot be expected.

【0011】本発明は上記事情に鑑みてなされたもの
で、ゲート信号供給回路を多重化することにより、簡単
な回路構成で、小損失、低サージ電圧でターンオフでき
る電圧制御形スイッチング素子のゲート駆動回路を提供
することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances. By multiplexing gate signal supply circuits, a gate drive of a voltage control type switching element which can be turned off with a small circuit loss and a low surge voltage with a simple circuit configuration. It is intended to provide a circuit.

【0012】また本発明は、ゲート信号供給回路の2重
化の代わりにターンオフ初期専用回路を追設することに
より、比較的簡単な回路構成で、小損失、低サージ電圧
でターンオフできる電圧制御形スイッチング素子のゲー
ト駆動回路を提供することを目的とする。
Further, the present invention provides a voltage control type which can be turned off with a small loss and low surge voltage with a relatively simple circuit configuration by adding a dedicated circuit for initial turn-off instead of duplicating the gate signal supply circuit. It is an object to provide a gate drive circuit for a switching element.

【0013】[0013]

【課題を解決するための手段】本発明は、ターンオン用
ゲート電圧とターンオフ用ゲート電圧をスイッチング回
路及びゲート抵抗を介して電圧制御形スイッチング素子
のゲートに選択的に供給するゲート信号供給回路を複数
設け、ターンオフに際しては一つをターンオフ初期から
の動作、他を所定時間後の動作とするようにしたことを
特徴とする。
According to the present invention, there are provided a plurality of gate signal supply circuits for selectively supplying a turn-on gate voltage and a turn-off gate voltage to a gate of a voltage-controlled switching element via a switching circuit and a gate resistor. At the time of turn-off, one operation is performed from an early stage of the turn-off, and the other operation is performed after a predetermined time.

【0014】また本発明は、ターンオン用ゲート電圧と
ターンオフ用ゲート電圧をスイッチング回路及びゲート
抵抗を介して電圧制御形スイッチング素子のゲートに選
択的に供給する電圧制御形スイッチング素子のゲート駆
動回路において、スイッチング回路の共通端子とGnd
レベルの間に放電路を有するターンオフ初期専用回路を
設け、ターンオフに際しては、まずターンオフ初期専用
回路のみを動作させ、所定時間後にスイッチング回路の
ターンオフ動作及びターンオフ初期専用回路のオフ動作
を行うようにしたことを特徴とする。
According to the present invention, there is provided a gate drive circuit of a voltage-controlled switching element for selectively supplying a turn-on gate voltage and a turn-off gate voltage to a gate of the voltage-controlled switching element via a switching circuit and a gate resistor. Common terminal of switching circuit and Gnd
A turn-off initial dedicated circuit having a discharge path between levels is provided, and at the time of turn-off, first, only the turn-off initial dedicated circuit is operated, and after a predetermined time, the switching circuit is turned off and the turn-off initial dedicated circuit is turned off. It is characterized by the following.

【0015】[0015]

【発明の実施の形態】図1に本発明の一実施形態を示
す。図中、1はIGBT、2−1及び2−2はゲート抵
抗、3−1及び3−2はターンオン・ターンオフ制御用
スイッチング回路であり、IGBT1のゲート信号供給
回路を2回路としている。
FIG. 1 shows an embodiment of the present invention. In the figure, reference numeral 1 denotes an IGBT, 2-1 and 2-2 denote gate resistors, 3-1 and 3-2 denote turn-on / turn-off control switching circuits, and two gate signal supply circuits of the IGBT 1 are provided.

【0016】次に、動作について述べる。IGBT1を
ターンオフさせる場合には、まず、一方のゲート信号供
給回路、例えば制御用スイッチング回路3−1側のみを
動作させる。つまり、制御用スイッチング回路3−1を
負側電源に切り換える。この状態では、他方のゲート信
号供給回路(制御用スイッチング回路3−2側)はター
ンオン状態のままであり、電源電圧を±Vg、ゲート抵
抗の値をRgとすると、電圧状態は図2(a)に示すよ
うになる。これをIGBT1から見ると、図2(b)に
示す回路と等価になる。即ち、IGBT1のゲートにR
g/2の抵抗を介して0(V)が加わる。
Next, the operation will be described. When turning off the IGBT 1, first, only one gate signal supply circuit, for example, only the control switching circuit 3-1 is operated. That is, the control switching circuit 3-1 is switched to the negative power supply. In this state, the other gate signal supply circuit (on the side of the control switching circuit 3-2) remains turned on, and when the power supply voltage is ± Vg and the value of the gate resistance is Rg, the voltage state is as shown in FIG. ). When this is viewed from the IGBT 1, it becomes equivalent to the circuit shown in FIG. That is, R is applied to the gate of IGBT1.
0 (V) is applied through a resistor of g / 2.

【0017】このため、IGBT1のゲートの初期の電
荷減少速度は、ゲート信号供給回路が一つ(図8参照)
で、ゲート抵抗の値Rgを大きめに設定することによっ
てサージ電圧を低減している場合と同等(電圧半分、抵
抗半分)となる。従って、サージ電圧も同等の電圧が生
じる。そして、ある程度時間が経過してから(還流ダイ
オードなどがターンオンしてサージ電圧発生の要因が減
少してから)他方の制御用スイッチング回路3−2もタ
ーンオフ駆動の動作をする。両ゲート信号供給回路でタ
ーンオフ駆動をするようになると、電荷減少速度は速く
なり、スイッチング速度は図8の場合よりも高速にな
る。これにより、同等のサージ電圧でスイッチング速度
を高速化できる。
For this reason, the initial charge reduction speed of the gate of the IGBT 1 is determined by one gate signal supply circuit (see FIG. 8).
This is equivalent to the case where the surge voltage is reduced by setting the value Rg of the gate resistance to be relatively large (half the voltage and half the resistance). Therefore, the same voltage occurs as the surge voltage. Then, after a certain period of time has passed (after the freewheel diode and the like are turned on and the cause of surge voltage generation is reduced), the other control switching circuit 3-2 also performs a turn-off driving operation. When turn-off driving is performed by both gate signal supply circuits, the charge reduction speed becomes faster, and the switching speed becomes higher than that in the case of FIG. As a result, the switching speed can be increased at the same surge voltage.

【0018】なお、上記実施形態ではゲート信号供給回
路を2回路(2重)としたが、3回路以上に多重化する
こともできる。その場合、回路数やゲート抵抗の値を適
宜選定すれば、きめ細かいターンオフ時のゲート電荷減
少速度調節が可能となり、より効果的な(低スイッチン
グ損失、低サージ電圧の)スイッチング動作が期待でき
る。
In the above-described embodiment, the gate signal supply circuit has two circuits (double), but the gate signal supply circuit can be multiplexed to three or more circuits. In this case, by appropriately selecting the number of circuits and the value of the gate resistance, it is possible to finely adjust the gate charge reduction speed at the time of turn-off, and it is possible to expect more effective (low switching loss, low surge voltage) switching operation.

【0019】図3に本発明の他の実施形態を示す。図
中、1はIGBT、2はゲート抵抗、3はターンオン・
ターンオフ制御用スイッチング回路、4はターンオン用
電源(電圧+Vcc)、5はターンオフ用電源(電圧−
Vee)である。ターンオン・ターンオフ制御用スイッ
チング回路3は、例えばトランジスタTR1,TR2を
直列に接続し、その接続点にゲート抵抗2を、ベースに
+Vcc接続ドライバDR1,−Vee接続ドライバD
R2をそれぞれ接続した構成としている。6はターンオ
フ初期専用回路で、Gnd接続ドライバDR3と、この
出力でオン、オフするトランジスタTR3により構成
し、トランジスタTR3のコレクタをゲート抵抗2、エ
ミッタをターンオン用電源4とターンオフ用電源5の接
続点(Gnd点)にそれぞれ接続している。
FIG. 3 shows another embodiment of the present invention. In the figure, 1 is an IGBT, 2 is a gate resistor, 3 is turn-on.
Switching circuit for turn-off control, 4 is power supply for turn-on (voltage + Vcc), 5 is power supply for turn-off (voltage-
Vee). The turn-on / off control switching circuit 3 includes, for example, transistors TR1 and TR2 connected in series, a gate resistor 2 at the connection point thereof, a + Vcc connection driver DR1 at the base, and a -Vee connection driver D at the base.
R2 is connected to each other. Reference numeral 6 denotes a turn-off initial dedicated circuit, which comprises a Gnd connection driver DR3, and a transistor TR3 which is turned on / off by this output. The collector of the transistor TR3 is a gate resistor 2, and the emitter is a connection point between the turn-on power supply 4 and the turn-off power supply 5. (Gnd point).

【0020】ターンオフ初期専用回路6は、ドライバ出
力の電位がGndレベルより高い場合に電荷を引き抜く
働きがある。また、Vcc接続ドライバDR1と−Ve
e接続ドライバDR2は、独立して駆動できるようにし
ている(通常のドライバでは、互いに反転動作するよう
になっている)。
The turn-off initial dedicated circuit 6 has a function of extracting electric charges when the potential of the driver output is higher than the Gnd level. Also, the Vcc connection driver DR1 and -Ve
The e-connection driver DR2 is configured to be able to be driven independently (in a normal driver, the operations are inverted with each other).

【0021】次に、動作について述べる。ターンオン時
にはターンオフ初期専用回路6は駆動せず、通常のゲー
トドライバと同じようにVcc接続ドライバDR1の部
分で同じように駆動する。このため、ターンオン時の特
性は通常のドライバと同等である。
Next, the operation will be described. At the time of turn-on, the turn-off initial dedicated circuit 6 is not driven, but is driven in the same manner as the normal gate driver at the Vcc connection driver DR1. Therefore, the characteristics at the time of turn-on are the same as those of a normal driver.

【0022】ターンオフ時は、+Vcc接続ドライバD
R1の部分をオフにした後、ターンオフ初期専用回路6
をオンにする。この状態では、図4に太線(矢印aを併
記)で示すようにIGBT1のゲートはゲート抵抗2及
びトランジスタTR3を通してGndレベルに接続され
る。通常のゲートドライバでは最初から−Vee電源に
接続することになるため、この段階でのゲート電荷の引
き抜き力は本実施形態の方が弱く、ゆっくりとスイッチ
ングすることになる。これによって、サージ電圧は低減
される。
At the time of turn-off, the + Vcc connection driver D
After turning off the R1 part, the turn-off initial dedicated circuit 6
Turn on. In this state, the gate of the IGBT 1 is connected to the Gnd level through the gate resistor 2 and the transistor TR3, as shown by the bold line in FIG. In a normal gate driver, the connection to the -Vee power supply is performed from the beginning, and the gate charge extraction force at this stage is weaker in the present embodiment, and the switching is performed slowly. Thereby, the surge voltage is reduced.

【0023】ある程度ターンオフが進み、サージ電圧の
発生要因が減少した段階で、図5に太線(矢印bを併
記)で示すように−Vee接続ドライバDR2の部分を
オンにする。同時に、ターンオフ初期専用回路6をオフ
にする。これにより、これ以後のスイッチング速度は通
常のドライバと同等となる。
At a stage where the turn-off has progressed to some extent and the generation factor of the surge voltage has been reduced, the portion of the -Vee connection driver DR2 is turned on as shown by the thick line (also indicated by the arrow b) in FIG. At the same time, the turn-off initial dedicated circuit 6 is turned off. As a result, the switching speed thereafter becomes equal to that of a normal driver.

【0024】従って、ゲート抵抗2を同じ値とした場合
は、本実施形態ではサージ電圧を低減できてもスイッチ
ング速度はターンオフ初期専用回路6の動作期間の影響
で遅くなるが、サージ電圧が最も生じるスイッチング直
後のスイッチング速度を遅くできる分、ゲート抵抗2を
小さめの値にすることができる。Vcc=Veeの場
合、ゲート抵抗2は略半分の値にすることが可能であ
り、その場合はターンオフ初期専用回路6の動作による
スイッチング時間の増加が、その後の−Vee接続ドラ
イバDR2の動作期間での低減によって十分に補われ
る。
Therefore, when the gate resistor 2 has the same value, in this embodiment, even if the surge voltage can be reduced, the switching speed becomes slow due to the operation period of the turn-off initial dedicated circuit 6, but the surge voltage occurs most. Since the switching speed immediately after switching can be reduced, the gate resistance 2 can be set to a smaller value. When Vcc = Vee, the gate resistance 2 can be reduced to approximately half the value. In this case, an increase in the switching time due to the operation of the turn-off initial dedicated circuit 6 increases in the subsequent operation period of the -Vee connection driver DR2. Is sufficiently compensated for by the reduction of

【0025】[0025]

【発明の効果】以上のように本発明によれば、最もサー
ジ電圧が高くなるターンオフ開始直後のゲート電荷減少
速度を遅くし、還流ダイオードなどがターンオンしてサ
ージ電圧発生要因が減少してからゲート電荷減少速度を
速くするゲート動作としたので、低スイッチング損失、
低サージ電圧でのスイッチング動作が可能となる。ま
た、ドライバ構成は少々複雑になっても、適切なドライ
バ構成の採用によりスナバ回路の大幅な削減、ひいては
スナバレス化が可能であり、装置全体としては大いに有
利となる。
As described above, according to the present invention, the gate charge decreasing speed immediately after the start of turn-off, at which the surge voltage becomes the highest, is slowed down, and after the freewheeling diode is turned on to reduce the surge voltage generation factor, the gate voltage is reduced. Low switching loss and low gate loss
Switching operation at a low surge voltage becomes possible. Further, even if the driver configuration is slightly complicated, the snubber circuit can be greatly reduced and the snubberless can be achieved by adopting an appropriate driver configuration, which is very advantageous as a whole device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態を示す回路構成図。FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【図2】一実施形態における一方のゲート信号供給回路
のみをターンオフ動作させた時の動作説明図で、(a)
は回路電圧状態を示す回路図、(b)はIGBT側から
見た等価回路図。
FIG. 2 is an operation explanatory diagram when only one gate signal supply circuit in one embodiment is turned off, and FIG.
FIG. 4 is a circuit diagram showing a circuit voltage state, and FIG. 4B is an equivalent circuit diagram viewed from the IGBT side.

【図3】本発明の他の実施形態を示す回路構成図。FIG. 3 is a circuit diagram showing another embodiment of the present invention.

【図4】他の実施形態におけるターンオフ初期専用回路
を動作させた時の動作状況を説明するための回路図。
FIG. 4 is a circuit diagram for explaining an operation state when a turn-off initial dedicated circuit according to another embodiment is operated.

【図5】他の実施形態における−Vee接続ドライバを
動作させた時の動作状況を説明するための回路図。
FIG. 5 is a circuit diagram illustrating an operation state when a −Vee connection driver according to another embodiment is operated.

【図6】従来の一般的なゲート周辺回路を示す回路構成
図。
FIG. 6 is a circuit configuration diagram showing a conventional general gate peripheral circuit.

【図7】図6のゲート周辺回路に相当するゲート駆動回
路を示す回路構成図。
FIG. 7 is a circuit diagram showing a gate drive circuit corresponding to the gate peripheral circuit of FIG. 6;

【図8】代表的なスナバ回路の一例を示す回路図。FIG. 8 is a circuit diagram illustrating an example of a typical snubber circuit.

【図9】代表的なスナバ回路の他の例を示す回路図。FIG. 9 is a circuit diagram showing another example of a typical snubber circuit.

【符号の説明】[Explanation of symbols]

1…IGBT 2、2−1、2−2…ゲート抵抗 3、3−1、3−2…ターンオン・ターンオフ制御用ス
イッチング回路 4…ターンオン用電源 5…ターンオフ用電源 6…ターンオフ初期専用回路 TR1〜TR3…トランジスタ DR1〜DR3…ドライバ
DESCRIPTION OF SYMBOLS 1 ... IGBT 2, 2-1 and 2-2 ... Gate resistance 3, 3-1 and 3-2 ... Switching circuit for turn-on / turn-off control 4 .... Power supply for turn-on 5 .... Power supply for turn-off 6 .... Dedicated circuit for initial turn-off TR1 TR3: Transistors DR1 to DR3: Driver

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 // H02H 9/04 H03K 17/56 Z Continued on the front page (51) Int.Cl. 6 Identification number Agency reference number FI Technical display location // H02H 9/04 H03K 17/56 Z

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ターンオン用ゲート電圧とターンオフ用
ゲート電圧をスイッチング回路及びゲート抵抗を介して
電圧制御形スイッチング素子のゲートに選択的に供給す
るゲート信号供給回路を複数設け、ターンオフに際して
は一つをターンオフ初期からの動作、他を所定時間後の
動作とするようにしたことを特徴とする電圧制御形スイ
ッチング素子のゲート駆動回路。
1. A plurality of gate signal supply circuits for selectively supplying a turn-on gate voltage and a turn-off gate voltage to a gate of a voltage-controlled switching element via a switching circuit and a gate resistor are provided. A gate drive circuit for a voltage-controlled switching element, wherein the operation is performed from an early stage of turn-off and the other operation is performed after a predetermined time.
【請求項2】 ターンオン用ゲート電圧とターンオフ用
ゲート電圧をスイッチング回路及びゲート抵抗を介して
電圧制御形スイッチング素子のゲートに選択的に供給す
る電圧制御形スイッチング素子のゲート駆動回路におい
て、スイッチング回路の共通端子とGndレベルの間に
放電路を有するターンオフ初期専用回路を設け、ターン
オフに際しては、まずターンオフ初期専用回路のみを動
作させ、所定時間後にスイッチング回路のターンオフ動
作及びターンオフ初期専用回路のオフ動作を行うように
したことを特徴とする電圧制御形スイッチング素子のゲ
ート駆動回路。
2. A gate drive circuit for a voltage-controlled switching element, wherein a gate voltage for a turn-on and a gate voltage for a turn-off are selectively supplied to a gate of the voltage-controlled switching element via a switching circuit and a gate resistor. A turn-off initial dedicated circuit having a discharge path between the common terminal and the Gnd level is provided. At the time of turn-off, only the turn-off initial dedicated circuit is operated first, and after a predetermined time, the switching circuit is turned off and the turn-off initial dedicated circuit is turned off. A gate drive circuit for a voltage-controlled switching element, wherein the gate drive circuit comprises:
JP23154596A 1996-09-02 1996-09-02 Gate drive circuit for voltage controlled switching element Expired - Lifetime JP3564893B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23154596A JP3564893B2 (en) 1996-09-02 1996-09-02 Gate drive circuit for voltage controlled switching element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23154596A JP3564893B2 (en) 1996-09-02 1996-09-02 Gate drive circuit for voltage controlled switching element

Publications (2)

Publication Number Publication Date
JPH1075164A true JPH1075164A (en) 1998-03-17
JP3564893B2 JP3564893B2 (en) 2004-09-15

Family

ID=16925182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23154596A Expired - Lifetime JP3564893B2 (en) 1996-09-02 1996-09-02 Gate drive circuit for voltage controlled switching element

Country Status (1)

Country Link
JP (1) JP3564893B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11308084A (en) * 1998-04-20 1999-11-05 Meidensha Corp Gate drive circuit of switching element
EP0978942A2 (en) * 1998-08-05 2000-02-09 Kabushiki Kaisha Toshiba Gate circuit
JP2000295834A (en) * 1999-04-05 2000-10-20 Toshiba Corp Power converter
US7148673B2 (en) 2002-10-25 2006-12-12 Marvell World Trade Ltd. Method and apparatus including low loss DC/DC converter
JP2008177853A (en) * 2007-01-18 2008-07-31 Toyota Central R&D Labs Inc Driving circuit of power semiconductor element
KR100912294B1 (en) 2006-09-01 2009-08-17 인터내쇼널 렉티파이어 코포레이션 High voltage gate driver ic with multi-function gating
JP2012070045A (en) * 2010-09-21 2012-04-05 Yazaki Corp Load driving device
JP2012080739A (en) * 2010-10-06 2012-04-19 Rohm Co Ltd Switching control apparatus, power conversion apparatus and integrated circuit
KR20170009362A (en) * 2015-07-16 2017-01-25 엘에스산전 주식회사 Driving circuit of switching device for electric power control
EP3343637A1 (en) 2016-12-27 2018-07-04 Renesas Electronics Corporation Semiconductor device and power converter
JP2018186619A (en) * 2017-04-25 2018-11-22 三菱電機株式会社 Power semiconductor device and power semiconductor drive system
JP2019193047A (en) * 2018-04-23 2019-10-31 トヨタ自動車株式会社 Switching element control circuit
WO2021177098A1 (en) * 2020-03-03 2021-09-10 株式会社デンソー Gate driving device
WO2023112139A1 (en) * 2021-12-14 2023-06-22 日立Astemo株式会社 Driving circuit and control method for driving circuit

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11308084A (en) * 1998-04-20 1999-11-05 Meidensha Corp Gate drive circuit of switching element
EP0978942A2 (en) * 1998-08-05 2000-02-09 Kabushiki Kaisha Toshiba Gate circuit
EP0978942A3 (en) * 1998-08-05 2003-10-01 Kabushiki Kaisha Toshiba Gate circuit
JP2000295834A (en) * 1999-04-05 2000-10-20 Toshiba Corp Power converter
US7148673B2 (en) 2002-10-25 2006-12-12 Marvell World Trade Ltd. Method and apparatus including low loss DC/DC converter
US7161342B2 (en) 2002-10-25 2007-01-09 Marvell World Trade Ltd. Low loss DC/DC converter
US7271573B2 (en) 2002-10-25 2007-09-18 Marvell World Trade Ltd. Low loss DC/DC converter including a multi-level controller that applies a monotonic sequence of voltage levels
KR100912294B1 (en) 2006-09-01 2009-08-17 인터내쇼널 렉티파이어 코포레이션 High voltage gate driver ic with multi-function gating
JP2008177853A (en) * 2007-01-18 2008-07-31 Toyota Central R&D Labs Inc Driving circuit of power semiconductor element
US7847604B2 (en) 2007-01-18 2010-12-07 Toyota Jidosha Kabushiki Kaisha Driving circuit for power semiconductor element including controlling circuit that provides control when detected voltage reaches predetermined voltage
JP2012070045A (en) * 2010-09-21 2012-04-05 Yazaki Corp Load driving device
JP2012080739A (en) * 2010-10-06 2012-04-19 Rohm Co Ltd Switching control apparatus, power conversion apparatus and integrated circuit
KR20170009362A (en) * 2015-07-16 2017-01-25 엘에스산전 주식회사 Driving circuit of switching device for electric power control
JP2017028990A (en) * 2015-07-16 2017-02-02 エルエス産電株式会社Lsis Co., Ltd. Driving circuit of switching element for electric power control
EP3343637A1 (en) 2016-12-27 2018-07-04 Renesas Electronics Corporation Semiconductor device and power converter
JP2018186619A (en) * 2017-04-25 2018-11-22 三菱電機株式会社 Power semiconductor device and power semiconductor drive system
JP2019193047A (en) * 2018-04-23 2019-10-31 トヨタ自動車株式会社 Switching element control circuit
WO2021177098A1 (en) * 2020-03-03 2021-09-10 株式会社デンソー Gate driving device
JP2021141661A (en) * 2020-03-03 2021-09-16 株式会社デンソー Gate driving device
WO2023112139A1 (en) * 2021-12-14 2023-06-22 日立Astemo株式会社 Driving circuit and control method for driving circuit

Also Published As

Publication number Publication date
JP3564893B2 (en) 2004-09-15

Similar Documents

Publication Publication Date Title
JP4113436B2 (en) Gate drive device
US5281862A (en) Power MOSFET driver with cross-conduction current reduction
JP3141613B2 (en) Method and circuit for driving voltage-driven element
EP2015453B1 (en) Drive circuit for voltage driven switching element
JP4938326B2 (en) Motor drive circuit
US20050017788A1 (en) Semiconductor apparatus
JP4313658B2 (en) Inverter circuit
JPH1075164A (en) Gate drive circuit for voltage control-type switching element
JPH0818423A (en) Control circuit for semiconductor device
JP4779549B2 (en) A gate driving circuit of a voltage driven semiconductor element.
EP0790698B1 (en) Method of driving power converter
JP2777307B2 (en) Short circuit protection circuit
JP3430878B2 (en) MOS gate type element driving circuit
JP3532377B2 (en) Gate drive circuit for voltage driven switch element
JPH11205112A (en) High voltage resistant power integrated circuit
JP2913699B2 (en) Drive circuit for voltage-driven semiconductor devices
EP0468209B1 (en) Single-drive level shifter, with low dynamic impedance
JP2000014127A (en) Gate drive circuit for voltage-driven semiconductor device
US7215093B2 (en) Motor drive circuit and motor drive method that can positively perform a brake operation
JPH11234108A (en) Switching device for switching inductive load
KR930015346A (en) Bipolar Complementary Metal Oxide Semiconductor (BICMOS) Output Buffer Noise Reduction Circuit
JP2001119926A (en) Gate driver of voltage-drive type semiconductor element
JP3340786B2 (en) Power transistor overcurrent protection circuit
EP0533354A1 (en) Driver circuit
JP3764259B2 (en) Inverter device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040217

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040419

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040518

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040531

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090618

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090618

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100618

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110618

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110618

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120618

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130618

Year of fee payment: 9

EXPY Cancellation because of completion of term