JP3129960B2 - Resin sealing structure of bare chip IC on FPC and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a module for obtaining reliability by sealing with a resin, particularly to a resin sealing structure of a bare chip IC on an FPC, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a measure for preventing bubbles of a sealing resin in a resin sealing structure of a bare chip IC on an FPC is as follows. For printed wiring boards), consider the optimum value based on the application position and application conditions (application speed, application amount, resin temperature, etc.) where air bubbles are unlikely to occur, improve the viscosity of the resin material itself, and achieve high fluidity Was using things. However, these measures could not completely prevent the generation of bubbles.

As a next countermeasure, a defoaming step of a sealing resin has been adopted. FIG. 6 shows a conventional bare chip IC on an FPC.
3 shows a defoaming step in the sealing resin. An electronic component module 50 in which a semiconductor component such as a bare chip IC is mounted on a substrate constituting a circuit such as an FPC and a resin is applied thereto is placed in a desiccator or a completely sealed temperature bath 51 before the resin or the resin is cured, and connected to the bath. By operating the vacuum pump 52, the defoaming operation is performed. Reference numeral 53 denotes the exhaust at that time.

[0004] In short, the defoaming device is composed of a temperature bath that can be completely sealed and a vacuum pump connected to the temperature bath, and the air in the temperature bath is discharged by operating the vacuum pump. Since the resin is not cured by being put into this device, bubbles in the sealing resin are discharged to the outside of the resin due to a decrease in the pressure of the air in the tank by the vacuum pump. Furthermore, the efficiency of defoaming can be improved by raising the temperature in the tank, but such a troublesome defoaming step has been employed.

An electronic component module 50 in which a semiconductor component such as a bare chip IC is mounted on a substrate constituting a circuit such as an FPC and resin is applied will be described with reference to FIG. FIG.
(A) is a plan view before mounting, in which a connection lead (ILB, inner lead bond) 55 to a bare chip IC of an IC mounting portion is mounted on an FPC (flexible printed circuit board) 54 so as to face the bump of the bare chip IC. It is arranged in the direction. FIG. 7B is a cross-sectional view before mounting. After a copper foil 57 on a polyimide film 56, which is a base material of the FPC, is patterned by etching, a resist agent 58 is formed thereon by printing and cured to prepare.

FIG. 7 (c) is a plan view after mounting, and FIG.
Is a FPC, 55 is a connection lead (ILB) for an IC mounting portion on the FPC, and 59 is a bare chip IC.
FIG. 7D is a cross-sectional view after mounting. A copper foil 57 is provided on a polyimide film 56 which is a base material of the FPC, and a resist agent 58 is printed thereon.
0 is press-contacted with the copper foil 57 to achieve electrical conduction.
The space between the bare chip IC and the FPC is filled with a sealing resin material 61.

[0007]

However, the conventional resin sealing structure of the bare chip IC on the FPC has the following problems.

In a bare chip IC mounted on an FPC board having a circuit configuration, the FPC board and the bare chip IC are electrically and mechanically connected via a connection pump of several tens μm to one hundred and several tens μm. Therefore, reliability is significantly affected by external force and environmental conditions.

Therefore, in order to protect the connection between the bare chip IC and the substrate, a resin material such as epoxy resin is applied to the space between the bare chip IC and the FPC and cured.
This is to ensure connection reliability. However, when bubbles are contained in the resin, cracks may occur in the sealing resin due to expansion and contraction of the bubbles depending on various conditions.
The sealing resin is also injected into the lower portion of the bare chip IC. In particular, the bubbles generated in this portion push up the bare chip IC upward due to expansion, and a stress in the peeling direction acts on the connection portion, leading to disconnection. In general, bubbles generated in the sealing resin were concentrated in this portion. In the conventional FPC, even if there is no flat portion under the mounted bare chip IC, the resin flowing between the FPC and the bare chip IC is:
The penetration speed varies depending on the bump pitch and the bump shape of the bare chip IC. This variation has caused the flow of the resin to be turbulent, which has been a factor of generating bubbles.

Next, generation of air bubbles in a resin sealing step of a bare chip IC mounted on an FPC in a conventional example will be described with reference to FIG.

FIG. 8A shows a flow of resin sealing in a case where the FPC surface is smooth and there is no bump on the bare chip IC (unrealistic). The area where the bare chip IC 59 is located is indicated by a dotted line, and the sealing resin 61 is injected from the resin application position 62, and the sealing resin is transmitted from the applied position to the periphery of the bare chip IC. It can be divided into those that flow due to surface tension during FPC. And
The traveling wavefront 63 of the flow of the sealing resin material has some irregularities. However, when the FPC surface is smooth and the bare chip IC has no bumps, air bubbles are not involved. 55 indicates FPC.

FIG. 8B shows how a sealing resin flows between the surface of a conventional FPC and a bare chip IC in the actual case. The area where the bare chip IC 59 is located is indicated by a dotted line, and the sealing resin 61 is injected from the resin application position 62, is affected by the bumps 64 of the bare chip IC 59, and has a traveling wavefront 63 of the flow (permeation) of the sealing resin. Has severe irregularities. 55 indicates FPC.

FIG. 8 (c) shows the flow of the sealing resin when the time further elapses in FIG. 8 (b). 55 is FPC, 61
Indicates a sealing resin material, 62 indicates a resin application position, and is affected by the bumps 64 of the bare chip IC 59, the traveling wavefront 63 of the flow of the sealing resin material becomes very uneven, and the sealing resin Flow becomes turbulent and eventually bubbles 65
Will be interposed. Also, since the shape and size pitch of the connection bumps of the bare chip IC are not standardized by each manufacturer, the generation probability of bubbles is not constant. FIG. 8D shows a cross section taken along the line AA ′ of FIG. 8C.

In the prior art, the air bubbles generated in the sealing resin incorporate a defoaming step of forcibly discharging air bubbles by a vacuum pump, so that the number of operation items is large and the production efficiency is greatly affected. I was Furthermore, there are products that cannot completely remove bubbles even through this defoaming step, and electronic component modules containing bubbles have been selected and removed by a microscopic appearance inspection.

[0015]

In order to solve the above-mentioned problems, the present invention features a mechanism that does not remove bubbles generated in the sealing resin but does not generate bubbles when applying the resin. A groove structure is formed on the surface of the FPC surface to prevent the resin flowing into the substrate due to surface tension from becoming turbulent and trapping air bubbles at a position below the bare chip IC of the substrate (FPC) on which the bare chip IC is mounted. Is to do. In the groove structure according to the present invention, a plurality of structures are formed in a direction parallel to, or radial to, or opposite to the direction in which the resin is filled from the position where the resin is applied. Thereby, bare chip I
Since the resin flowing between C and the FPC has the groove structure according to the present invention, the amount of resin flowing in each groove is made uniform, and the resin can be filled without causing turbulent flow. The shape of the groove structure of the present invention,
The most suitable structure (parallel type, radial type, reverse radial type, combination type, etc.) is selected in consideration of the conditions such as the bump shape and bump pitch of the bare chip IC to be mounted.

According to the first aspect of the present invention, in the resin sealing structure of the bare chip IC on the FPC , the circuit pattern is formed on the base material.
Bare chip I on FPC printed with resist material
C is mounted on the FPC to seal the bare chip IC with resin
In the resin-encapsulated structure of the bare chip IC described above, the resist is formed on the FPC area corresponding to the lower part of the bare chip IC to be mounted.
Formed of an organic material that forms
Parallel to the direction of filling from the position
A plurality of groove structures are provided in a reverse radial manner . Further, the base on the FPC according to claim 2 of the present invention.
The resin-sealed structure of Achip IC is a circuit pattern
Is formed on the FPC on which the resist is printed.
FP that mounts a chip IC and seals the bare chip IC with resin
In the resin sealing structure of the bare chip IC on C,
On the FPC area corresponding to the lower part of the bare chip IC
Formed of a metal material forming a circuit pattern,
Parallel or radial to the filling direction from the application position
Or characterized by the provision of multiple groove structures in a reverse radial pattern.
Is what you do.

[0017]

[0018]

Further, the resin sealing structure of the bare chip IC on FPC according to claim 3 of the present invention, the groove structures, the
Metal material forming circuit pattern and organic material forming resist agent
And a material .

Furthermore, the manufacturing method according to claim 4 resin sealing the bare chip IC on FPC according to the present invention, times on the substrate
A bare chip IC is mounted on an FPC on which a circuit pattern is formed and a resist agent is printed , and the bare chip IC is sealed with a resin.
Manufacturing method of resin sealing bare chip IC on FPC to be stopped
In the method, the resist agent is printed on the FPC area corresponding to the lower part of the bare chip IC to be mounted at the same time as the resist agent is printed.
From the position where the sealing resin is applied
Parallel or radial or counter-radial
Form several groove structures and seal at the application position of the sealing resin
It is characterized by applying and filling a resin .
The bare chip I on the FPC according to claim 5 of the present invention.
The method of manufacturing resin encapsulation of C is that a circuit pattern is formed on a substrate.
Bare chip I on FPC printed with resist material
C is mounted on the FPC to seal the bare chip IC with resin
In a manufacturing method for resin-sealing bare chip ICs,
On the FPC area, which is the lower part of the bare chip IC to be mounted
And circuit pattern etching at the same time
From the position where the sealing resin is applied
Parallel to the filling direction or radial or counter-radial
A plurality of groove structures are formed and sealed at the application position of the sealing resin.
It is characterized by applying and filling a stop resin.
You. A beech on an FPC according to claim 6 of the present invention.
The manufacturing method of the resin sealing of the IC
Same as the printing of the metal material forming the circuit pattern and the resist agent
Composed of organic material that forms resist material sometimes formed
It is characterized by doing.

The groove structure according to the present invention can reduce variation in permeation of the resin flowing between the bare chip IC and the FPC, suppress generation of turbulence, and prevent entrapment of air bubbles. That is, the groove structure according to the present invention constitutes one groove for several connection bumps of the bare chip IC in parallel, radially or reverse radially with respect to the direction in which the resin flows from the resin application position. As the number of grooves increases, the generation of turbulence can be suppressed. However, if the number of grooves is too large, the surface tension effect is attenuated, and conversely, the sealing resin does not flow. Therefore, the number of grooves needs to be adjusted. When the sealing resin is applied, the resin flows into the lower portion of the bare chip IC via the connection bump of the bare chip IC. Furthermore, since the sealing resin flows along the groove structure of the present invention, even when bumps are present and the dispersion of permeation occurs, the turbulence of the flow of the sealing resin is reduced and bubbles are not included. Filling will take place.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 5 are diagrams relating to an embodiment of the present invention.

FIG. 1 shows an FP according to an embodiment of the present invention.
It is explanatory drawing at the time of using the resist agent which is an organic material in the resin sealing structure of the bare chip IC on C, and its manufacturing method as a material of a groove structure, (a) Top view, (b) Sectional drawing, (c) FIG. 4 shows a cross-sectional view when a sealing resin is filled.

In the plan view of FIG. 1A, the connection lead (ILB) 1 on which the bare chip IC 7 is mounted on the FPC 2 is shown.
Are arranged in four directions so as to face the bumps of the bare chip IC, and the groove structure 10 according to the present invention is formed on the FPC. Reference numeral 3 denotes a resin application position. In the sectional view of FIG. 1B, a copper foil circuit pattern (about 18 μm thick) is formed on a polyimide film (about 25 μm thick) 4 which is a base material of the FPC.
m) 5 and a resist agent (a material is a polyimide-based ink, a thickness of about 5 μm) 6 is printed. And
The FPC 2 includes a polyimide film 4, a copper foil circuit pattern 5, and a resist agent 6.

FIG. 1C is a sectional view of a resin sealing structure in which a bare chip IC is mounted on an FPC.

Polyimide film 4 which is a base material of FPC
A copper foil circuit pattern 5 is provided thereon, a resist agent 6 is printed thereon, and gold bumps (about several tens μm to one hundred and several tens μm) 8 connected on the bare chip IC 7 are pressed against the copper foil circuit pattern 5 to be electrically connected. Electrical continuity is achieved. The groove structure 10 of the present invention is provided on the FPC region corresponding to the lower part of the bare chip IC to be mounted, and the space between the bare chip IC and the FPC is filled with a sealing resin 9. As the sealing resin material 9, a thermosetting epoxy resin material having a low viscosity (about 3 poise to about 50 poise) was used. A method of forming a groove structure by using a resist is to form a copper foil circuit pattern 5 on a polyimide film 4 serving as a base material of an FPC by etching, and then form and harden a resist 6 as shown in a plan view by printing. At the time of resist printing, the groove structure of the present invention can be formed at the same time, and an additional processing step and a dedicated device are unnecessary. If the sealing resin is applied from the position 3, the resin is uniformly filled around and below the bare chip IC by the groove structure 10, and the generation of bubbles can be suppressed.

The groove structure 1 of the present invention by printing a resist agent
In the case where 0s are simultaneously formed, since the thickness of one printing is about 5 μm, several times of overprinting is performed as necessary, and the thickness of the groove structure 10 is about 5 μm to about 100 μm. Becomes The size of the bare chip IC 7 is about 5 mm.
Since the pitch of the gold bumps for connection is about 100 μm to about 500 μm, the width of the size of the groove structure 10 of the present invention is about 20 μm to about 500 μm.
m, length is about 1 mm to about 5 mm, height is about 1
0 μm to about 100 μm, pitch of arrangement is about 70 μm
About 3 mm μm is used.

FIG. 2 shows an FP according to an embodiment of the present invention.
It is explanatory drawing at the time of using the copper foil circuit pattern which is a metal material for the material of a groove structure in the resin sealing structure of the bare chip IC on C, and its manufacturing method, (a) Top view, (b) Sectional drawing (C) is a cross-sectional view when the sealing resin is filled.

FIG. 2 shows an embodiment in which a groove structure according to the present invention is formed by a copper foil pattern which is a metal material constituting a circuit pattern in an FPC. Except that the groove structure according to the present invention is made of a copper foil pattern which is a metal material, it is almost the same as the case of the embodiment shown in FIG.

In the plan view of FIG. 2A, the connection lead (ILB) 1 on which the bare chip IC 7 is mounted on the FPC 2 is shown.
Are arranged in four directions so as to face the bumps of the bare chip IC, and correspond to the lower part of the mounted bare chip IC.
A groove structure 11 according to the present invention is formed on the FPC 2 on the region. Reference numeral 3 denotes a resin application position. In the cross-sectional view of FIG. 2B, a copper foil circuit pattern (about 1 μm thick) is formed on a polyimide film (about 25 μm thick) 4 which is a base material of the FPC.
8 μm) 5, resist agent (material is polyimide material,
(About 5 μm thick) 6 is printed. And FP
C2 is composed of a polyimide film 4, a copper foil circuit pattern 5, and a resist agent 6.

FIG. 2C is a sectional view of a resin sealing structure in which a bare chip IC is mounted on an FPC. There is a copper foil circuit pattern 5 on a polyimide film 4 which is a base material of the FPC, a resist agent 6 is printed, and a connection gold bump (size about several tens μm to one hundred and several tens μm) 8 on the bare chip IC 7 is made of copper foil. It is pressed into contact with the circuit pattern 5 to achieve electrical conduction. The groove structure 11 of the present invention is provided on the FPC area corresponding to the lower part of the bare chip IC to be mounted,
The space between the bare chip IC and the FPC is filled with a sealing resin 9. As the sealing resin 9, low viscosity (about 3
Poise to about 50 poise) A thermosetting epoxy resin material was used.

The method of manufacturing the groove structure using the copper foil pattern is as follows.
When the circuit pattern 5 of the copper foil on the polyimide film 4 which is the base material of the FPC is formed by etching,
The groove structure 11 according to the present invention is also formed on the FPC area corresponding to the lower part of the mounted bare chip IC. When forming a circuit,
At the same time, a groove structure can be formed, and no additional steps or dedicated devices are required. The flow of the sealing resin is the same as in the first embodiment. In the case of the groove structure using the copper foil pattern, the thickness of the copper foil pattern is about 18 μm, which is superior to the groove structure using the resist in terms of thickness. If the sealing resin is applied from the position 3, the resin is uniformly filled around and below the bare chip IC by the groove structure 11, and generation of bubbles can be suppressed.

FIG. 3 shows an FP according to an embodiment of the present invention.
It is explanatory drawing at the time of using the material which contains at least one component material of FPC in the resin structure of the bare chip IC on C, and its manufacturing method in a groove structure, (a) Top view, (b) Sectional drawing (C) is a cross-sectional view when the sealing resin is filled.

The present embodiment is the same as the embodiment shown in FIG. 1 except that the groove structure of the present invention is made of a material containing at least one constituent material of the FPC. The present invention is manufactured by continuously performing the case of the embodiment shown in FIG. 1 followed by the case of the embodiment shown in FIG.

In the plan view of FIG. 3A, the connection lead (ILB) 1 on which the bare chip IC 7 is mounted on the FPC 2 is shown.
Are arranged in four directions so as to face the bumps of the bare chip IC, and correspond to the lower part of the mounted bare chip IC.
A groove structure 12 according to the present invention is formed on the FPC 2 on the region. And, the groove structure 12 according to the present invention is FP
It has a laminated structure of a copper foil pattern layer, which is one of the constituent materials of C, and a resist agent. Reference numeral 3 denotes a resin application position. In the cross-sectional view of FIG. 3B, a copper foil circuit pattern (about 18 μm in thickness) 5 is provided on a polyimide film (about 25 μm in thickness) 4 which is a base material of the FPC, and a resist agent (the material is a polyimide material, (About 5 μm) 6 is printed. The FPC 2 includes a polyimide film 4, a copper foil circuit pattern 5, and a resist agent 6.

FIG. 3C is a sectional view of a resin sealing structure in which a bare chip IC is mounted on an FPC. There is a copper foil circuit pattern 5 on a polyimide film 4 which is a base material of the FPC, a resist agent 6 is printed, and a connection gold bump (size about several tens μm to one hundred and several tens μm) 8 on the bare chip IC 7 is made of copper foil. It is pressed into contact with the circuit pattern 5 to achieve electrical conduction. And, the groove structure 12 of the present invention is provided on the FPC region corresponding to the lower part of the bare chip IC to be mounted,
The space between the bare chip IC and the FPC is filled with a sealing resin 9. As the sealing resin 9, low viscosity (about 3
Poise to about 50 poise) A thermosetting epoxy resin material was used.

The method of manufacturing the groove structure by the copper foil pattern is as follows.
When the circuit pattern 5 of the copper foil on the polyimide film 4 which is the base material of the FPC is formed by etching,
The groove structure 12 according to the present invention is also formed on the FPC area corresponding to the lower part of the bare chip IC to be mounted. When forming a circuit,
At the same time, a groove structure can be formed, and no additional steps or dedicated devices are required. Further, as a method of manufacturing a groove structure using a resist thereon, after forming a groove structure using a copper foil pattern, a resist 6 is formed by printing and cured as shown in a plan view. At the time of resist printing, the groove structure of the present invention can be formed at the same time, and an additional processing step and a dedicated device are unnecessary.

The flow of the sealing resin is the same as in the first embodiment.
In the case of a groove structure having a two-layer structure based on the copper foil pattern and the resist agent, the thickness of the copper foil pattern is about 18 μm, and a thickness of about 5 μm due to the resist agent is added. ing. When the sealing resin is applied from the position 3, the resin is uniformly filled around and below the bare chip IC by the groove structure 12, and the generation of bubbles can be suppressed.

FIG. 4 shows an FP according to an embodiment of the present invention.
FIG. 7 is an explanatory view showing the shape of some groove structures in a resin sealing structure of a bare chip IC on C and a method of manufacturing the same.
Radial type groove structure, (b) parallel type groove structure, (c) anti-parallel type groove structure, (d) radial type and wide groove structure pattern, (e) radial type And (f) a groove structure formed by a combination of several patterns.

FIG. 4A shows a case where a radial groove structure 14 is formed from the resin application position 13. FIG. 4B shows a case where a parallel groove structure 15 is formed from the resin application position 13. FIG. 4 (c) is a case of manufacturing a trench structure 16 in the reverse radiation-shaped type resin coating position 13. FIG. 4D shows a case in which the groove structure 17 is formed in a radial pattern from the resin application position 13 and the groove structure pattern is thickened, and the amount of resin of the sealing resin can be reduced. FIG. 4E shows a groove structure 18 which is of a radial type from the resin application position 13 and has a high-density groove structure.
The pitch is set according to the viscosity of the resin material used and the state of generation of bubbles. While the pitch of the groove structure of the present invention shown in FIGS. 1 to 3 is about 500 μm to about 3 mm, the pitch of the present invention shown in FIG. 4 is about 100 μm to about 3 mm.
A high-density pitch of about 00 μm is used. FIG. 4 (f)
Is a groove structure 19 obtained by combining the above patterns.
It is.

There are several types of bump shapes of the bare chip IC. FIG. 5A shows a mushroom type bump, and FIG.
(B) It is a straight type bump, and there are other variations. Further, the arrangement of the bumps on the bare chip IC is set based on factors such as the circuit design and the heat radiation design of the circuit of the bare chip IC. 8 is a bare chip IC. The size (head shape) of the mushroom type bump is about 90 μm × about 120 μm to about 120 μm × about 140 μm
And the size of the straight bump is about 70 μm
× about 90 μm to about 100 μm × about 95 μm.

Therefore, the bumps are not always arranged only on the outer peripheral portion of the bare chip IC. In some cases, bumps are arranged in a grid pattern on almost the entire surface of the bare chip IC, and in other cases, bumps are radially arranged on almost the entire surface of the bare chip IC. Therefore, by using the combination pattern as shown in FIG. 4F, it is possible to suppress the inclusion of bubbles in the sealing resin. Further, by making the leading end 20 and the trailing end 21 of the groove structure circular, generation of bubbles can be suppressed more.

[0043]

As it is evident from the foregoing description, according to this onset bright, groove structure
It is possible to perform resin sealing without entrapping air bubbles in the sealing resin agent without requiring additional processing steps or dedicated devices .

[0044]

[0045]

[0046]

[0047]

The effects of the present invention are listed as follows: (1) The generation of bubbles can be suppressed when the sealing resin is applied.

(2) The uneven resin inflow due to the bump shape and the pump bite of the bare chip IC can be improved, and the resin can be reliably sealed around the bare chip IC and under the bare chip IC.

(3) Since the generation of air bubbles can be prevented at the stage when the sealing resin is applied, the defoaming step can be omitted.
Man-hours can be reduced and production efficiency can be improved. Therefore, the cost can be reduced.

(4) The volume of the sealing resin can be reduced by the groove structure, and the amount of resin used can be reduced. Also, the resin application time can be reduced.

(5) Since the groove structure is formed below the bare chip IC, the strength after resin sealing can be improved.

(6) Since the groove structure is formed below the bare chip IC, it is effective in preventing warpage due to humidity or heat in a single FPC, and the mounting accuracy of the bare chip IC can be improved.

[Brief description of the drawings]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view in a case where a resist agent as an organic material is used for a groove structure in a resin sealing structure of a bare chip IC on an FPC and a method of manufacturing the same according to an embodiment of the present invention; A plan view, (b) cross-sectional view, and (c) a cross-sectional view when a sealing resin is filled are shown.

FIG. 2 is an explanatory diagram in a case where a copper foil circuit pattern which is a metal material is used for a groove structure in a resin sealing structure of a bare chip IC on an FPC and a method of manufacturing the same according to an embodiment of the present invention; (A) is a plan view, (b) is a cross-sectional view, and (c) is a cross-sectional view when a sealing resin is filled.

FIG. 3 is an explanatory view in a case where a material including at least one component material of an FPC is used for a groove structure in a resin sealing structure of a bare chip IC on an FPC and a method of manufacturing the same according to an embodiment of the present invention; Yes, (a) plan view, (b)
A cross-sectional view shows a cross-sectional view when the sealing resin is filled.

FIGS. 4A and 4B are views illustrating a resin sealing structure of a bare chip IC on an FPC and a method of manufacturing the same according to an embodiment of the present invention. (B) a parallel groove structure, (c) an anti-parallel groove structure, (d) a radial structure with a thick groove structure pattern, and (e) a radial structure and a groove structure. (F) shows a groove structure formed by combining several patterns.

5A and 5B are diagrams illustrating a resin sealing structure of a bare chip IC on an FPC according to an embodiment of the present invention and a shape of a bump of the bare chip IC in a method of manufacturing the same.
Mushroom type bumps and (b) straight type bumps are shown.

FIG. 6 shows a defoaming step of a sealing resin of a bare chip IC on an FPC in a conventional example.

FIG. 7 is an explanatory view of a resin sealing structure of a bare chip IC on an FPC of a conventional example, and (a) a plan view of the FPC before mounting;
(B) Cross-sectional view of FPC before mounting, (c) FPC after mounting
(D) shows a cross-sectional view of the FPC before mounting.

FIGS. 8A and 8B are diagrams illustrating the flow of a sealing resin between the bare chip IC and the bare chip IC in the resin sealing structure of the FPC on the FPC; FIG.
(B) There are bumps, the initial state of penetration of the sealing resin,
(C) A state in which there is a bump and bubbles are included after a lapse of time of penetration of the sealing resin, and (d) shows an AA ′ cross section of (c).

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 connection lead 2 FPC 3 coating position of sealing resin 4 polyimide film as base material of FPC 5 copper foil circuit pattern 6 resist agent 7 bare chip IC 8 connection bump 9 sealing resin agent 10 groove structure of the present invention on FPC area Reference Signs List 11 groove structure made of organic material of the present invention 12 groove structure made of a metal material of the present invention 13 groove structure made of a constituent material of FPC of the present invention 14 coating position of sealing resin 15 radial groove structure 16 parallel groove structure 17 Anti-parallel groove structure 18 Radial groove structure 19 Radial and high-density groove structure 20 Combination groove structure 21 Tip of groove structure 22 Termination of groove structure

Claims (6)

(57) [Claims] A circuit pattern formed on a base material;
The bare chip IC is mounted on the FPC on which the
In a resin sealing structure of the bare chip IC on the FPC for resin sealing the bare chip IC, an organic material forming a resist agent is formed on an FPC region corresponding to a lower portion of the bare chip IC to be mounted, and a sealing resin is formed.
Parallel or radiated from the position where the fat is applied to the filling direction
A resin sealing structure for a bare chip IC on an FPC , wherein a plurality of groove structures are provided in a radial or reverse radial manner . 2. A resist having a circuit pattern formed on a substrate.
The bare chip IC is mounted on the FPC on which the
Bare chip on FPC for resin-sealing the bare chip IC
In the resin sealing structure of the IC, on the FPC area corresponding to the lower part of the bare chip IC to be mounted
Formed by a metal material forming a circuit pattern and sealed
Parallel or release from the resin application position to the filling direction
That multiple groove structures are provided in a radial or reverse radial
Characteristic resin-sealed structure of bare chip IC on FPC. 3. The circuit structure according to claim 3, wherein the groove structure forms the circuit pattern.
It consists of a metal material and an organic material that constitutes a resist agent.
3. The resin sealing structure for a bare chip IC on an FPC according to claim 2, wherein: 4. A resist having a circuit pattern formed on a substrate.
The bare chip IC is mounted on the FPC on which the
Bare chip on FPC for resin-sealing the bare chip IC
In the manufacturing method of resin-sealing the IC, on the FPC area corresponding to the lower part of the bare chip IC to be mounted
The organic material that forms the resist simultaneously with the printing of the resist
From the position where the sealing resin is applied
Multiple grooves in parallel, radial or counter-radial
Is formed, and a sealing resin is applied and filled at the application position of the sealing resin.
Resin sealing of bare chip IC on FPC
Manufacturing method . 5. A resist having a circuit pattern formed on a substrate.
The bare chip IC is mounted on the FPC on which the
In a manufacturing method of resin-sealing a bare chip IC on an FPC for resin-sealing the bare chip IC , a circuit pattern is etched on an FPC region corresponding to a lower portion of the bare chip IC to be mounted simultaneously with etching of a circuit pattern.
From the position where the sealing resin is applied
Parallel to the filling direction or radial or counter-radial
A method of manufacturing a resin for a bare chip IC on an FPC , wherein a plurality of groove structures are formed, and a sealing resin is applied and filled at a position where the sealing resin is applied . 6. The groove structure forms the circuit pattern.
The metal material and the resist formed simultaneously with the printing of the resist agent
And an organic material forming a strike agent.
6. The resin sealing of the bare chip IC on the FPC according to claim 5.
Manufacturing method.