JPH0629427A - Semiconductor mounting substrate - Google Patents
Semiconductor mounting substrateInfo
- Publication number
- JPH0629427A JPH0629427A JP34106491A JP34106491A JPH0629427A JP H0629427 A JPH0629427 A JP H0629427A JP 34106491 A JP34106491 A JP 34106491A JP 34106491 A JP34106491 A JP 34106491A JP H0629427 A JPH0629427 A JP H0629427A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- sealing resin
- resin
- substrate
- water
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、長期信頼性に優れた半
導体搭載用基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting substrate having excellent long-term reliability.
【０００２】[0002]
【従来の技術】従来、半導体チップをプリント配線板に
接続する方法としては、ピングリッドアレー、リードレ
スチップキャリア、リーディッドチップキャリア等の半
導体搭載用基板を用いる方法が知られている。しかし、
近年、搭載される半導体チップの高速化、高集積化、大
容量化に伴い、チップの大型化が進展してきており、半
導体チップの信頼性は益々必要となっており、このため
半導体封止樹脂（８）にかかる要求はさらに厳しいもの
になっている。具体的には、耐ＰＣＴ性、耐温度サイク
ル、耐熱性、低応力等全ての特性を、満足しなければな
らない。特に、従来の半導体封止樹脂においては、耐Ｐ
ＣＴ性に問題があった。2. Description of the Related Art Conventionally, as a method of connecting a semiconductor chip to a printed wiring board, there is known a method of using a semiconductor mounting substrate such as a pin grid array, a leadless chip carrier or a lead chip carrier. But,
In recent years, as semiconductor chips to be mounted have become faster, more highly integrated, and have a larger capacity, the size of the chips has been increasing, and the reliability of the semiconductor chips has become more and more necessary. The requirement for (8) is becoming more severe. Specifically, all characteristics such as PCT resistance, temperature cycle resistance, heat resistance, and low stress must be satisfied. Particularly, in the conventional semiconductor encapsulation resin, P resistance
There was a problem with CT properties.
【０００３】従来の半導体搭載用基板においては図２に
示すように半導体チップ（１０）を搭載し、ボンディン
グワイヤ（１１）で回路パターンのボンディングパッド
（４）と接続した後、封止樹脂枠（５）を貼り付け半導
体封止樹脂（８）にて半導体チップ（１０）を封止して
パッケージを形成し、該パッケージ状態でＰＣＴ試験を
実施すると、半導体封止樹脂の表面から水分が侵入し、
樹脂中のイオンと共に拡散し半導体チップ上に達し、パ
ット部の腐食となり、断線不良の原因となっていた。In a conventional semiconductor mounting substrate, a semiconductor chip (10) is mounted as shown in FIG. 2, and after connecting with a bonding pad (4) of a circuit pattern by a bonding wire (11), a sealing resin frame ( 5) is attached, the semiconductor chip (10) is sealed with the semiconductor sealing resin (8) to form a package, and when a PCT test is performed in the package state, moisture enters from the surface of the semiconductor sealing resin. ,
It diffuses with the ions in the resin and reaches the surface of the semiconductor chip, causing corrosion of the pad portion, which is a cause of disconnection failure.
【０００４】このため、図３に示すようにフッ素系樹
脂、シリコーン系樹脂に代表される撥水性樹脂（９）を
半導体封止樹脂上に被覆することが提案されているが、
これらの樹脂は元々の粘度及び硬化中の粘度が低いう
え、密着性がないため凸状の半導体封止樹脂から樹脂枠
を越える程流出し、被覆できない部分が生じ本来の水分
の侵入を押さえることができなかった。For this reason, as shown in FIG. 3, it has been proposed to coat the semiconductor sealing resin with a water-repellent resin (9) typified by a fluorine resin and a silicone resin.
These resins have low original viscosity and low viscosity during curing, and because they do not have adhesion, they flow out from the convex semiconductor encapsulating resin beyond the resin frame, leaving uncoverable parts and preventing the original intrusion of water. I couldn't.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、上記のよう
な半導体封止樹脂に侵入する水分により腐食が発生する
事を防止し、長期信頼性の問題を解決した半導体搭載用
基板を提供することを目的としたものである。DISCLOSURE OF THE INVENTION The present invention provides a semiconductor mounting substrate which prevents the occurrence of corrosion due to the water entering the semiconductor encapsulating resin as described above and solves the problem of long-term reliability. This is the purpose.
【０００６】[0006]
【課題を解決するための手段】即ち本発明は、プリント
回路板に凹部を設け、該凹部に半導体チップを搭載した
後、凹部周辺のボンディングパッドを取り囲む位置に封
止樹脂枠を貼り付けて封止樹脂を注入する半導体搭載用
基板であって、前記封止樹脂枠が二段の高さからなるこ
とを特徴とする半導体搭載用基板である。That is, according to the present invention, a recess is formed in a printed circuit board, a semiconductor chip is mounted in the recess, and a sealing resin frame is attached to a position surrounding the bonding pad around the recess to seal the printed circuit board. A semiconductor mounting substrate into which a stop resin is injected, wherein the sealing resin frame has two heights.
【０００７】以下、図面により本発明を説明する。図１
は、本発明による半導体搭載用基板の一実施例を示す図
で、（ａ）は上面図、（ｂ）は図（ａ）中のＡ−Ａ’断
面図、（ｃ）は図（ｂ）中のＢ部を拡大した図であり、
半導体チップを搭載し樹脂封止した基板のＢ部の拡大図
である。本発明の半導体搭載用基板は、両面銅張積層板
の所定の位置に、座ぐり加工による半導体搭載用凹部
（２）と、スルーホール（６）を形成し、回路パターン
（７）を形成した後、ソルダーレジスト（３）を基板に
印刷形成し、半導体用ボンディングパッド（４）及び露
出している導体部分にニッケル・金メッキを施し、更に
本発明の特徴である二段の高さを有する封止樹脂枠
（５）を接着する。そこで一段目の高さまで封止樹脂
（８）を注入硬化させ更に、撥水性の樹脂（９）を二段
目まで注入硬化させるものである。The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a diagram showing an embodiment of a semiconductor mounting substrate according to the present invention, (a) is a top view, (b) is a sectional view taken along the line AA ′ in FIG. (A), and (c) is a diagram (b). It is the figure which expanded the B section inside,
It is an enlarged view of the B section of the board | substrate which mounted the semiconductor chip and was resin-sealed. The semiconductor mounting substrate of the present invention has a semiconductor mounting recess (2) and a through hole (6) formed by spot facing at a predetermined position of a double-sided copper clad laminate, and a circuit pattern (7) is formed. After that, a solder resist (3) is formed on the substrate by printing, the semiconductor bonding pad (4) and the exposed conductor portion are plated with nickel and gold, and further, a seal having a two-step height which is a feature of the present invention. The resin frame (5) is adhered. Therefore, the sealing resin (8) is injected and cured to the height of the first step, and the water-repellent resin (9) is injected and cured to the second step.
【０００８】本発明における二段の高さを有する封止樹
脂枠については、樹脂枠の高さは特に限定するものでは
ない。基本的には、一段目の高さはボンディング用ワイ
ヤーが確実に被覆されればよく、高さとしては０．１ｍ
ｍ以上であれば特に限定しない。二段目については撥水
樹脂が封止樹脂上に確実に被覆できる量を堰止めれる高
さが必要となり撥水樹脂の硬化中の粘度等の特性によっ
て異なるが０．１ｍｍ以上であれば特に限定しない。
又、樹脂枠の形状は特に限定するものではないが、基本
的には、撥水樹脂が封止樹脂上に確実に被覆できる量を
堰止めれる形状であれば、図４、図５、図６、図７のい
ずれでも問題ない。Regarding the encapsulating resin frame having two steps in the present invention, the height of the resin frame is not particularly limited. Basically, the height of the first step should be 0.1 m as long as the bonding wire is surely covered.
It is not particularly limited as long as it is m or more. For the second stage, a height that can block the amount of water-repellent resin that can be reliably coated on the encapsulating resin is required, and it depends on characteristics such as viscosity of the water-repellent resin during curing. Not limited.
Although the shape of the resin frame is not particularly limited, basically, as long as the water-repellent resin has a shape capable of blocking the amount that can reliably cover the sealing resin, the resin frame shown in FIGS. There is no problem in either 6 or FIG.
【０００９】次に、樹脂枠の載置位置は特に限定するも
のではない。最内周のスルーホールの列とボンディング
パット部の間に納まるサイズで、スルーホールのランド
からの逃げが０．２ｍｍ以上、ボンディングパッドの先
端からの逃げが１ｍｍ以上であるものがよい。これはボ
ンディングパッド部（４）に近すぎて逃げが１ｍｍより
小さかったり、スルーホール（６）の上部まであった
り、あるいはスルーホールのランドからの逃げが０．２
ｍｍより小さいと接着剤がはみ出して、ボンディングパ
ッド部（４）におけるボンディング不良や、スルーホー
ル詰まりの原因となる。樹脂枠の材質は特に限定するも
のではないが、線膨張率がパッケージを構成している基
板（１）と同等であるものが好ましい。Next, the mounting position of the resin frame is not particularly limited. It is preferable that the size fits between the row of through holes on the innermost circumference and the bonding pad portion, and the clearance from the land of the through hole is 0.2 mm or more and the clearance from the tip of the bonding pad is 1 mm or more. This is because it is too close to the bonding pad part (4) and the clearance is smaller than 1 mm, or it is up to the upper part of the through hole (6), or the clearance from the land of the through hole is 0.2.
If it is smaller than mm, the adhesive will squeeze out, causing defective bonding in the bonding pad portion (4) and clogging of through holes. The material of the resin frame is not particularly limited, but it is preferable that the resin frame has a linear expansion coefficient equal to that of the substrate (1) forming the package.
【００１０】[0010]
【発明の効果】本発明によると撥水樹脂を半導体封止用
樹脂上に設けることが可能になり、ＰＣＴ（１２５℃、
２．３ａｔｍ）の環境下に放置しても水分の侵入を押さ
え、半導体封止用樹脂中の残存イオンの防止ができるこ
とから、信頼性の大幅な向上が可能になり、半導体チッ
プを搭載するパッケージ基板としては極めて有用なもの
である。According to the present invention, the water repellent resin can be provided on the semiconductor encapsulating resin, and the PCT (125 ° C.,
Even if left in an environment of 2.3 atm), moisture can be prevented from entering and residual ions in the resin for semiconductor encapsulation can be prevented, so that reliability can be greatly improved, and a package mounting a semiconductor chip. It is extremely useful as a substrate.
【図１】本発明による半導体搭載用基板の一実施例を示
す図で、（ａ）は上面図、（ｂ）は図（ａ）中のＡ−
Ａ′断面図、（ｃ）は図（ｂ）中のＢ部の拡大図であ
る。FIG. 1 is a diagram showing an embodiment of a semiconductor mounting substrate according to the present invention, in which (a) is a top view and (b) is A- in FIG.
A 'sectional view, (c) is an enlarged view of portion B in FIG.
【図２】従来の半導体搭載用基板に半導体チップを搭載
し樹脂封止した基板のＢ部の拡大図である。FIG. 2 is an enlarged view of a portion B of a conventional semiconductor mounting substrate on which a semiconductor chip is mounted and resin-sealed.
【図３】従来の半導体搭載用基板を用い撥水樹脂をコー
トしたＢ部の拡大図である。FIG. 3 is an enlarged view of a portion B coated with a water-repellent resin using a conventional semiconductor mounting substrate.
【図４】本発明における樹脂封止枠である。FIG. 4 is a resin sealing frame according to the present invention.
【図５】本発明における樹脂封止枠である。FIG. 5 is a resin sealing frame according to the present invention.
【図６】本発明における樹脂封止枠である。FIG. 6 is a resin sealing frame according to the present invention.
【図７】本発明における樹脂封止枠である。FIG. 7 is a resin sealing frame according to the present invention.
Claims (1)
半導体チップを搭載した後、凹部周辺のボンディングパ
ッドを取り囲む位置に封止樹脂枠を貼り付けて封止樹脂
を注入する半導体搭載用基板であって、前記封止樹脂枠
が二段の高さからなることを特徴とする半導体搭載用基
板。1. A semiconductor mounting substrate in which a recess is provided in a printed circuit board, a semiconductor chip is mounted in the recess, and a sealing resin frame is attached to a position surrounding a bonding pad around the recess to inject a sealing resin. The semiconductor mounting substrate, wherein the sealing resin frame has two heights.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34106491A JPH0629427A (en) | 1991-12-24 | 1991-12-24 | Semiconductor mounting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34106491A JPH0629427A (en) | 1991-12-24 | 1991-12-24 | Semiconductor mounting substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0629427A true JPH0629427A (en) | 1994-02-04 |
Family
ID=18342914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34106491A Pending JPH0629427A (en) | 1991-12-24 | 1991-12-24 | Semiconductor mounting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0629427A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62275188A (en) * | 1986-02-14 | 1987-11-30 | Casio Comput Co Ltd | Liquid crystal composition |
| JPH08213516A (en) * | 1995-01-31 | 1996-08-20 | Nec Corp | Semiconductor device and manufacture thereof |
| KR20000015580A (en) * | 1998-08-31 | 2000-03-15 | 김규현 | Circuit tape for semiconductor package |
| JP2009111428A (en) * | 2009-02-16 | 2009-05-21 | Kyocera Corp | Electronic device |
-
1991
- 1991-12-24 JP JP34106491A patent/JPH0629427A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62275188A (en) * | 1986-02-14 | 1987-11-30 | Casio Comput Co Ltd | Liquid crystal composition |
| JPH08213516A (en) * | 1995-01-31 | 1996-08-20 | Nec Corp | Semiconductor device and manufacture thereof |
| KR20000015580A (en) * | 1998-08-31 | 2000-03-15 | 김규현 | Circuit tape for semiconductor package |
| JP2009111428A (en) * | 2009-02-16 | 2009-05-21 | Kyocera Corp | Electronic device |
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