JPH09232474A - Resin sealing construction for bare chip ic on fpc and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the dispersion of penetration of resin flowing in between a bare chip IC and an FPC, to suppress the generation of an uneven flow, and to suppress the generation of bubbles on the occasion of applying sealing resin, by providing groove constructions on the FPC region below the bare chip IC mounted. SOLUTION: Groove constructions 10 are formed on an FPC surface 2, to prevent resin from flowing unevenly and from containing bubbles by surface tension, at positions in the lower region of the bare chip IC 7 of the board FPC 2 where the bare chip IC 7 is mounted. Concerning to these groove constructions 10, a plurality are formed in parallel to a direction of filling resin from a position of applying the resin, or radially or backwardly radially. As a result of this, concerning to resin flowing in between the bare chip IC 7 and the FPC 2, the amount of resin flowing in every groove is uniformalized, and filling can be performed without the generation of an uneven flow. Accordingly, it becomes possible to suppress the generation of bubbles on the occasion of applying the sealing resin.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a module which is highly reliable by sealing with a resin, and more particularly to a resin sealing structure for a bare chip IC on an FPC and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional method for preventing bubbles of a sealing resin in a resin sealing structure for a bare chip IC on an FPC is to prevent the bubbles from being generated when the resin is first applied. For printed wiring boards), the optimum value is examined according to the coating position and coating conditions (coating speed, coating amount, resin temperature, etc.) where bubbles are less likely to occur, and the viscosity of the resin agent itself is improved, resulting in high fluidity. I was using one. However, it was not possible to completely prevent the generation of air bubbles by such measures.

As a next countermeasure, a defoaming process of the sealing resin has been adopted. Fig. 6 shows a bare chip IC on a conventional FPC.
The defoaming process in the sealing resin of is shown. An electronic component module 50 in which a semiconductor component such as a bare chip IC is mounted on a substrate forming a circuit such as an FPC and a resin is applied is placed in a desiccator or a completely sealed temperature bath 51 before the resin is cured, and is connected to the bath. The vacuum pump 52 is operated to perform defoaming work. Reference numeral 53 indicates the exhaust gas at that time.

In short, the defoaming device is composed of a temperature chamber that can be completely sealed and a vacuum pump connected to it, and the air in the temperature chamber is discharged by operating the vacuum pump. Since the resin is not cured by putting it in this apparatus, the air pressure in the tank is reduced by the vacuum pump, and the bubbles in the sealing resin are discharged to the outside of the resin. Further, although the efficiency of defoaming can be improved by raising the temperature in the tank, such a troublesome defoaming step has been adopted.

An electronic component module 50 in which a semiconductor component such as a bare chip IC is mounted on a substrate forming a circuit such as an FPC and a resin is applied will be described with reference to FIG. Figure 7
(A) is a plan view before mounting, in which a connecting lead (ILB, inner lead bond) 55 for connecting to a bare chip IC of an IC mounting portion 55 is faced to a bump of the bare chip IC on an FPC (flexible printed wiring circuit). Are arranged in the direction. FIG. 7B is a sectional view before mounting. A copper foil 57 on a polyimide film 56, which is a base material of the FPC, is patterned by etching, and then a resist agent 58 is formed thereon by printing, and is cured.

FIG. 7 (c) is a plan view after mounting,
Is an FPC, 55 is a connection lead (ILB) for an IC mounting portion on the FPC, and 59 is a bare chip IC.
FIG. 7D is a sectional view after mounting. There is a copper foil 57 on a polyimide film 56 which is a base material of the FPC, a resist agent 58 is printed, and the bumps 6 on the bare chip IC 59.
0 is pressed against the copper foil 57 to establish electrical continuity.
The space between the bare chip IC and the FPC is filled with the sealing resin agent 61.

[0007]

However, the conventional resin encapsulation structure of a bare chip IC on an FPC has the following problems.

In the bare chip IC mounted on the FPC board having a circuit structure, the FPC board and the bare chip IC are electrically and mechanically joined to each other through a connection pump of several tens μm to one hundred and several tens μm. Therefore, the reliability is significantly affected by external force and environmental conditions.

Therefore, in order to protect the connection portion between the bare chip IC and the substrate, a resin agent such as an epoxy resin is applied to the space between the bare chip IC and the FPC and cured,
It ensures connection reliability. However, when bubbles are contained in the resin, cracks may occur in the sealing resin due to expansion and contraction of the bubbles depending on various conditions.
Further, the sealing resin is also injected into the lower portion of the bare chip IC, and in particular, bubbles generated in this portion push up the bare chip IC upward due to expansion, and stress in the peeling direction acts on the connection portion, leading to disconnection. Bubbles generated in the sealing resin were mostly concentrated in this portion. In the conventional FPC, even if there is nothing below the mounted bare chip IC and it is flat, the resin flowing between the FPC and the bare chip IC is
The penetration speed varies depending on the bump pitch and bump shape of the bare chip IC. This variation has made the flow of resin a turbulent flow and has been a factor in generating bubbles.

Next, the generation of bubbles in the resin sealing process of the bare chip IC mounted on the FPC in the conventional example will be described with reference to FIG.

FIG. 8A shows the flow of resin sealing when the FPC surface is smooth and the bare chip IC has no bumps (unrealistic). A region where the bare chip IC 59 is present is indicated by a dotted line, and the sealing resin agent 61 is injected from the resin application position 62, and the sealing resin agent propagates around the bare chip IC from the applied position. It can be divided into those that flow in due to surface tension during FPC. And
The traveling wave front 63 of the flow of the encapsulating resin agent has some irregularities, but in the unrealistic case where the FPC surface is smooth and the bare chip IC has no bumps, entrapment of bubbles does not occur. 55 shows FPC.

FIG. 8B shows how the encapsulating resin agent flows between the conventional FPC surface and the bare chip IC in the actual case. A region where the bare chip IC 59 is present is shown by a dotted line, and the encapsulating resin agent 61 is injected from the resin application position 62, is affected by the bump 64 of the bare chip IC 59, and is a traveling wave front 63 of the flow (permeation) of the encapsulating resin agent. Becomes more uneven. 55 shows FPC.

FIG. 8C shows the flow of the encapsulating resin agent when the time shown in FIG. 8B further elapses. 55 is FPC, 61
Is a sealing resin agent, and 62 is a resin coating position. The bumps 64 of the bare chip IC 59 affect the traveling wave front 63 of the flow of the sealing resin agent, and the unevenness becomes severe. Flow becomes turbulent and eventually bubbles 65
Will be involved. Also, since the connection bumps of the bare chip IC are not standardized in shape and size pitch by each manufacturer, the probability of bubble generation is not constant. FIG. 8D shows a cross section taken along the line AA ′ of FIG.

In the prior art, the bubbles generated in the sealing resin incorporate a defoaming process in which the bubbles are forcibly discharged by a vacuum pump, and the number of work items is large, which greatly affects the production efficiency. Was there. Further, there are some products in which the air bubbles cannot be completely removed even through this defoaming step, and the electronic component modules containing the air bubbles are selected and removed by a visual inspection with a microscope.

[0015]

In order to solve the above-mentioned problems, the present invention is characterized by a mechanism that does not generate bubbles when the resin is applied, rather than removing the generated bubbles in the sealing resin. Therefore, a groove structure is formed on the surface of the FPC in order to prevent the resin flowing due to the surface tension from causing a turbulent flow and enclosing bubbles at the position of the lower area of the bare chip IC of the substrate (FPC) on which the bare chip IC is mounted. To do. In the groove structure according to the present invention, a plurality of structures are formed in parallel, radially or inversely radially from the position where the resin is applied, in the filling direction. As a result, the bare chip I
The resin flowing between C and FPC has a groove structure according to the present invention, so that the amount of resin flowing in each groove is uniform, and the resin can be filled without causing turbulent flow. The shape of the groove structure of the present invention is
The most suitable structure (parallel type, radial type, reverse radial type, combination type, etc.) is selected in consideration of the bump shape of the bare chip IC to be mounted and conditions such as bump pitch.

According to the first aspect of the present invention, the resin sealing structure of the bare chip IC on the FPC has a bare chip IC on the FPC.
F, which is the bottom of the bare chip IC
A feature is that a groove structure is provided on the PC area.

The resin sealing structure for a bare chip IC on an FPC according to a second aspect of the present invention is characterized in that the groove structure is made of an organic material.

Further, a resin sealing structure of a bare chip IC on an FPC according to a third aspect of the present invention is characterized in that the groove structure is made of a metal material.

According to a fourth aspect of the present invention, in the resin sealing structure for a bare chip IC on an FPC, the groove structure is an FPC.
It is characterized by being composed of a material containing at least one or more of the constituent materials.

Further, according to a fifth aspect of the present invention, in a method of manufacturing a resin encapsulation of a bare chip IC on an FPC, the bare chip IC is mounted on the FPC, and a groove structure is formed on an FPC region corresponding to a lower portion of the bare chip IC to be mounted. Is provided to reduce turbulent flow at the time of resin injection.

The groove structure according to the present invention can alleviate the variation in permeation of the resin flowing between the bare chip IC and the FPC, suppress the generation of turbulent flow, and prevent the inclusion of bubbles. That is, the groove structure according to the present invention is parallel to the direction of the resin flowing from the resin application position, or has a groove structure according to the present invention to form one groove for several connecting bumps of the bare chip IC. The larger the number of grooves installed, the more the generation of turbulence can be suppressed. However, if the number of grooves is too large, the surface tension effect is attenuated, and conversely the sealing resin agent does not flow in, so it is necessary to adjust the number installed. When the sealing resin agent is applied, the resin flows into the lower portion of the bare chip IC via the connection bumps of the bare chip IC. Further, since the encapsulating resin agent flows along the groove structure of the present invention, even when bumps are present and the dispersion of penetration occurs, the turbulent flow of the encapsulating resin agent is reduced and bubbles are not included. Filling will be performed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 5 are diagrams relating to an embodiment of the present invention.

FIG. 1 shows an FP according to an embodiment of the present invention.
FIG. 6A is an explanatory view when a resist agent which is an organic material is used as a material of a groove structure in a resin sealing structure of a bare chip IC on C and a manufacturing method thereof, FIG. ) A cross-sectional view when filled with a sealing resin agent is shown.

In the plan view of FIG. 1A, the connection lead (ILB) 1 on which the bare chip IC 7 is mounted on the FPC 2 is shown.
Are arranged in four directions so as to face the bumps of the bare chip IC, and the groove structure 10 according to the present invention is formed on the FPC. Reference numeral 3 indicates a resin application position. In the cross-sectional view of FIG. 1B, a copper foil circuit pattern (thickness: about 18 μm) is formed on a polyimide film (thickness: about 25 μm) 4 which is a base material of the FPC.
m) 5 and a resist agent (made of a polyimide-based ink and having a thickness of about 5 μm) 6 is printed. And
The FPC 2 is composed of a polyimide film 4, a copper foil circuit pattern 5 and a resist agent 6.

FIG. 1C is a sectional view of a resin sealing structure in which a bare chip IC is mounted on an FPC.

Polyimide film 4 which is the base material of FPC
There is a copper foil circuit pattern 5 on top, a resist agent 6 is printed, and gold bumps (size of about several tens of μm to hundreds of tens of μm) 8 on the bare chip IC 7 are pressure-contacted with the copper foil circuit pattern 5 and are electrically connected. The electrical continuity is achieved. The groove structure 10 of the present invention is provided on the FPC region corresponding to the lower part of the bare chip IC to be mounted, and the space between the bare chip IC and the FPC is filled with the sealing resin agent 9. As the encapsulating resin agent 9, a thermosetting epoxy resin material having low viscosity (about 3 poise to about 50 poise) was used. In the method of manufacturing the groove structure using a resist, the copper foil circuit pattern 5 on the polyimide film 4 which is the base material of the FPC is patterned by etching, and then the resist 6 is formed by printing as shown in the plan view and cured. At the time of resist printing, the groove structure of the present invention can be produced at the same time, and an additional processing step or a dedicated device is unnecessary. If the sealing resin is applied from the position 3, the groove structure 10 uniformly fills the resin around and under the bare chip IC, thereby suppressing the generation of bubbles.

Groove structure 1 of the present invention by printing a resist agent
When 0 is formed at the same time, the thickness of one printing is about 5 μm, so several times of overlapping printing is performed, and the thickness of the groove structure 10 is about 5 μm to about 100 μm. Becomes Moreover, the size of the bare chip IC 7 is about 5 mm.
Since the pitch is about 30 mm to 30 mm, and the arrangement pitch of the gold bumps for connection is about 100 μm to about 500 μm, the width of the size of the groove structure 10 of the present invention is about 20 μm to about 500 μm.
m, length about 1 mm to about 5 mm, height about 1
0 μm to about 100 μm, pitch of arrangement is about 70 μm
˜about 3 mm μm is used.

FIG. 2 shows an FP according to an embodiment of the present invention.
It is explanatory drawing at the time of using the copper foil circuit pattern which is a metal material as the material of a groove | channel structure in the resin sealing structure of the bare chip IC on C, and its manufacturing method, (a) top view, (b) sectional drawing. , (C) are cross-sectional views when filled with a sealing resin agent.

FIG. 2 illustrates a case where the groove structure according to the present invention is made of a copper foil pattern, which is a metal material forming a circuit pattern in an FPC, according to an embodiment. It is almost the same as that of the embodiment shown in FIG. 1 except that the groove structure according to the present invention is made of a copper foil pattern which is a metal material.

In the plan view of FIG. 2A, the connection lead (ILB) 1 on which the bare chip IC 7 is mounted on the FPC 2 is shown.
Are arranged in four directions so as to face the bumps of the bare chip IC, and the FPC corresponding to the bottom of the mounted bare chip IC
A groove structure 11 according to the present invention is formed on the region on the FPC 2. Reference numeral 3 indicates a resin application position. In the cross-sectional view of FIG. 2B, a copper foil circuit pattern (thickness: about 1 μm) is formed on a polyimide film (thickness: about 25 μm) 4 which is a base material of the FPC.
8 μm) 5 and resist agent (material is polyimide material,
6 is printed. And FP
C2 is composed of a polyimide film 4, a copper foil circuit pattern 5 and a resist agent 6.

FIG. 2C is a sectional view of a resin sealing structure in which a bare chip IC is mounted on an FPC. There is a copper foil circuit pattern 5 on a polyimide film 4 which is a base material of an FPC, a resist agent 6 is printed, and a connection gold bump (size of about several tens μm to hundreds of tens μm) 8 on a bare chip IC 7 is a copper foil. The circuit pattern 5 is pressed into contact with the circuit pattern 5 for electrical conduction. Then, the groove structure 11 of the present invention is provided on the FPC region corresponding to the lower portion of the bare chip IC to be mounted,
The space between the bare chip IC and the FPC is filled with the sealing resin agent 9. The sealing resin agent 9 has a low viscosity (about 3
A thermosetting epoxy resin material was used.

A method for producing a groove structure using a copper foil pattern is as follows.
When the circuit pattern 5 of the copper foil on the polyimide film 4 which is the base material of the FPC is formed by etching,
The groove structure 11 according to the present invention is also formed on the FPC region corresponding to the lower part of the bare chip IC to be mounted. At the time of circuit formation,
At the same time, a groove structure can be formed, and no additional process or dedicated device is required. The inflow of the sealing resin is the same as in the first embodiment. In the case of the groove structure of the copper foil pattern, the thickness of the copper foil pattern is about 18 μm, which is superior in thickness to the groove structure of the resist. If the sealing resin is applied from the position 3, the resin can be uniformly filled in the periphery and the lower portion of the bare chip IC by the groove structure 11, and the generation of bubbles can be suppressed.

FIG. 3 shows an FP according to an embodiment of the present invention.
FIG. 4A is an explanatory diagram of a case where a material including at least one constituent material of FPC is used for a groove structure in a resin sealing structure of a bare chip IC on C and a manufacturing method thereof, FIG. , (C) are cross-sectional views when filled with a sealing resin agent.

The groove structure of the present invention is the same as that of the embodiment shown in FIG. 1 except that the groove structure is made of a material containing at least one constituent material of FPC. The present invention is manufactured by performing the case of the embodiment shown in FIG. 2 and then the case of the embodiment shown in FIG.

In the plan view of FIG. 3A, the connection lead (ILB) 1 on which the bare chip IC 7 is mounted on the FPC 2 is shown.
Are arranged in four directions so as to face the bumps of the bare chip IC, and the FPC corresponding to the bottom of the mounted bare chip IC
The groove structure 12 according to the present invention is formed on the FPC 2 on the region. The groove structure 12 according to the present invention is made of FP.
It has a laminated structure of a layer of a copper foil pattern which is one of the constituent materials of C and a resist agent. Reference numeral 3 indicates a resin application position. In the cross-sectional view of FIG. 3B, there is a copper foil circuit pattern (thickness: about 18 μm) 5 on a polyimide film (thickness: about 25 μm) 4 which is a base material of an FPC, and a resist agent (material is a polyimide material, thickness: 6 is printed. The FPC 2 is composed of the polyimide film 4, the copper foil circuit pattern 5 and the resist agent 6.

FIG. 3C is a sectional view of a resin sealing structure in which a bare chip IC is mounted on an FPC. There is a copper foil circuit pattern 5 on a polyimide film 4 which is a base material of an FPC, a resist agent 6 is printed, and a connection gold bump (size of about several tens μm to hundreds of tens μm) 8 on a bare chip IC 7 is a copper foil. The circuit pattern 5 is pressed into contact with the circuit pattern 5 for electrical conduction. Further, the groove structure 12 of the present invention is provided on the FPC region corresponding to the lower portion of the bare chip IC to be mounted,
The space between the bare chip IC and the FPC is filled with the sealing resin agent 9. The sealing resin agent 9 has a low viscosity (about 3
A thermosetting epoxy resin material was used.

A method for producing a groove structure using a copper foil pattern is as follows.
When the circuit pattern 5 of the copper foil on the polyimide film 4 which is the base material of the FPC is formed by etching,
The groove structure 12 according to the present invention is also formed on the FPC region corresponding to the lower part of the bare chip IC to be mounted. At the time of circuit formation,
At the same time, a groove structure can be formed, and no additional process or dedicated device is required. Further, in the method of manufacturing the groove structure by the resist thereon, after forming the groove structure by the copper foil pattern, the resist 6 is formed by printing as shown in the plan view and cured to manufacture. At the time of resist printing, the groove structure of the present invention can be produced at the same time, and an additional processing step or a dedicated device is unnecessary.

The inflow of the sealing resin is the same as in the first embodiment.
In the case of a groove structure having a two-layer structure of the copper foil pattern and the resist agent, the thickness of the copper foil pattern is about 18 μm, and the thickness of the resist agent is about 5 μm, which is more excellent in terms of thickness. ing. If the sealing resin is applied from the position 3, the groove structure 12 uniformly fills the resin around and under the bare chip IC, thereby suppressing the generation of bubbles.

FIG. 4 shows an FP according to an embodiment of the present invention.
FIG. 6A is a diagram illustrating the shapes of some groove structures in the resin sealing structure of the bare chip IC on C and the manufacturing method thereof,
Radial groove structure, (b) parallel groove structure, (c) anti-parallel groove structure, (d) radial groove structure with thick groove pattern, (e) radial groove And (f) a groove structure with a combination of several patterns.

FIG. 4A shows the case where the radial groove structure 14 is formed from the resin application position 13. FIG. 4B shows a case where the parallel groove structure 15 is formed from the resin application position 13. FIG. 4C shows a case where the antiparallel groove structure 16 is formed from the resin application position 13. FIG. 4D shows a case where the groove structure 17 is formed in a radial type from the resin application position 13 and the groove structure pattern is thick, and the resin amount of the sealing resin agent can be reduced. FIG. 4E shows a groove structure 18 which is of a radial type from the resin application position 13 and which has a high density groove structure.
The pitch is set according to the viscosity of the resin material used and the generation of bubbles. The arrangement pitch of the groove structure of the present invention shown in FIGS. 1 to 3 is about 500 μm to about 3 mm, whereas the arrangement pitch of the present invention shown in FIG. 4 is about 100 μm to about 3 mm.
A high density pitch of about 00 μm is used. FIG. 4 (f)
Is a combination of the above patterns Groove structure 19
It is.

There are several types of bumps for bare chip ICs. FIG. 5A shows a mushroom type bump, and FIG.
(B) It is a straight type bump, and there are other variations, and the placement of the bump on the bare chip IC is set based on factors such as the circuit design of the circuit of the bare chip IC and the heat radiation design. Reference numeral 8 is a bare chip IC. The size (head shape) of the mushroom type bump is about 90 μm × about 120 μm to about 120 μm × about 140 μm
The size of the straight bump is about 70 μm.
× about 90 μm to about 100 μm × about 95 μm.

Therefore, the bumps are not always arranged only on the outer peripheral portion of the bare chip IC. In some cases, the bumps are arranged in a grid pattern on almost the entire surface of the bare chip IC, and in some cases, the bumps are arranged radially on the almost entire surface of the bare chip IC. Therefore, by using the combination pattern as shown in FIG. 4F, it is possible to suppress inclusion of bubbles in the sealing resin agent. Further, by making the tip 20 and the end 21 of the groove structure circular, it is possible to further suppress the generation of bubbles.

[0043]

As described above, according to claim 1 of the present invention, a bare chip IC is mounted on an FPC, and the bare chip IC is resin-sealed. By providing the groove structure on the FPC region corresponding to the lower portion of the bare chip IC to be formed, it is possible to perform resin sealing without entraining bubbles in the sealing resin agent.

Further, in the resin sealing structure for bare chip IC on FPC according to claim 2 of the present invention, the groove structure is made of an organic material so that the sealing resin agent does not entrap air bubbles. You can

Further, in the resin sealing structure for bare chip IC on FPC according to claim 3 of the present invention, the groove structure is made of a metal material so that the sealing resin agent does not entrap air bubbles. You can

According to a fourth aspect of the present invention, in the resin sealing structure for a bare chip IC on an FPC, the groove structure is an FPC.
By using a material containing at least one of the above constituent materials, it is possible to perform resin encapsulation without entraining bubbles in the encapsulating resin agent.

Further, according to the method of manufacturing a resin-sealed structure according to claim 5 of the present invention, a bare chip IC is mounted on an FPC, and the bare chip IC is resin-sealed. In the manufacturing method described above, a turbulent flow at the time of resin injection is reduced by providing a groove structure on the FPC region corresponding to the bottom of the mounted bare chip IC.
It is possible to provide a method for manufacturing a resin-sealed bare chip IC on a PC.

Further, the effects of the present invention are listed as follows: (1) When applying the sealing resin, it is possible to suppress the generation of bubbles.

(2) It is possible to improve the uneven flow of resin due to the bump shape of the bare chip IC and the pump bitch, and reliably seal the resin around the bare chip IC and under the bare chip IC.

(3) Since the generation of bubbles can be prevented at the stage of applying the sealing resin, the defoaming step can be eliminated,
The number of steps can be reduced and the production efficiency can be improved. Therefore, the cost can be reduced.

(4) The groove structure can reduce the volume of the sealing resin and the amount of resin used. Also, the resin application time can be reduced.

(5) Since the groove structure is formed in the lower portion of the bare chip IC, the strength after resin sealing can be improved.

(6) Since the groove structure is formed in the lower portion of the bare chip IC, it is effective in preventing warpage due to humidity and heat in the single FPC, and the mounting accuracy of the bare chip IC can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a case where a resist agent which is an organic material is used for a groove structure in a resin sealing structure of a bare chip IC on an FPC and a manufacturing method thereof according to an embodiment of the present invention, FIG. A plan view, (b) sectional view, and (c) a sectional view when filled with a sealing resin agent are shown.

FIG. 2 is an explanatory diagram of a case where a copper foil circuit pattern, which is a metal material, is used for a groove structure in a resin sealing structure of a bare chip IC on an FPC and a manufacturing method thereof according to an embodiment of the present invention, (A) Plan view, (b) Sectional view, (c) Sectional view when filled with a sealing resin agent is shown.

FIG. 3 is an explanatory diagram of a case where a material including at least one constituent material of FPC is used for a groove structure in a resin sealing structure of a bare chip IC on an FPC and a manufacturing method thereof according to an embodiment of the present invention. Yes, (a) plan view, (b)
Sectional drawing, (c) Sectional drawing at the time of filling a sealing resin agent is shown.

FIG. 4 is an explanatory view showing the shapes of some groove structures in a resin sealing structure for a bare chip IC on an FPC and a method for manufacturing the same according to an embodiment of the present invention, including: (a) a radial groove structure; (B) Parallel type groove structure, (c) Anti-parallel type groove structure, (d) Radial type and groove structure with thick pattern, (e) Radial type and groove structure 3A and 3B show a groove structure having a high density, and (f) a groove structure formed by combining several patterns.

5A and 5B are explanatory views showing a resin sealing structure of a bare chip IC on an FPC and a bump shape of the bare chip IC in a manufacturing method thereof according to an embodiment of the present invention;
A mushroom type bump and (b) a straight type bump are shown.

FIG. 6 shows a defoaming process of a sealing resin for a bare chip IC on an FPC in a conventional example.

FIG. 7 is an explanatory view of a resin sealing structure of a bare chip IC on an FPC of a conventional example, (a) a plan view of the FPC before mounting,
(B) Cross-sectional view of FPC before mounting, (c) FPC after mounting
2D is a plan view of the FPC, and FIG.

FIG. 8 is a diagram illustrating a flow of an encapsulating resin agent between the bare chip IC and a bare chip IC in a resin encapsulation structure of a bare chip IC on an FPC.
(B) There is a bump and the initial state of penetration of the sealing resin,
(C) A state in which there are bumps and air bubbles are included after a lapse of time for permeation of the sealing resin, and (d) shows a cross section taken along the line AA ′ of (c).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Connection lead 2 FPC 3 Application position of sealing resin 4 Polyimide film which is a base material of FPC 5 Copper foil circuit pattern 6 Resist agent 7 Bare chip IC 8 Connection bump 9 Encapsulating resin agent 10 Groove structure of the present invention on FPC area 11 Groove Structure of Organic Material of the Present Invention 12 Groove Structure of Metallic Material of the Present Invention 13 Groove Structure of Constituent Material of FPC of the Present Invention 14 Sealing Resin Application Position 15 Radial Groove Structure 16 Parallel Groove Structure 17 Anti-parallel groove structure 18 Radial groove structure 19 Radial and high density groove structure 20 Combined groove structure 21 Tip of groove structure 22 End of groove structure

Claims (5)

[Claims] 1. A bare chip I on an FPC in which a bare chip IC is mounted on an FPC and the bare chip IC is resin-sealed.
Bare chip IC mounted in C resin sealing structure
A resin encapsulation structure for a bare chip IC on an FPC, characterized in that a groove structure is provided on an FPC region corresponding to a lower part of the FPC. 2. The resin sealing structure for a bare chip IC on an FPC according to claim 1, wherein the groove structure is made of an organic material. 3. The resin sealing structure for a bare chip IC on an FPC according to claim 1, wherein the groove structure is made of a metal material. 4. The resin sealing structure for a bare chip IC on an FPC according to claim 1, wherein the groove structure is made of a material containing at least one constituent material of the FPC. 5. A bare chip I on an FPC in which a bare chip IC is mounted on the FPC and the bare chip IC is resin-sealed.
In the resin encapsulation manufacturing method of C, a turbulent flow at the time of resin injection is reduced by providing a groove structure on the FPC region corresponding to the lower part of the bare chip IC to be mounted. Manufacturing method.