JP3685347B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3685347B2
JP3685347B2 JP35249295A JP35249295A JP3685347B2 JP 3685347 B2 JP3685347 B2 JP 3685347B2 JP 35249295 A JP35249295 A JP 35249295A JP 35249295 A JP35249295 A JP 35249295A JP 3685347 B2 JP3685347 B2 JP 3685347B2
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hole
semiconductor chip
holes
conversion
substrate
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JPH09186422A (en
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茂康 伊藤
康夫 久世
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【目次】
以下の順序で本発明を説明する。
発明の属する技術分野
従来の技術（図６及び図７）
発明が解決しようとする課題
課題を解決するための手段
発明の実施の形態
（１）第１実施例（図１〜図３）
（２）第２実施例（図４及び図５）
（３）他の実施例
発明の効果
【０００２】
【発明の属する技術分野】
本発明は半導体装置に関し、例えば一面にボール電極が配設されてなる半導体装置に適用して好適なものである。
【０００３】
【従来の技術】
従来、フリツプチツプ実装によつて半導体チツプがベアチツプで主基板（マザーボード）に実装されたものが用いられている。例えば図６（Ａ）に示すような半導体チツプ１において、当該半導体チツプ１の接合面１Ａには周縁部に沿つて所定のピツチでアルミニウム（Ａｌ）電極（図示せず）が配設され、当該各アルミニウム電極に対応してそれぞれはんだバンプ２が形成されている。
【０００４】
図６（Ｂ）において、図６（Ａ）に示す半導体チツプ１をＡ−Ａ′線で断面をとり、当該半導体チツプ１を主基板（マザーボード）３の実装面３Ａにフリツプチツプ実装したものを示す。この場合、主基板３の実装面３Ａには、複数のランド４がそれぞれはんだバンプ２と対応し得るように配設され、当該各ランド４に各はんだバンプ２を位置合わせした状態でマウントした後、これらをリフローすることによつて接合するようになされている。さらに半導体チツプ１及び主基板３間を例えばエポキシ樹脂でなる封止部材５で封止することによつて半導体チツプ１がパツケージングされている。
【０００５】
また同様にして、図７（Ａ）に示すような半導体チツプ６において、当該半導体チツプ６の接合面６Ａにはアルミニウム（Ａｌ）電極（図示せず）が所定のピツチで格子状に配設され、当該各アルミニウム電極に対応してそれぞれはんだバンプ７が形成されている。図７（Ｂ）において、図７（Ａ）に示す半導体チツプ６をＢ−Ｂ′線で断面をとり、当該半導体チツプ６を主基板（マザーボード）８の実装面８Ａにフリツプチツプ実装したものを示す。
【０００６】
この場合、主基板８の実装面８Ａには、複数のランド９がそれぞれはんだバンプ７と対応し得るように配設され、当該各ランド９に各はんだバンプ７を位置合わせした状態でマウントした後、これらをリフローすることによつて接合するようになされている。さらに半導体チツプ１及び主基板８間は例えばエポキシ樹脂でなる封止部材１０で封止することによつて半導体チツプ６がパツケージングされている。
【０００７】
近年、このようなプリツプチツプ実装技術では、半導体チツプ１及び６の多ピン化及び小型化を同時に満足させるべく、リードピツチの狭ピツチ化すなわちフアインピツチ化が進められている。
【０００８】
【発明が解決しようとする課題】
ところで、半導体チツプのリードピツチが 0.5〔mm〕、 0.4〔mm〕及び 0.3〔mm〕と次第に狭ピツチ化されるに伴い、製造過程における技術的な困難さが要求される。またこのようなフアインピツチ化された半導体チツプをフリツプチツプ実装する場合には、信頼性を向上させる必要性から樹脂封止が必要であり、このため半導体チツプの修理及び点検等が非常に困難となる問題があつた。
【０００９】
さらに主基板の実装面において、フリツプチツプ実装用の半導体チツプは他の一般部品と同じように実装されるが、当該フリツプチツプ実装用の専用の設備が必要となり、このため製造過程における時間的及び経済的な損失が大きくなるという問題があつた。
【００１０】
本発明は以上の点を考慮してなされたもので、半導体装置の実装対象となる配線基板に対する接続の信頼性を向上し得る半導体装置を提案しようとするものである。
【００１１】
【課題を解決するための手段】
かかる課題を解決するため本発明においては、変換基板の一面に半導体チツプの各電極に対応させて複数の第１の電極が設けられると共に、変換基板の他面に各第１の電極のうちの対応するものとそれぞれ一面及び他面間をスルーホールを介して導通接続された複数の第２の電極が設けられ、かつ変換基板の一面に半導体チツプがフリツプチツプ実装されてなる半導体装置において、第１の電極及び第２の電極は、スルーホールの孔内部に樹脂又は導電性のペーストでなる充填部材を充填して埋設した後、当該スルーホールの孔を両側から銅メツキを塗布して閉塞するようにして形成され、変換基板の一面に設けられた各第１の電極の膜厚よりも、当該変換基板の他面に設けられた各第２の電極の膜厚を厚くするようにした。
【００１２】
このように半導体装置を主基板の実装面に実装する場合に、当該実装面に形成された各電極を対応する各第２の電極とクリームはんだを用いて導通接続したとき、変換基板の一面に設けられた各第１の電極の膜厚よりも、当該変換基板の他面に設けられた各第２の電極の膜厚を厚くしたことにより、変換基板の他面及び主基板の実装面間でギヤツプを拡げることができ、この結果、ヒートストレスによる半導体チツプの損傷を未然に防ぐことができる。
【００１３】
【発明の実施の形態】
以下図面について、本発明の一実施例を詳述する。
【００１４】
（１）第１実施例
図１（Ａ）及び（Ｂ）において、２０は全体としていわゆるＣＳＰ（Chip Size Package ）を示し、半導体チツプ２１の接合面２１Ａには複数のアルミニウム（Ａｌ）電極（図示せず）が当該接合面２１Ａの各縁部に沿つて所定のピツチで配設され、当該各アルミニウム電極にはそれぞれはんだバンプ２２が対応して形成されている。
【００１５】
ここでＣＳＰ２０には、半導体チツプ２１がフリツプチツプ実装されると共に当該半導体チツプ２１及び主基板（図示せず）間を導通接続するようになされた回路基板（以下、これを変換基板と呼ぶ）２３が設けられている。この変換基板２３は、例えばガラスエポキシ又はＢＴレジン等からなる基材の両面に銅箔（図示せず）を張り合わせたいわゆる銅張積層板を加工することにより形成されている。
【００１６】
この変換基板２３の一面２３Ａには、複数の電極２４がそれぞれ半導体チツプ２１に形成されたはんだバンプ２２と対応し得るように配設され、当該各電極２４にそれぞれはんだバンプ２２を位置合わせした状態でマウントした後、これらをリフローすることによつて接合するようになされている。
【００１７】
この場合、複数のスルーホール２６は、変換基板２３の一面２３Ａの各縁部に沿つて所定のピツチで一面２３Ａ及び他面２３Ｂ間を介して配設されている。この変換基板２３の一面２３Ａにおいて、これら複数の電極２４からはそれぞれ配線パターン２５が引き出され、当該各配線パターン２５の先端は対応する各スルーホール２６と導通接続されている。
【００１８】
また変換基板２３の中央部には、所定の孔径でなる樹脂注入孔２７が一面２３Ａ及び他面２３Ｂ間を介して穿設され、半導体チツプ２１を一面２３Ａにフリツプチツプ実装した後、他面２３Ｂ側から樹脂注入孔２７を介して例えばエポキシ樹脂でなる封止部材２８を注入するようになされている。これにより半導体チツプ２１及び変換基板２３の一面２３Ａ間は封止部材２８で封止され、かくして半導体チツプ２１がパツケージングされ得る。
【００１９】
また図１（Ｂ）に示すように、変換基板２３の他面２３Ｂには複数のスルーホール２６の他端が若干突出して配設され、当該各スルーホール２６は、主基板（図示せず）の実装面に配設された複数のランドとそれぞれ対応して位置合わせされ得るようになされている。
【００２０】
具体的には図２（Ａ）及び（Ｂ）に示すように、複数のスルーホール２６は、変換基板２３の一面２３Ａ及び他面２３Ｂにおいて半導体チツプ２１の内側周縁部及び外側周縁部に沿つてそれぞれ２列ずつ所定のピツチで配設されている。また変換基板２３の一面２３Ａ及び他面２３Ｂにも、これら複数のスルーホール２６の配列状態を補足すべく、当該複数のスルーホール２６以外の所定位置に所定数のダミー用のスルーホール又はランド等（以下、これらをダミースルーホールと呼ぶ）２９が上述と同様に形成されている。
【００２１】
この場合、複数のスルーホール２６及びダミースルーホール２９は、それぞれ変換基板２３の他面２３Ｂから所定の高さで突出するように形成されている。
また変換基板２３の他面２３Ｂの四隅には、それぞれダミー用の金属バンプ（以下、これをダミーバンプと呼ぶ）３０Ａ〜３０Ｄが、これら各スルーホール２６及びダミースルーホール２９と同じバンプ高さを保つて形成されている。
【００２２】
続いて図１（Ａ）及び（Ｂ）との対応部分に同一符号を付して示す図３において、図１に示すＣＳＰ２０を主基板４０に実装した場合に当該ＣＳＰ２０のＣ−Ｃ′線を断面にとつて示す断面図を示す。なおここでは封止部材２８は図示しないこととする。
【００２３】
ここで変換基板２３を製造する前処理段階について説明する。まず変換基板２３の一面２３Ａに所定の厚みでなる銅箔（以下、これを第１の銅箔と呼ぶ）３２が張り合わされると共に、当該変換基板２３の他面２３Ｂにも第１の銅箔３２の厚みよりも比較的厚い第２の銅箔３３が張り合わされている。因みに、第１の銅箔３２は12〜18〔μｍ〕のうち所望の厚みで選定され、また第２の銅箔３３は12〜70〔μｍ〕のうち所望の厚みで選定される。
【００２４】
この変換基板２３に各スルーホール２６を形成するための孔を穿設加工するが、このときの各スルーホール２６の孔径は、当該各スルーホール２６のピツチ間隔、すなわち主基板４０の実装面４０Ａに所定のピツチで配設された各電極４１のピツチ間隔によつて決定される。例えば、ピツチ間隔が 0.5〔mm〕のときには各スルーホール２６の孔径は0.15〔mm〕となり、このとき半導体チツプ２１のピン数が200 前後までのものに対しては変換基板２３の外形の大きさを半導体チツプ２１の外形の大きさに近づけることができる。
【００２５】
この状態において変換基板２３に各スルーホール２６を形成することにより、当該変換基板２３の一面２３Ａ側及び他面２３Ｂ側からそれぞれ各スルーホール２６の一端部２６Ａ及び他端部２６Ｂがそれぞれ第１及び第２の銅箔３２及び３３を介してフランジ状に若干突出する。これにより第１の銅箔３２の厚みよりも第２の銅箔３３の厚みの方が大きいことから、変換基板２３の一面２３Ａからの各スルーホール２６の一端部２６Ａの距離よりも、変換基板２３の他面２３Ｂからの各スルーホール２６の他端部２６Ｂの距離の方が比較的長くなる。
【００２６】
この後、各スルーホール２６の一端部２６Ａ及び他端部２６Ｂに、それぞれ厚みが15〜30〔μｍ〕でなる導電性のスルーホールメツキ（図示せず）を塗布しておく。また各スルーホール２６の孔内部に、例えばエポキシ系の樹脂又は導電性のペーストでなる充填部材３６を充填して埋設しておく。続いて各スルーホール２６の孔内部に充填部材３６を充填した後、一端部２６Ａ及び他端部２６Ｂの両側からそれぞれ厚みが５〜10〔μｍ〕でなる銅メツキ３４及び３５を塗布することにより、各スルーホール２６の孔を閉塞する。
【００２７】
この後、変換基板２３の一面２３Ａ及び他面２３Ｂ共にパターンエツチングを行なうことにより、各スルーホール２６の一端部２６Ａ及び他端部２６Ｂ以外に張られた銅箔が取り除かれ、各スルーホール２６の一端部２６Ａ及び他端部２６Ｂにのみ第１及び第２の銅箔３２及び３３が形成される。
【００２８】
かくして変換基板２３の一面２３Ａには複数の電極２４及びこれらに対応する配線パターン２５がそれぞれスルーホール２６と導通接続するように配設されると共に、当該一面２３Ａの所定位置にはソルダレジスト３７が塗布される。また変換基板２３の他面２３Ｂには、各スルーホール２６の他端部２６Ｂと同じバンプの高さでなる所定数のダミースルーホール及びダミーバンプ（共に図示せず）が配設される。
【００２９】
なお、主基板４０の実装面４０Ａには、変換基板２３の他面２３Ｂに配設されている各スルーホール２６に対応して複数の電極４１が配設されているが、当該他面２３Ｂに配設されている各ダミースルーホールにも対応してそれぞれ所定数の電極（以下、これをダミーランドと呼ぶ）（図示せず）が形成されている。
【００３０】
これにより変換基板２３の他面２３Ｂに配設されている各スルーホール２６の他端部２６Ｂ及び各ダミースルーホールが、それぞれ同じバンプの高さを保つて主基板４０の実装面４０Ａにマウントされ得る。かくして変換基板２３及び主基板４０間の接続を補強して当該接続の信頼性を向上させることができる。なお主基板４０の実装面４０Ａの所定位置にはレジスト４３が塗布されている。
【００３１】
因みに主基板４０の実装面４０Ａに配設された各電極４１及び各ダミーランドには、それぞれ図示しないクリームはんだが印刷されており、ＣＳＰ２０を主基板４０にマウントした後リフローすることにより、各電極４１及び各ダミーランドにおいて溶融した各はんだバンプが、これらに対応する変換基板２３の他面２３Ｂに形成された各スルーホール２６の他端部２６Ｂ及び各ダミースルーホールとそれぞれ接合され得る。
【００３２】
以上の構成において、ＣＳＰ２０は、複数のスルーホール２６が所定のパターンで形成された変換基板２３の一面２３Ａに半導体チツプ２１をフリツプチツプ実装した後、樹脂封止することによつて当該半導体チツプ２１をパツケージングしたものである。
【００３３】
この場合、変換基板２３の一面２３Ａには、半導体チツプ２１の各はんだバンプ２２に対応してそれぞれ電極２４が配設され、当該各電極２４はそれぞれ配線パターン２５を介して各スルーホール２６の一端部２６Ａと導通接続されている。
【００３４】
また変換基板２３の他面２３Ｂには、各スルーホール２６の他端部２６Ｂが突出されると共に、所定のパターンで複数のダミースルーホール２９及びダミーバンプ３０Ａ〜３０Ｄが形成されている。これら各スルーホール２６の他端部２６Ｂ及び各ダミースルーホール２９及びダミーバンプ３０Ａ〜３０Ｄは、主基板４０の実装面４０Ａに配設された各電極４１及び各ダミーランド（図示せず）に対応して配置されている。
【００３５】
これによりＣＳＰ２０を主基板４０の実装面４０Ａに実装した後に樹脂封止しなくても、当該ＣＳＰ２０及び主基板４０間の接続における信頼性を向上させることができる。従つてＣＳＰ２０を主基板４０から容易に取り外すことができ、かくして半導体チツプ２１を容易に修理及び点検等することができる。
【００３６】
またＣＳＰ２０において、変換基板２３に複数のスルーホール２６を設け、当該各スルーホール２６を介して半導体チツプ２０及び主基板４０間を導電接続させるようにしたことにより、変換基板２３の一面２３Ａ及び他面２３Ｂに複数の配線パターンを配設する必要がなくて済み、かくして変換基板２３の外形を半導体チツプ２０の外形とほぼ同じ大きさで成形することができる。
【００３７】
さらにＣＳＰ２０において、変換基板２３の他面２３Ｂに配設された複数のスルーホール２６の他端部２６Ｂの当該他面２３Ｂからの距離を、それぞれ対応する各スルーホール２６の一端部２６Ａの当該一面２３Ａからの距離よりも長くなるように形成したことにより、ＣＳＰ２０を主基板４０に実装した場合に、隣り合う電極間でブリツジが生じるのを防止することができる。また変換基板２３の他面２３Ｂ及び主基板４０の実装面４０Ａ間でギヤツプを拡げることができ、この結果、ヒートストレスによる半導体チツプ２１の損傷を未然に防ぐことができる。
【００３８】
さらにＣＳＰ２０において、変換基板２３に配設した複数のスルーホール２６の他端部２６Ｂと同じ長さでなる複数のダミースルーホール２９及びダミーバンプ３０Ａ〜３０Ｄを形成したことにより、主基板４０の実装面４０Ａにはこれらに対応する各電極４１及び各ダミーランド４２を設けるのみで、変換基板２３及び主基板４０間の接続を補強して当該接続の信頼性を向上させることができる。
【００３９】
さらにこの結果主基板４０の実装面４０Ａに予めＣＳＰ２０に対する専用の設備を用意する必要がなく、ＣＳＰ２０を主基板４０に実装する過程における時間的及び経済的な損失を従来よりも格段と低減させ得る。
【００４０】
以上の構成によれば、複数のスルーホール２６が所定のパターンで形成された変換基板２３の一面２３に、半導体チツプ２１を当該各スルーホール２６と導通接続させてフリツプチツプ実装した後樹脂封止することによつて当該半導体チツプ２１をパツケージングしたＣＳＰ２０を設け、当該変換基板２３の他面２３Ｂから各スルーホール２６を所定の長さで突出させると共に、当該各スルーホール２６と同じ長さでなる複数のダミースルーホール２９及びダミーバンプ３０Ａ〜３０Ｄを形成したことにより、主基板４０に対する接続の信頼性を向上し得ると共にＣＳＰ２０全体としての大きさを比較的小型化することができる。
【００４１】
（２）第２実施例
図４は第２実施例におけるＣＳＰ５０を示し、第１実施例と同様に半導体チツプ５１が変換基板５３にフリツプチツプ実装された構成からなる。この場合、半導体チツプ５１の接合面５１Ａには、複数のアルミニウム電極（図示せず）に対応してそれぞれはんだバンプ５２が当該接合面５１Ａの内側周縁部に沿つて所定のピツチで４列ずつ配設されている。
【００４２】
変換基板５３には、一面５３Ａ及び他面５３Ｂ間を介して複数のスルーホール５４がそれぞれ半導体チツプ５１に形成されたはんだバンプ５２と対応し得るように配設され、当該各スルーホール５４にそれぞれはんだバンプ５２を位置合わせした状態でマウントした後、これらをリフローすることによつて接合するようになされている。
【００４３】
この場合、変換基板５３の一面５３Ａ及び他面５３Ｂからは、第１実施例と同様に、それぞれ各スルーホール５４の一端部５４Ａ及び他端部５４Ｂが突出されている。また変換基板５３の一面５３Ａからの一端部５４Ａの距離よりも変換基板５３の他面５３Ｂからの他端部５４Ｂの距離の方が比較的長くなるように、それぞれ第１及び第２の銅箔５５及び５６が張られている。
【００４４】
さらに各スルーホール５４の孔内部に充填部材６０を充填して埋設しておくと共に、一端部５４Ａ及び他端部５４Ｂの両側からそれそれ所定の厚みでなる銅メツキ５７及び５８を塗布して各スルーホール５４の孔を閉塞する。なお変換基板５３の一面５３Ａの所定位置にはソルダレジスト５９が塗布されている。
【００４５】
なお、主基板７０の実装面７０Ａには、変換基板５３の他面５３Ｂに配設されている各スルーホール５４に対応して複数の電極７１が配設されている。これにより変換基板５３の他面５３Ｂに配設されている各スルーホール５４の他端部５４Ｂ及び各ダミーバンプ６２Ａ〜６２Ｄが、それぞれ同じバンプの高さを保つて主基板７０の実装面７０Ａにマウントされ得る。かくして変換基板５３及び主基板７０間の接続を補強して当該接続の信頼性を向上させることができる。なお主基板７０の実装面７０Ａの所定位置にはレジスト７２が塗布されている。
【００４６】
因みに主基板７０の実装面７０Ａに配設された各電極７１には、それぞれ図示しないクリームはんだが印刷されており、ＣＳＰ５０を主基板７０にマウントした後リフローすることにより、各電極７１において溶融した各はんだバンプが、これらに対応する変換基板５３の他面５３Ｂに形成された各スルーホール５４の他端部５４Ｂとそれぞれ接合され得る。
【００４７】
ここで図５（Ａ）及び（Ｂ）において、変換基板５３の一面５３Ａ及び他面５３Ｂを示す。変換基板５３の中央には、所定の孔径でなる樹脂注入孔６１が一面５３Ａ及び他面５３Ｂを介して穿設され、当該樹脂注入孔６１を介して封止部材（図示せず）が注入されるようになされている。また変換基板５３の他面５３Ｂの四隅には、それぞれダミーバンプ６２Ａ〜６２Ｄが所定のバンプ高さを保つて形成されている。
【００４８】
以上の構成によれば、複数のスルーホール５４が所定のパターンで形成された変換基板５３の一面５３Ａに、半導体チツプ５１を当該各スルーホール５４と導通接続させてフリツプチツプ実装した後樹脂封止することによつて当該半導体チツプ５１をパツケージングしたＣＳＰ５０を設け、当該変換基板５３の他面５３Ｂから各スルーホール５４を所定の長さで突出させると共に、当該各スルーホール５４と同じ長さでなる複数のダミーバンプ６２Ａ〜６２Ｄを形成したことにより、主基板７０に対する接続の信頼性を向上し得ると共にＣＳＰ５０全体としての大きさを比較的小型化することができる。
【００４９】
さらにこのＣＳＰ５０においては、変換基板５３に配設された複数のスルーホール５４がそれぞれ半導体チツプ５１に形成されたはんだバンプ５２と直接対応し得るように配設されていることから、第１実施例におけるＣＳＰ２０よりも格段と小型化することができる。
【００５０】
（３）他の実施例
なお第１及び第２実施例においては、変換基板２３及び５３に配設された複数のスルーホール２６及び５４の配列パターンをそれぞれ図２（Ａ）及び（Ｂ）と図５（Ａ）及び（Ｂ）に示すようにした場合について述べたが、本発明はこれに限らず、半導体チツプに形成された複数のはんだバンプに対応し得るようにすれば、その他種々の配列パターンで配設するようにしても良い。
【００５１】
また第１及び第２実施例においては、変換基板２３及び５３の各他面２３Ｂ及び５３Ｂに配設された複数のダミースルーホール２９及びダミーバンプ３０Ａ〜３０Ｄ及び６２Ａ〜６２Ｄの配列パターンをそれぞれ図２（Ｂ）及び図５（Ｂ）に示すようにした場合について述べたが、本発明はこれに限らず、その他種々の配列パターンで配設するようにしても良い。さらにこれらダミースルーホール２９、ダミーバンプ３０Ａ〜３０Ｄ及び６２Ａ〜６２Ｄがなくても接続の安定性を確保し得る場合には、これらダミーバンプの一部又は全部を形成しなくても良い。
【００５２】
さらに第１及び第２実施例においては、ＣＳＰ２０及び５０において半導体チツプ２１及び５１の接合面２１Ａ及び５１Ａには複数のはんだバンプ２２及び５２を形成した場合について述べたが、本発明はこれに限らず、例えば金バンプ等の他の金属バンプを用いるようにしても良く、またその他種々のスタツドバンプを用いるようにしても良い。
【００５３】
さらに第１及び第２実施例においては、ＣＳＰ２０及び５０において変換基板２３及び５３を両面基板とした場合について述べたが、本発明はこれに限らず、例えば変換基板２３及び５３の各一面２３Ａ及び５３Ａにさらにそれぞれフオトビア層を積層した多層基板として用いるようにしても良い。
【００５４】
さらに第１及び第２実施例においては、変換基板２３及び５３に配設された複数のスルーホール２６及び５４の各孔内部にそれぞれ充填部材３６及び６０を充填して埋設するようにした場合について述べたが、本発明はこれに限らず、当該複数のスルーホール２６及び５４の各孔内部を充填することなく中空状態のままにしても良い。この場合、各スルーホール２６及び５４の内部に接合用のはんだが入り込むことにより、はんだ供給量が多い場合でも主基板４０及び７０に対する実装時においてブリツジの発生率を比較的低減させることができる。要は、スルーホール以外であつても変換基板２３及び５３の一面２３Ａ、５３Ａ及び他面２３Ａ、５３Ａを貫通して設けられた導電部材であれば種々のものを適用し得る。
【００５５】
さらに第１及び第２実施例においては、変換基板２３及び５３の中央部にそれぞれ樹脂注入孔２７及び６１を穿設した場合について述べたが、本発明はこれに限らず、これら樹脂注入孔２７及び６１を穿設しなくても良い。この場合、ＣＳＰ２０及び５０において半導体チツプ２１及び５１と変換基板２３及び５３との間に外部から種々の樹脂を注入するようにする。
【００５６】
【発明の効果】
上述のように本発明によれば、変換基板の一面に半導体チツプの各電極に対応させて複数の第１の電極が設けられると共に、変換基板の他面に各第１の電極のうちの対応するものとそれぞれ一面及び他面間をスルーホールを介して導通接続された複数の第２の電極が設けられ、かつ変換基板の一面に半導体チツプがフリツプチツプ実装されてなる半導体装置において、第１の電極及び第２の電極は、スルーホールの孔内部に樹脂又は導電性のペーストでなる充填部材を充填して埋設した後、当該スルーホールの孔を両側から銅メツキを塗布して閉塞するようにして形成され、変換基板の一面に設けられた各第１の電極の膜厚よりも、当該変換基板の他面に設けられた各第２の電極の膜厚を厚くするようにしたことにより、その分だけ変換基板の他面及び主基板の実装面間でギヤツプを拡げることができ、この結果、ヒートストレスによる半導体チツプの損傷を未然に防ぐことができ、かくして半導体装置の実装対象となる主基板に対する接続の信頼性を向上させることができる。
【図面の簡単な説明】
【図１】第１実施例によるＣＳＰの構成を示す略線図である。
【図２】第１実施例によるＣＳＰの変換基板の構成を示す平面図である。
【図３】第１実施例によるＣＳＰの主基板への実装時における部分的断面図である。
【図４】第２実施例によるＣＳＰの主基板への実装時における部分的断面図である。
【図５】第２実施例によるＣＳＰの変換基板の構成を示す平面図である。
【図６】従来のフリツプチツプ実装基板の構成を示す平面図及び断面図である。
【図７】従来のフリツプチツプ実装基板の構成を示す平面図及び断面図である。
【符号の説明】
２０、５０……ＣＳＰ、２１、５１……半導体チツプ、２２、５２……はんだバンプ、２３、５３……変換基板、２６、５４……スルーホール、２７、６１……樹脂注入孔、２８……封止部材、２９……ダミースルーホール、３０Ａ〜３０Ｄ、６２Ａ〜６２Ｄ……ダミーバンプ、３２、５５……第１の銅箔、３３、５６……第２の銅箔、４０、７０……主基板、４１、７１……電極。[0001]
【table of contents】
The present invention will be described in the following order.
TECHNICAL FIELD OF THE INVENTION
Conventional technology (FIGS. 6 and 7)
Problems to be solved by the invention
Means for solving the problem
BEST MODE FOR CARRYING OUT THE INVENTION
(1) 1st Example (FIGS. 1-3)
(2) Second embodiment (FIGS. 4 and 5)
(3) Other embodiments
The invention's effect
[0002]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and is suitable for application to, for example, a semiconductor device having a ball electrode disposed on one surface.
[0003]
[Prior art]
Conventionally, a semiconductor chip mounted on a main board (mother board) by a flip chip mounting is used. For example, in a semiconductor chip 1 as shown in FIG. 6 (A), an aluminum (Al) electrode (not shown) is disposed on the bonding surface 1A of the semiconductor chip 1 along a peripheral edge with a predetermined pitch. A solder bump 2 is formed corresponding to each aluminum electrode.
[0004]
6B, the semiconductor chip 1 shown in FIG. 6A is taken along the line AA ′, and the semiconductor chip 1 is flip-chip mounted on the mounting surface 3A of the main substrate (motherboard) 3. . In this case, a plurality of lands 4 are arranged on the mounting surface 3A of the main substrate 3 so as to correspond to the solder bumps 2, respectively, and after mounting the solder bumps 2 in alignment with the lands 4 respectively. These are joined by reflowing them. Further, the semiconductor chip 1 is packaged by sealing the semiconductor chip 1 and the main substrate 3 with a sealing member 5 made of, for example, epoxy resin.
[0005]
Similarly, in the semiconductor chip 6 as shown in FIG. 7A, aluminum (Al) electrodes (not shown) are arranged in a grid pattern with predetermined pitches on the bonding surface 6A of the semiconductor chip 6. The solder bumps 7 are formed corresponding to the respective aluminum electrodes. 7B, the semiconductor chip 6 shown in FIG. 7A is taken along the line BB ′, and the semiconductor chip 6 is flip-chip mounted on the mounting surface 8A of the main substrate (motherboard) 8. .
[0006]
In this case, a plurality of lands 9 are arranged on the mounting surface 8A of the main substrate 8 so as to correspond to the solder bumps 7, respectively, and after mounting the solder bumps 7 on the lands 9, the lands 9 are aligned. These are joined by reflowing them. Further, the semiconductor chip 6 is packaged by sealing between the semiconductor chip 1 and the main substrate 8 with a sealing member 10 made of, for example, epoxy resin.
[0007]
In recent years, in such a pre-chip mounting technique, lead pitches have been narrowed, that is, fine pitches, in order to satisfy the increase in the number of pins and the reduction in size of the semiconductor chips 1 and 6 at the same time.
[0008]
[Problems to be solved by the invention]
By the way, as the lead pitch of the semiconductor chip is gradually narrowed to 0.5 [mm], 0.4 [mm] and 0.3 [mm], technical difficulties in the manufacturing process are required. In addition, when such a fine-chip semiconductor chip is flip-chip mounted, resin sealing is necessary because of the need to improve reliability, which makes it difficult to repair and inspect the semiconductor chip. There was.
[0009]
Further, on the mounting surface of the main board, the semiconductor chip for mounting the chip is mounted in the same manner as other general components, but it requires special equipment for mounting the chip, which is time and economical in the manufacturing process. There was a problem of increasing the loss.
[0010]
The present invention has been made in consideration of the above points, and an object of the present invention is to propose a semiconductor device capable of improving the reliability of connection to a wiring board on which a semiconductor device is to be mounted.
[0011]
[Means for Solving the Problems]
In order to solve such a problem, in the present invention, a plurality of first electrodes are provided on one surface of the conversion substrate so as to correspond to the respective electrodes of the semiconductor chip, and among the first electrodes on the other surface of the conversion substrate. In a semiconductor device in which a plurality of second electrodes that are conductively connected to one another and the other surface through through holes are provided, and a semiconductor chip is flip-chip mounted on one surface of the conversion substrate. The electrode and the second electrode are filled with a filling member made of resin or conductive paste in the through-hole, and then the through-hole is closed by applying copper plating from both sides. Thus, the thickness of each second electrode provided on the other surface of the conversion substrate is made larger than the thickness of each first electrode provided on one surface of the conversion substrate.
[0012]
When the semiconductor device is mounted on the mounting surface of the main substrate in this way, when each electrode formed on the mounting surface is conductively connected to each corresponding second electrode using cream solder, By increasing the film thickness of each second electrode provided on the other surface of the conversion substrate rather than the film thickness of each provided first electrode, the distance between the other surface of the conversion substrate and the mounting surface of the main substrate As a result, it is possible to prevent the semiconductor chip from being damaged by heat stress.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0014]
(1) First embodiment
1A and 1B, reference numeral 20 denotes a so-called CSP (Chip Size Package) as a whole, and a plurality of aluminum (Al) electrodes (not shown) are provided on the bonding surface 21A of the semiconductor chip 21. Each of the aluminum electrodes is formed with a corresponding solder bump 22 corresponding to a predetermined pitch along each edge of 21A.
[0015]
Here, the CSP 20 has a circuit board (hereinafter referred to as a conversion board) 23 on which the semiconductor chip 21 is flip-chip mounted and the semiconductor chip 21 and a main board (not shown) are electrically connected. Is provided. The conversion substrate 23 is formed by processing a so-called copper-clad laminate in which copper foil (not shown) is bonded to both surfaces of a base material made of glass epoxy or BT resin, for example.
[0016]
A plurality of electrodes 24 are arranged on one surface 23A of the conversion substrate 23 so as to correspond to the solder bumps 22 formed on the semiconductor chip 21, respectively, and the solder bumps 22 are aligned with the respective electrodes 24. After mounting with, they are joined by reflowing them.
[0017]
In this case, the plurality of through-holes 26 are arranged between the one surface 23A and the other surface 23B with a predetermined pitch along each edge of the one surface 23A of the conversion substrate 23. On one surface 23A of the conversion substrate 23, wiring patterns 25 are drawn out from the plurality of electrodes 24, and the tips of the wiring patterns 25 are electrically connected to the corresponding through holes 26.
[0018]
Further, a resin injection hole 27 having a predetermined hole diameter is formed in the central portion of the conversion board 23 through the space between the one surface 23A and the other surface 23B. A sealing member 28 made of, for example, an epoxy resin is injected through the resin injection hole 27. As a result, the space between the semiconductor chip 21 and the one surface 23A of the conversion substrate 23 is sealed by the sealing member 28, and thus the semiconductor chip 21 can be packaged.
[0019]
As shown in FIG. 1B, the other surface 23B of the conversion board 23 is provided with the other ends of the plurality of through holes 26 protruding slightly, and each through hole 26 is a main board (not shown). The plurality of lands disposed on the mounting surface can be aligned with each other.
[0020]
Specifically, as shown in FIGS. 2A and 2B, the plurality of through holes 26 extend along the inner peripheral edge and the outer peripheral edge of the semiconductor chip 21 on the one surface 23 </ b> A and the other surface 23 </ b> B of the conversion substrate 23. Two rows each are arranged with a predetermined pitch. In addition, a predetermined number of dummy through holes or lands, etc. for a predetermined number other than the plurality of through holes 26 are also provided on the one surface 23A and the other surface 23B of the conversion substrate 23 in order to supplement the arrangement state of the plurality of through holes 26. (Hereinafter referred to as dummy through holes) 29 is formed in the same manner as described above.
[0021]
In this case, the plurality of through holes 26 and the dummy through holes 29 are formed so as to protrude from the other surface 23B of the conversion substrate 23 at a predetermined height, respectively.
Further, at the four corners of the other surface 23B of the conversion substrate 23, dummy metal bumps (hereinafter referred to as dummy bumps) 30A to 30D maintain the same bump height as the through holes 26 and the dummy through holes 29, respectively. Is formed.
[0022]
Subsequently, in FIG. 3 in which the same reference numerals are assigned to the corresponding parts in FIGS. 1A and 1B, when the CSP 20 shown in FIG. 1 is mounted on the main board 40, the CC ′ line of the CSP 20 is Sectional drawing shown to a cross section is shown. Here, the sealing member 28 is not shown.
[0023]
Here, the pre-processing stage which manufactures the conversion board | substrate 23 is demonstrated. First, a copper foil (hereinafter referred to as a first copper foil) 32 having a predetermined thickness is attached to one surface 23A of the conversion substrate 23, and the first copper foil is also applied to the other surface 23B of the conversion substrate 23. A second copper foil 33 that is relatively thicker than 32 is laminated. Incidentally, the first copper foil 32 is selected with a desired thickness of 12 to 18 [μm], and the second copper foil 33 is selected with a desired thickness of 12 to 70 [μm].
[0024]
A hole for forming each through-hole 26 is formed in the conversion board 23. The diameter of each through-hole 26 at this time is the pitch interval of each through-hole 26, that is, the mounting surface 40A of the main board 40. It is determined by the pitch interval of each electrode 41 arranged at a predetermined pitch. For example, when the pitch interval is 0.5 [mm], the hole diameter of each through hole 26 is 0.15 [mm]. At this time, the size of the outer shape of the conversion board 23 for the semiconductor chip 21 having up to about 200 pins. Can be made close to the size of the outer shape of the semiconductor chip 21.
[0025]
In this state, by forming each through hole 26 in the conversion substrate 23, one end 26A and the other end 26B of each through hole 26 are respectively connected to the first and other ends 23B from the one surface 23A side and the other surface 23B side of the conversion substrate 23, respectively. It protrudes slightly in a flange shape through the second copper foils 32 and 33. Accordingly, since the thickness of the second copper foil 33 is larger than the thickness of the first copper foil 32, the conversion board is more than the distance of the one end portion 26 </ b> A of each through hole 26 from the one surface 23 </ b> A of the conversion board 23. The distance of the other end portion 26B of each through hole 26 from the other surface 23B of 23 is relatively long.
[0026]
Thereafter, conductive through-hole plating (not shown) having a thickness of 15 to 30 [μm] is applied to one end 26A and the other end 26B of each through-hole 26. Further, the inside of each through hole 26 is filled with a filling member 36 made of, for example, epoxy resin or conductive paste. Subsequently, after filling the inside of each through hole 26 with a filling member 36, copper platings 34 and 35 each having a thickness of 5 to 10 [μm] are applied from both sides of the one end 26A and the other end 26B. The holes of the through holes 26 are closed.
[0027]
Thereafter, pattern etching is performed on both the one surface 23A and the other surface 23B of the conversion substrate 23, so that the copper foils stretched except for the one end portion 26A and the other end portion 26B of each through hole 26 are removed. The first and second copper foils 32 and 33 are formed only at the one end portion 26A and the other end portion 26B.
[0028]
Thus, on one surface 23A of the conversion substrate 23, a plurality of electrodes 24 and wiring patterns 25 corresponding thereto are arranged so as to be conductively connected to the through holes 26, respectively, and a solder resist 37 is provided at a predetermined position on the one surface 23A. Applied. On the other surface 23B of the conversion substrate 23, a predetermined number of dummy through holes and dummy bumps (both not shown) having the same bump height as the other end portion 26B of each through hole 26 are disposed.
[0029]
The mounting surface 40A of the main substrate 40 is provided with a plurality of electrodes 41 corresponding to the through holes 26 provided on the other surface 23B of the conversion substrate 23, but on the other surface 23B. A predetermined number of electrodes (hereinafter referred to as “dummy lands”) (not shown) are formed corresponding to the disposed dummy through holes.
[0030]
As a result, the other end 26B of each through hole 26 and each dummy through hole disposed on the other surface 23B of the conversion board 23 are mounted on the mounting surface 40A of the main board 40 while maintaining the same bump height. obtain. Thus, the connection between the conversion board 23 and the main board 40 can be reinforced to improve the reliability of the connection. A resist 43 is applied to a predetermined position on the mounting surface 40A of the main substrate 40.
[0031]
Incidentally, cream solder (not shown) is printed on each electrode 41 and each dummy land disposed on the mounting surface 40A of the main board 40, and each electrode is mounted by reflowing after mounting the CSP 20 on the main board 40. 41 and each solder bump melted in each dummy land can be joined to the other end portion 26B of each through-hole 26 and each dummy through-hole formed in the other surface 23B of the conversion substrate 23 corresponding thereto.
[0032]
In the above configuration, the CSP 20 flip-mounts the semiconductor chip 21 on one surface 23A of the conversion substrate 23 in which a plurality of through holes 26 are formed in a predetermined pattern, and then seals the semiconductor chip 21 by resin sealing. It is what was packaged.
[0033]
In this case, an electrode 24 is provided on one surface 23A of the conversion substrate 23 corresponding to each solder bump 22 of the semiconductor chip 21, and each electrode 24 is connected to one end of each through hole 26 via a wiring pattern 25. The portion 26A is conductively connected.
[0034]
The other surface 23B of each through hole 26 protrudes from the other surface 23B of the conversion substrate 23, and a plurality of dummy through holes 29 and dummy bumps 30A to 30D are formed in a predetermined pattern. The other end 26B of each through hole 26, each dummy through hole 29, and dummy bumps 30A to 30D correspond to each electrode 41 and each dummy land (not shown) disposed on the mounting surface 40A of the main board 40. Are arranged.
[0035]
Thereby, even if it does not carry out resin sealing after mounting CSP20 in the mounting surface 40A of the main board | substrate 40, the reliability in the connection between the said CSP20 and the main board | substrate 40 can be improved. Therefore, the CSP 20 can be easily removed from the main board 40, and thus the semiconductor chip 21 can be easily repaired and inspected.
[0036]
Further, in the CSP 20, a plurality of through holes 26 are provided in the conversion board 23, and the semiconductor chip 20 and the main board 40 are conductively connected through the through holes 26. It is not necessary to dispose a plurality of wiring patterns on the surface 23B, and thus the outer shape of the conversion substrate 23 can be formed to be approximately the same size as the outer shape of the semiconductor chip 20.
[0037]
Furthermore, in the CSP 20, the distance from the other surface 23B of the other end portion 26B of the plurality of through holes 26 arranged on the other surface 23B of the conversion substrate 23 is determined as the one surface of the corresponding one end portion 26A of each through hole 26. By forming it so as to be longer than the distance from 23A, when the CSP 20 is mounted on the main board 40, it is possible to prevent the occurrence of a bridge between adjacent electrodes. Further, the gear can be expanded between the other surface 23B of the conversion substrate 23 and the mounting surface 40A of the main substrate 40. As a result, damage to the semiconductor chip 21 due to heat stress can be prevented.
[0038]
Further, in the CSP 20, a plurality of dummy through holes 29 and dummy bumps 30 </ b> A to 30 </ b> D having the same length as the other end portions 26 </ b> B of the plurality of through holes 26 disposed on the conversion substrate 23 are formed, whereby the mounting surface of the main substrate 40 is mounted. Only by providing each electrode 41 and each dummy land 42 corresponding to these in 40A, the connection between the conversion board | substrate 23 and the main board | substrate 40 can be reinforced, and the reliability of the said connection can be improved.
[0039]
Further, as a result, it is not necessary to prepare a dedicated facility for the CSP 20 in advance on the mounting surface 40A of the main board 40, and the time and economical loss in the process of mounting the CSP 20 on the main board 40 can be significantly reduced as compared with the conventional case. .
[0040]
According to the above configuration, the semiconductor chip 21 is conductively connected to each through hole 26 on one surface 23 of the conversion substrate 23 in which a plurality of through holes 26 are formed in a predetermined pattern, and then resin-sealed. Accordingly, the CSP 20 in which the semiconductor chip 21 is packaged is provided so that each through hole 26 protrudes from the other surface 23B of the conversion substrate 23 with a predetermined length and has the same length as each through hole 26. By forming the plurality of dummy through holes 29 and the dummy bumps 30A to 30D, the reliability of the connection to the main substrate 40 can be improved, and the size of the entire CSP 20 can be relatively reduced.
[0041]
(2) Second embodiment
FIG. 4 shows the CSP 50 in the second embodiment, and the semiconductor chip 51 is flip-chip mounted on the conversion substrate 53 as in the first embodiment. In this case, on the bonding surface 51A of the semiconductor chip 51, four solder bumps 52 are arranged in a predetermined pitch along the inner peripheral edge of the bonding surface 51A corresponding to a plurality of aluminum electrodes (not shown). It is installed.
[0042]
A plurality of through holes 54 are arranged on the conversion substrate 53 so as to correspond to the solder bumps 52 formed on the semiconductor chip 51 through the one surface 53A and the other surface 53B, respectively. After mounting the solder bumps 52 in an aligned state, they are joined by reflowing them.
[0043]
In this case, one end portion 54A and the other end portion 54B of each through hole 54 protrude from the one surface 53A and the other surface 53B of the conversion substrate 53, respectively, as in the first embodiment. Further, the first and second copper foils are respectively set such that the distance of the other end portion 54B from the other surface 53B of the conversion substrate 53 is relatively longer than the distance of the one end portion 54A from the one surface 53A of the conversion substrate 53. 55 and 56 are stretched.
[0044]
Further, the filling member 60 is filled and embedded in the through holes 54, and copper platings 57 and 58 each having a predetermined thickness are applied from both sides of the one end 54A and the other end 54B. The through hole 54 is closed. A solder resist 59 is applied to a predetermined position on one surface 53A of the conversion substrate 53.
[0045]
A plurality of electrodes 71 are disposed on the mounting surface 70 </ b> A of the main substrate 70 so as to correspond to the through holes 54 disposed on the other surface 53 </ b> B of the conversion substrate 53. As a result, the other end 54B of each through hole 54 and the dummy bumps 62A to 62D disposed on the other surface 53B of the conversion substrate 53 are mounted on the mounting surface 70A of the main substrate 70 while maintaining the same bump height. Can be done. Thus, the connection between the conversion substrate 53 and the main substrate 70 can be reinforced to improve the reliability of the connection. A resist 72 is applied to a predetermined position on the mounting surface 70A of the main substrate 70.
[0046]
Incidentally, cream solder (not shown) is printed on each electrode 71 disposed on the mounting surface 70A of the main board 70, and the CSP 50 is melted at each electrode 71 by reflowing after being mounted on the main board 70. Each solder bump can be joined to the other end portion 54B of each through hole 54 formed on the other surface 53B of the conversion substrate 53 corresponding thereto.
[0047]
Here, in FIGS. 5A and 5B, one surface 53A and the other surface 53B of the conversion substrate 53 are shown. In the center of the conversion substrate 53, a resin injection hole 61 having a predetermined hole diameter is formed through one surface 53A and the other surface 53B, and a sealing member (not shown) is injected through the resin injection hole 61. It is made so that. Dummy bumps 62A to 62D are formed at the four corners of the other surface 53B of the conversion substrate 53 so as to maintain a predetermined bump height.
[0048]
According to the above configuration, the semiconductor chip 51 is conductively connected to each through hole 54 on the one surface 53A of the conversion substrate 53 in which a plurality of through holes 54 are formed in a predetermined pattern, and then resin-sealed. Accordingly, the CSP 50 packaged with the semiconductor chip 51 is provided, and the through holes 54 protrude from the other surface 53B of the conversion substrate 53 with a predetermined length, and have the same length as the through holes 54. By forming the plurality of dummy bumps 62A to 62D, the reliability of the connection to the main substrate 70 can be improved, and the overall size of the CSP 50 can be made relatively small.
[0049]
Further, in the CSP 50, the plurality of through holes 54 provided in the conversion substrate 53 are provided so as to directly correspond to the solder bumps 52 formed in the semiconductor chip 51, respectively. The CSP 20 can be significantly reduced in size.
[0050]
(3) Other embodiments
In the first and second embodiments, the arrangement patterns of the plurality of through holes 26 and 54 arranged on the conversion substrates 23 and 53 are shown in FIGS. 2A and 2B, and FIGS. Although the case where it was shown to B) was described, this invention is not restricted to this, If it can respond to the several solder bump formed in the semiconductor chip, it will arrange | position with other various arrangement | sequence patterns. Anyway.
[0051]
In the first and second embodiments, the arrangement patterns of the plurality of dummy through holes 29 and the dummy bumps 30A to 30D and 62A to 62D arranged on the other surfaces 23B and 53B of the conversion substrates 23 and 53 are shown in FIG. (B) and FIG. 5 (B) have been described. However, the present invention is not limited to this, and other various arrangement patterns may be used. Further, if the connection stability can be secured without the dummy through hole 29 and the dummy bumps 30A to 30D and 62A to 62D, some or all of the dummy bumps may not be formed.
[0052]
Further, in the first and second embodiments, the case where the plurality of solder bumps 22 and 52 are formed on the joining surfaces 21A and 51A of the semiconductor chips 21 and 51 in the CSPs 20 and 50 has been described, but the present invention is not limited to this. Instead, other metal bumps such as gold bumps may be used, and various other stud bumps may be used.
[0053]
Further, in the first and second embodiments, the case where the conversion substrates 23 and 53 are double-sided substrates in the CSPs 20 and 50 has been described. However, the present invention is not limited to this, for example, each surface 23A of the conversion substrates 23 and 53 and It may be used as a multilayer substrate in which a photovia layer is further laminated on 53A.
[0054]
Further, in the first and second embodiments, the filling members 36 and 60 are filled and embedded in the holes of the plurality of through holes 26 and 54 disposed in the conversion substrates 23 and 53, respectively. As described above, the present invention is not limited to this, and the inside of each of the plurality of through holes 26 and 54 may be left hollow without being filled. In this case, since the solder for joining enters the through holes 26 and 54, the occurrence rate of the bridge can be relatively reduced when mounting on the main boards 40 and 70 even when the solder supply amount is large. In short, various members other than the through holes may be applied as long as they are conductive members provided so as to penetrate the one surfaces 23A and 53A and the other surfaces 23A and 53A of the conversion substrates 23 and 53.
[0055]
Further, in the first and second embodiments, the case where the resin injection holes 27 and 61 are formed in the central portions of the conversion substrates 23 and 53 has been described, but the present invention is not limited thereto, and the resin injection holes 27 are not limited thereto. And 61 need not be drilled. In this case, various resins are injected from the outside between the semiconductor chips 21 and 51 and the conversion substrates 23 and 53 in the CSPs 20 and 50.
[0056]
【The invention's effect】
As described above, according to the present invention, a plurality of first electrodes are provided on one surface of the conversion substrate so as to correspond to the respective electrodes of the semiconductor chip, and a corresponding one of the first electrodes is provided on the other surface of the conversion substrate. In a semiconductor device in which a plurality of second electrodes that are conductively connected between one surface and the other surface through through holes are provided, and a semiconductor chip is flip-chip mounted on one surface of the conversion substrate. The electrode and the second electrode are filled with a filling member made of resin or conductive paste inside the hole of the through hole, and then the hole of the through hole is closed by applying copper plating from both sides. By making the film thickness of each second electrode provided on the other surface of the conversion substrate thicker than the film thickness of each first electrode provided on one surface of the conversion substrate, Just that much conversion board It is possible to expand the gap between the other surface and the mounting surface of the main board. As a result, damage to the semiconductor chip due to heat stress can be prevented, and thus the reliability of the connection to the main board on which the semiconductor device is mounted is reliable. Can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a configuration of a CSP according to a first embodiment.
FIG. 2 is a plan view showing a configuration of a CSP conversion substrate according to the first embodiment.
FIG. 3 is a partial cross-sectional view of the CSP according to the first embodiment when mounted on the main board.
FIG. 4 is a partial cross-sectional view of the CSP according to the second embodiment when mounted on a main board.
FIG. 5 is a plan view showing a configuration of a CSP conversion board according to a second embodiment.
6A and 6B are a plan view and a cross-sectional view showing a configuration of a conventional flip-chip mounting substrate.
7A and 7B are a plan view and a cross-sectional view showing a configuration of a conventional flip-chip mounting board.
[Explanation of symbols]
20, 50 ... CSP, 21, 51 ... Semiconductor chip, 22, 52 ... Solder bump, 23, 53 ... Conversion board, 26, 54 ... Through hole, 27, 61 ... Resin injection hole, 28 ... ... Sealing member, 29 ... dummy through-hole, 30A-30D, 62A-62D ... dummy bump, 32, 55 ... first copper foil, 33, 56 ... second copper foil, 40, 70 ... Main substrate, 41, 71 ... electrodes.

Claims (3)

変換基板の一面に半導体チツプの各電極に対応させて複数の第１の電極が設けられると共に、上記変換基板の他面に各上記第１の電極のうちの対応するものとそれぞれ上記一面及び上記他面間をスルーホールを介して導通接続された複数の第２の電極が設けられ、かつ上記変換基板の上記一面に上記半導体チツプがフリツプチツプ実装されてなる半導体装置において、
上記第１の電極及び上記第２の電極は、
上記スルーホールの孔内部に樹脂又は導電性のペーストでなる充填部材を充填して埋設した後、当該スルーホールの孔を両側から銅メツキを塗布して閉塞するようにして形成され、
上記変換基板の上記一面に設けられた各上記第１の電極の膜厚よりも、当該変換基板の上記他面に設けられた各上記第２の電極の膜厚を厚くするようにした
ことを特徴とする半導体装置。Together so as to correspond to the electrodes of the semiconductor chip a plurality of first electrodes provided on one surface of the converter board, corresponding ones respectively said first surface and said one of the said first electrode on the other side of the converter board In a semiconductor device in which a plurality of second electrodes that are conductively connected to each other through through holes are provided, and the semiconductor chip is flip- chip mounted on the one surface of the conversion substrate.
The first electrode and the second electrode are:
After filling and filling a filling member made of resin or conductive paste inside the hole of the through hole, the hole of the through hole is formed so as to be closed by applying copper plating from both sides,
Than the film thickness of each of the first electrode provided on the one surface of the converter board, that it has to increase in the thickness of each said second electrode provided on the other surface of the converter board A featured semiconductor device. 上記回路基板の中央部に所定の径でなる孔を上記一面及び上記他面間を介して穿設した後、上記孔を介して封止部材を注入するようにした
ことを特徴とする請求項１に記載の半導体装置。 The hole having a predetermined diameter is formed in the central portion of the circuit board through the space between the one surface and the other surface, and then the sealing member is injected through the hole. 2. The semiconductor device according to 1. 上記回路基板の上記他面の各角部に、それぞれ金属バンプを各上記第２の電極の膜厚と同じ厚みで形成した
ことを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein metal bumps are formed at respective corners on the other surface of the circuit board to have the same thickness as that of the second electrodes .
JP35249295A 1995-12-30 1995-12-30 Semiconductor device Expired - Fee Related JP3685347B2 (en)

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