JP6917295B2 - Electronic component built-in board, sheet board - Google Patents

Electronic component built-in board, sheet board Download PDF

Info

Publication number
JP6917295B2
JP6917295B2 JP2017247790A JP2017247790A JP6917295B2 JP 6917295 B2 JP6917295 B2 JP 6917295B2 JP 2017247790 A JP2017247790 A JP 2017247790A JP 2017247790 A JP2017247790 A JP 2017247790A JP 6917295 B2 JP6917295 B2 JP 6917295B2
Authority
JP
Japan
Prior art keywords
substrate
electronic component
layer
upper substrate
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017247790A
Other languages
Japanese (ja)
Other versions
JP2019114686A (en
Inventor
悟志 松澤
悟志 松澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2017247790A priority Critical patent/JP6917295B2/en
Priority to US16/210,050 priority patent/US10727175B2/en
Publication of JP2019114686A publication Critical patent/JP2019114686A/en
Application granted granted Critical
Publication of JP6917295B2 publication Critical patent/JP6917295B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

電子部品内蔵基板、シート基板に関する。 Related to electronic component built-in boards and sheet boards.

従来、半導体チップ等の電子部品を有した基板の小型化や省スペース化等のため、半導体チップ等の電子部品が埋め込まれた所謂電子部品内蔵基板が提案されている。電子部品内蔵基板は、半導体チップが実装された第１の基板に、はんだボールを介して第２の基板が積層され、第１の基板と第２の基板との間を樹脂封止されている（例えば、特許文献１参照）。 Conventionally, a so-called electronic component-embedded substrate in which an electronic component such as a semiconductor chip is embedded has been proposed in order to reduce the size and space of a substrate having an electronic component such as a semiconductor chip. In the electronic component-embedded substrate, a second substrate is laminated on a first substrate on which a semiconductor chip is mounted via a solder ball, and a resin is sealed between the first substrate and the second substrate. (See, for example, Patent Document 1).

国際公開第２００７／０６９６０６号International Publication No. 2007/069606

ところで、第１の基板と第２の基板との間の間隔（Ｇａｐ）を狭くして電子部品内蔵基板を薄型化することが考えられる。すると、半導体チップと第２の基板との間に樹脂が十分に充填されず、半導体チップと第２の基板との間にボイドが発生する虞がある。ボイドが発生すると、例えば、ボイドが吸湿して膨張し、ボイドの近傍の樹脂に剥がれが生じる場合があり、電子部品内蔵基板の信頼性を低下させる。 By the way, it is conceivable to narrow the gap (Gap) between the first substrate and the second substrate to reduce the thickness of the electronic component built-in substrate. Then, the resin may not be sufficiently filled between the semiconductor chip and the second substrate, and voids may occur between the semiconductor chip and the second substrate. When a void is generated, for example, the void absorbs moisture and expands, and the resin in the vicinity of the void may be peeled off, which lowers the reliability of the electronic component built-in substrate.

本発明の一観点によれば、電子部品内蔵基板は、下基板と、前記下基板上に実装された電子部品と、前記下基板と前記電子部品との間に充填されたアンダーフィル樹脂と、前記電子部品及び前記下基板の上方に設けられた上基板と、前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、を有し、前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層とを有し、前記ソルダーレジスト層には、前記電子部品と対向する直上領域に先端が配置され、前記先端から、前記上基板の側面まで延びる複数の溝が形成され、複数の前記溝の互いの間隔が前記側面に向って徐々に広くなるように設定されている。 According to one aspect of the present invention, the electronic component built-in substrate includes a lower substrate, an electronic component mounted on the lower substrate, an underfill resin filled between the lower substrate and the electronic component, and the like. A substrate connecting member provided between the electronic component and the upper substrate provided above the lower substrate, the lower substrate and the upper substrate, and connecting the lower substrate and the upper substrate, and the lower substrate. The upper substrate has a sealing resin that is filled between the upper substrate and the electronic component and the substrate connecting member, and the upper substrate has a substrate main body and a solder formed on the lower surface of the substrate main body. and a resist layer, the said solder resist layer, before SL is disposed distal to the electronic component facing the region immediately above, from the tip, a plurality of grooves extending to the side surface of the substrate is formed, a plurality of the The distance between the grooves is set so as to gradually widen toward the side surface .

また、本発明の別の一観点によれば、シート基板は、複数の電子部品内蔵基板と、隣接する２つの前記電子部品内蔵基板の間に設定された切断領域と、を有し、前記電子部品内蔵基板は、下基板と、前記下基板上に実装された電子部品と、前記下基板と前記電子部品との間に充填されたアンダーフィル樹脂と、前記電子部品及び前記下基板の上方に設けられた上基板と、前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、を有し、前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層を有し、前記ソルダーレジスト層には、前記電子部品と対向する直上領域に先端が配置され、前記先端から、前記切断領域まで延びる複数の溝が形成され、複数の前記溝の互いの間隔が前記前記切断領域に向って徐々に広くなるように設定されている。 Further, according to another aspect of the present invention, the sheet substrate has a plurality of electronic component-embedded substrates and a cutting region set between two adjacent electronic component-embedded substrates, and the electronic components are included. The component-embedded substrate includes a lower substrate, an electronic component mounted on the lower substrate, an underfill resin filled between the lower substrate and the electronic component, and above the electronic component and the lower substrate. It is provided between the provided upper substrate, the lower substrate and the upper substrate, and is filled between the substrate connecting member which is provided between the lower substrate and the upper substrate and between the lower substrate and the upper substrate. The upper substrate has a substrate main body and a solder resist layer formed on the lower surface of the substrate main body, and has a sealing resin for sealing the electronic component and the substrate connecting member. the pre SL is disposed distal to the electronic component facing the region immediately above, from the tip, the cutting region is a plurality of grooves formed to extend up to, and mutual spacing of a plurality of said grooves toward said cutting area It is set to gradually widen.

本発明の一開示によれば、信頼性の低下を抑制できる。 According to one disclosure of the present invention, a decrease in reliability can be suppressed.

（ａ）は電子部品内蔵基板を示す概略断面図、（ｂ）は第２基板を示す概略平面図。(A) is a schematic cross-sectional view showing a substrate containing electronic components, and (b) is a schematic plan view showing a second substrate. （ａ）は上基板を形成するワーク基板を示す概略平面図、（ｂ）はワーク基板の概略断面図。(A) is a schematic plan view showing a work substrate forming an upper substrate, and (b) is a schematic cross-sectional view of the work substrate. （ａ）は封止樹脂形成後のシート基板を示す概略平面図、（ｂ）はシート基板の概略断面図。(A) is a schematic plan view showing the sheet substrate after forming the sealing resin, and (b) is a schematic cross-sectional view of the sheet substrate. （ａ）（ｂ）は比較例の電子部品内蔵基板を示す概略断面図、（ｃ）は本実施形態の電子部品内蔵基板の作用を示す概略平面図。(A) and (b) are schematic cross-sectional views showing an electronic component-embedded substrate of a comparative example, and (c) is a schematic plan view showing the operation of the electronic component-embedded substrate of the present embodiment. 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 図５の第２基板を含むワーク基板の一部を示す概略平面図。The schematic plan view which shows a part of the work board including the 2nd board of FIG. 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 変形例の第２基板を示す概略平面図。The schematic plan view which shows the 2nd substrate of a modification. 図９の第２基板を含むワーク基板の一部を示す概略平面図。The schematic plan view which shows a part of the work board including the 2nd board of FIG. 変形例のワーク基板を示す概略断面図。Schematic cross-sectional view showing a work substrate of a modified example. 変形例の電子部品内蔵基板を示す概略断面図。The schematic cross-sectional view which shows the electronic component built-in substrate of a modification.

以下、一実施形態を説明する。
なお、添付図面は、理解を容易にするために構成要素を拡大して示している場合がある。構成要素の寸法比率は実際のものと、または別の図面中のものと異なる場合がある。また、断面図では、理解を容易にするために、一部の構成要素のハッチングを省略している場合がある。 Hereinafter, one embodiment will be described.
In the attached drawings, the components may be enlarged for easy understanding. The dimensional ratios of the components may differ from the actual ones or those in another drawing. Further, in the cross-sectional view, hatching of some components may be omitted for easy understanding.

図１（ａ）に示すように、電子部品内蔵基板１は、下基板１０、上基板２０、半導体素子３１、アンダーフィル樹脂３２、基板接続部材４０、封止樹脂５０を有している。電子部品内蔵基板１において、下基板１０と上基板２０とが、下基板１０と上基板２０とを電気的に接続する基板接続部材４０を介して積層されている。 As shown in FIG. 1A, the electronic component built-in substrate 1 has a lower substrate 10, an upper substrate 20, a semiconductor element 31, an underfill resin 32, a substrate connecting member 40, and a sealing resin 50. In the electronic component built-in substrate 1, the lower substrate 10 and the upper substrate 20 are laminated via a substrate connecting member 40 that electrically connects the lower substrate 10 and the upper substrate 20.

下基板１０は、基板本体１１、配線層１２、ソルダーレジスト層１３、配線層１４、ソルダーレジスト層１５を有している。
配線層１２は、基板本体１１の上面に形成されている。配線層１４は、基板本体１１の下面に形成されている。配線層１２，１４の材料としては、例えば銅（Ｃｕ）等を用いることができる。 The lower substrate 10 has a substrate main body 11, a wiring layer 12, a solder resist layer 13, a wiring layer 14, and a solder resist layer 15.
The wiring layer 12 is formed on the upper surface of the substrate main body 11. The wiring layer 14 is formed on the lower surface of the substrate main body 11. As the material of the wiring layers 12 and 14, for example, copper (Cu) or the like can be used.

基板本体１１は、配線層１２と配線層１４とを相互に電気的に接続する構造を有していれば十分である。このため、基板本体１１の内部には配線層が形成されていてもよく、配線層が形成されていなくてもよい。なお、基板本体１１の内部に配線層が形成される場合には、複数の配線層が絶縁層を介して積層され、絶縁層に形成されたビアと配線層によって上記配線層１２と配線層１４を電気的に接続する。内部に形成される配線層やビアの材料としては、たとえば銅や銅合金を用いることができる。絶縁層の材料としては、たとえばエポキシ樹脂やポリイミド樹脂などの絶縁性樹脂、又はこれら樹脂にシリカやアルミナ等のフィラーを混入した樹脂材を用いることができる。基板本体１１としては、例えばコア基板を有するコア付きビルドアップ基板やコア基板を有さないコアレス基板等を用いることができる。また、基板本体１１として、シリコン基板やセラミック基板等を用いてもよい。 It is sufficient that the substrate main body 11 has a structure in which the wiring layer 12 and the wiring layer 14 are electrically connected to each other. Therefore, the wiring layer may or may not be formed inside the substrate main body 11. When a wiring layer is formed inside the substrate main body 11, a plurality of wiring layers are laminated via an insulating layer, and the wiring layer 12 and the wiring layer 14 are formed by vias and wiring layers formed in the insulating layer. Electrically connect. As the material of the wiring layer and vias formed inside, for example, copper or a copper alloy can be used. As the material of the insulating layer, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed with these resins can be used. As the substrate main body 11, for example, a build-up substrate with a core having a core substrate, a coreless substrate without a core substrate, or the like can be used. Further, as the substrate main body 11, a silicon substrate, a ceramic substrate, or the like may be used.

ソルダーレジスト層１３は、基板本体１１の上面と配線層１２の一部を覆うように設けられている。ソルダーレジスト層１３は、配線層１２の一部をパッド１６として露出する開口部１３Ｙと、配線層１２の一部を接続パッド１７として露出する開口部１３Ｘとを有している。ソルダーレジスト層１３の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。 The solder resist layer 13 is provided so as to cover the upper surface of the substrate main body 11 and a part of the wiring layer 12. The solder resist layer 13 has an opening 13Y that exposes a part of the wiring layer 12 as a pad 16 and an opening 13X that exposes a part of the wiring layer 12 as a connection pad 17. As the material of the solder resist layer 13, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used.

なお、必要に応じて、開口部１３Ｘ，１３Ｙから露出する配線層１２上にＯＳＰ（Organic Solderability Preservative）処理を施してＯＳＰ膜を形成し、そのＯＳＰ膜に上記半導体素子３１を接続するようにしてもよい。また、開口部１３Ｘ，１３Ｙから露出する配線層１２上に金属層を形成してもよい。金属層の例としては、金（Ａｕ）層や、ニッケル（Ｎｉ）層／Ａｕ層（配線層１２上にＮｉ層とＡｕ層をこの順番で積層した金属層）や、Ｎｉ層／パラジウム（Ｐｄ）層／Ａｕ層（配線層１２上にＮｉ層とＰｄ層とＡｕ層をこの順番で積層した金属層）などを挙げることができる。これらＮｉ層、Ａｕ層、Ｐｄ層としては、例えば無電解めっき法により形成された金属層（無電解めっき金属層）を用いることができる。また、上記Ａｕ層はＡｕ又はＡｕ合金からなる金属層、上記Ｎｉ層はＮｉ又はＮｉ合金からなる金属層、上記Ｐｄ層はＰｄ又はＰｄ合金からなる金属層である。 If necessary, an OSP (Organic Solderability Preservative) treatment is performed on the wiring layer 12 exposed from the openings 13X and 13Y to form an OSP film, and the semiconductor element 31 is connected to the OSP film. May be good. Further, a metal layer may be formed on the wiring layer 12 exposed from the openings 13X and 13Y. Examples of the metal layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order on a wiring layer 12), and a Ni layer / palladium (Pd). ) Layer / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order on a wiring layer 12) and the like. As the Ni layer, Au layer, and Pd layer, for example, a metal layer (electroless plating metal layer) formed by an electroless plating method can be used. The Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of a Pd or Pd alloy.

パッド１６は、バンプ３３を介して半導体素子３１に接続されている。すなわち、半導体素子３１は、下基板１０に対してフリップチップ実装されている。半導体素子３１としては、たとえばＣＰＵ(Central Processing Unit)チップやＧＰＵ(Graphics Processing Unit)チップなどのロジックチップを用いることができる。また、半導体素子３１としては、たとえばＤＲＡＭ(Dynamic Random Access Memory)チップ、ＳＲＡＭ(Static Random Access Memory)チップやフラッシュメモリチップなどのメモリチップを用いることもできる。 The pad 16 is connected to the semiconductor element 31 via a bump 33. That is, the semiconductor element 31 is flip-chip mounted on the lower substrate 10. As the semiconductor element 31, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used. Further, as the semiconductor element 31, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, a SRAM (Static Random Access Memory) chip, or a flash memory chip can be used.

バンプ３３としては、パッド１６上のバンプ、半導体素子３１のパッド上のバンプ、又は双方のバンプを用いることができる。バンプ３３としては、例えば、金バンプやはんだバンプを用いることができる。はんだバンプの材料としては、例えば、鉛（Ｐｂ）を含む合金、錫（Ｓｎ）とＡｕの合金、ＳｎとＣｕの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等を用いることができる。 As the bump 33, a bump on the pad 16, a bump on the pad of the semiconductor element 31, or both bumps can be used. As the bump 33, for example, a gold bump or a solder bump can be used. As the material of the solder bump, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn and Ag and Cu, and the like can be used. can.

なお、下基板１０に半導体素子３１を実装したが、これに限らず、他の電子部品（例えば、キャパシタ、インダクタ等）を下基板１０に実装してもよい。また、複数の電子部品を下基板１０に実装してもよい。 Although the semiconductor element 31 is mounted on the lower substrate 10, the present invention is not limited to this, and other electronic components (for example, capacitors, inductors, etc.) may be mounted on the lower substrate 10. Further, a plurality of electronic components may be mounted on the lower substrate 10.

アンダーフィル樹脂３２は、下基板１０の上面と半導体素子３１との間に充填されている。アンダーフィル樹脂３２の材料としては、例えばエポキシ樹脂などの絶縁性樹脂を用いることができる。 The underfill resin 32 is filled between the upper surface of the lower substrate 10 and the semiconductor element 31. As the material of the underfill resin 32, an insulating resin such as an epoxy resin can be used.

ソルダーレジスト層１５は、基板本体１１の下面と配線層１４の一部を覆うように形成されている。ソルダーレジスト層１５は、配線層１４の一部を外部接続パッド１８として露出する開口部１５Ｘを有している。ソルダーレジスト層１５の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。 The solder resist layer 15 is formed so as to cover the lower surface of the substrate main body 11 and a part of the wiring layer 14. The solder resist layer 15 has an opening 15X that exposes a part of the wiring layer 14 as an external connection pad 18. As the material of the solder resist layer 15, an insulating resin such as an epoxy resin or an acrylic resin can be used.

外部接続パッド１８には、この電子部品内蔵基板１をマザーボード等の実装基板（図示略）に実装する際に使用される外部接続端子６０が接続されている。外部接続端子６０は、例えば、はんだボールである。なお、外部接続端子６０として、はんだバンプやリードピン等を外部接続パッド１８に接続してもよい。 An external connection terminal 60 used when mounting the electronic component built-in board 1 on a mounting board (not shown) such as a motherboard is connected to the external connection pad 18. The external connection terminal 60 is, for example, a solder ball. As the external connection terminal 60, a solder bump, a lead pin, or the like may be connected to the external connection pad 18.

なお、必要に応じて、ソルダーレジスト層１５の開口部１５Ｘから露出する配線層１４の表面にＯＳＰ処理を施してＯＳＰ膜を形成し、そのＯＳＰ膜に外部接続端子６０を接続してもよい。また、開口部１５Ｘから露出する配線層１４の表面に金属層を形成し、その金属層に外部接続端子６０を接続してもよい。金属層の例としては、Ａｕ層や、Ｎｉ層／Ａｕ層（配線層１４の表面にＮｉ層とＡｕ層をこの順番で積層した金属層）、Ｎｉ層／Ｐｄ層／Ａｕ層（配線層１４の表面にＮｉ層とＰｄ層とＡｕ層をこの順番で積層した金属層）などを挙げることができる。なお、開口部１５Ｘから露出する配線層１４（あるいは、配線層１４上にＯＳＰ膜や金属層が形成されている場合には、それらＯＳＰ膜又は金属層）自体を、外部接続端子としてもよい。 If necessary, the surface of the wiring layer 14 exposed from the opening 15X of the solder resist layer 15 may be subjected to OSP treatment to form an OSP film, and the external connection terminal 60 may be connected to the OSP film. Further, a metal layer may be formed on the surface of the wiring layer 14 exposed from the opening 15X, and the external connection terminal 60 may be connected to the metal layer. Examples of the metal layer include an Au layer, a Ni layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order on the surface of the wiring layer 14), and a Ni layer / Pd layer / Au layer (wiring layer 14). A metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order on the surface of the above) and the like can be mentioned. The wiring layer 14 exposed from the opening 15X (or, if an OSP film or a metal layer is formed on the wiring layer 14, the OSP film or the metal layer) itself may be used as an external connection terminal.

上基板２０は、基板本体２１、ソルダーレジスト層２３、配線層２４、ソルダーレジスト層２５を有している。
ソルダーレジスト層２３は、基板本体２１の上面を覆うように設けられている。ソルダーレジスト層２３の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。 The upper substrate 20 has a substrate main body 21, a solder resist layer 23, a wiring layer 24, and a solder resist layer 25.
The solder resist layer 23 is provided so as to cover the upper surface of the substrate main body 21. As the material of the solder resist layer 23, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used.

なお、上基板２０において、基板本体２１の上面に配線層が形成されていてもよい。その場合、ソルダーレジスト層２３に、配線層の一部をパッドとして露出する開口部を形成することもできる。そして、必要に応じて、ソルダーレジスト層２３から配線層にＩＳＰ膜や金属層を形成することもできる。 In the upper substrate 20, a wiring layer may be formed on the upper surface of the substrate main body 21. In that case, the solder resist layer 23 can be formed with an opening that exposes a part of the wiring layer as a pad. Then, if necessary, an ISP film or a metal layer can be formed from the solder resist layer 23 to the wiring layer.

配線層２４は、基板本体２１の下面に形成されている。配線層２４の材料としては、例えば銅（Ｃｕ）等を用いることができる。
基板本体２１としては、内部に配線層が形成されていてもよく、配線層が形成されていなくてもよい。なお、基板本体２１の内部に配線層が形成される場合には、複数の配線層が絶縁層を介して積層され、絶縁層に形成されたビアと配線層によって内部の配線層が配線層２４と電気的に接続される。内部に形成される配線層やビアの材料としては、たとえば銅や銅合金を用いることができる。絶縁層の材料としては、たとえばエポキシ樹脂やポリイミド樹脂などの絶縁性樹脂、又はこれら樹脂にシリカやアルミナ等のフィラーを混入した樹脂材を用いることができる。基板本体２１としては、例えばコア基板を有するコア付きビルドアップ基板やコア基板を有さないコアレス基板等を用いることができる。また、基板本体２１として、シリコン基板やセラミック基板等を用いてもよい。 The wiring layer 24 is formed on the lower surface of the substrate main body 21. As the material of the wiring layer 24, for example, copper (Cu) or the like can be used.
The substrate main body 21 may or may not have a wiring layer formed inside. When a wiring layer is formed inside the substrate main body 21, a plurality of wiring layers are laminated via an insulating layer, and the internal wiring layer is formed by the via and the wiring layer formed in the insulating layer to form the wiring layer 24. Is electrically connected to. As the material of the wiring layer and vias formed inside, for example, copper or a copper alloy can be used. As the material of the insulating layer, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which a filler such as silica or alumina is mixed with these resins can be used. As the substrate main body 21, for example, a build-up substrate with a core having a core substrate, a coreless substrate without a core substrate, or the like can be used. Further, as the substrate main body 21, a silicon substrate, a ceramic substrate, or the like may be used.

ソルダーレジスト層２５は、基板本体２１の下面と配線層２４の一部を覆うように形成されている。ソルダーレジスト層２５は、配線層２４の一部を接続パッド２６として露出する開口部２５Ｘと、後述する排出溝２７を有している。ソルダーレジスト層２５の材料としては、たとえばエポキシ樹脂やアクリル樹脂などの絶縁性樹脂を用いることができる。 The solder resist layer 25 is formed so as to cover the lower surface of the substrate main body 21 and a part of the wiring layer 24. The solder resist layer 25 has an opening 25X that exposes a part of the wiring layer 24 as a connection pad 26, and a discharge groove 27 that will be described later. As the material of the solder resist layer 25, for example, an insulating resin such as an epoxy resin or an acrylic resin can be used.

なお、必要に応じて、ソルダーレジスト層２５の開口部２５Ｘから露出する配線層２４の表面にＯＳＰ処理を施してＯＳＰ膜を形成してもよい。また、開口部２５Ｘから露出する配線層２４上に金属層を形成してもよい。金属層の例としては、Ａｕ層や、Ｎｉ層／Ａｕ層（配線層２４の表面にＮｉ層とＡｕ層をこの順番で積層した金属層）、Ｎｉ層／Ｐｄ層／Ａｕ層（配線層２４の表面にＮｉ層とＰｄ層とＡｕ層をこの順番で積層した金属層）などを挙げることができる。 If necessary, the surface of the wiring layer 24 exposed from the opening 25X of the solder resist layer 25 may be subjected to OSP treatment to form an OSP film. Further, a metal layer may be formed on the wiring layer 24 exposed from the opening 25X. Examples of the metal layer include an Au layer, a Ni layer / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order on the surface of the wiring layer 24), and a Ni layer / Pd layer / Au layer (wiring layer 24). A metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order on the surface of the above) and the like can be mentioned.

下基板１０の接続パッド１７は、基板接続部材４０を介して上基板２０の接続パッド２６に接続されている。
基板接続部材４０は、下基板１０と上基板２０とを電気的に接続する機能を有する。また、基板接続部材４０は、下基板１０と上基板２０との間に所定の間隔（離間距離，ギャップ）を規定値とする機能を有する。 The connection pad 17 of the lower substrate 10 is connected to the connection pad 26 of the upper substrate 20 via the substrate connection member 40.
The board connecting member 40 has a function of electrically connecting the lower board 10 and the upper board 20. Further, the substrate connecting member 40 has a function of setting a predetermined distance (separation distance, gap) between the lower substrate 10 and the upper substrate 20 as a specified value.

基板接続部材４０としては、例えばコア付きはんだボールを用いることができる。基板接続部材４０は、略球状のコア４１と、コア４１の外周面を被覆するはんだ４２とを有する。コア４１の材料としては、例えばＣｕ等の金属からなる金属コアや、樹脂からなる樹脂コアを用いることができる。はんだ４２としては、Ｐｂを含む合金、ＳｎとＣｕの合金、ＳｎとＳｂの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等のはんだ材料を用いることができる。 As the substrate connecting member 40, for example, a solder ball with a core can be used. The substrate connecting member 40 has a substantially spherical core 41 and a solder 42 that covers the outer peripheral surface of the core 41. As the material of the core 41, for example, a metal core made of a metal such as Cu or a resin core made of a resin can be used. As the solder 42, a solder material such as an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, and an alloy of Sn and Ag and Cu can be used.

なお、基板接続部材４０は、コア４１及びはんだ４２を備えたコア付きのはんだボールには限定されず、例えば、コアを有していないはんだボール等を用いることもできる。又、銅ポスト等の金属ポストや金バンプ等の金属バンプを用いることもできる。コアを有していない、はんだボール等を用いた場合には、電子部品内蔵基板１の製造時に、所定の治具を用いて、下基板１０と上基板２０との間隔を設定できる。 The substrate connecting member 40 is not limited to a solder ball with a core having a core 41 and a solder 42, and for example, a solder ball without a core can be used. Further, a metal post such as a copper post or a metal bump such as a gold bump can also be used. When a solder ball or the like having no core is used, the distance between the lower substrate 10 and the upper substrate 20 can be set by using a predetermined jig at the time of manufacturing the electronic component built-in substrate 1.

封止樹脂５０は、下基板１０と上基板２０との間の空間に充填されている。この封止樹脂５０は、半導体素子３１、基板接続部材４０、アンダーフィル樹脂３２を封止する。この封止樹脂５０により、上基板２０が下基板１０に対して固定される。封止樹脂５０は、下基板１０と上基板２０とを接着する接着剤として機能する。また、封止樹脂５０は、半導体素子３１、基板接続部材４０を保護する保護層として機能する。また、封止樹脂５０は、電子部品内蔵基板１全体の機械的強度を高める。 The sealing resin 50 is filled in the space between the lower substrate 10 and the upper substrate 20. The sealing resin 50 seals the semiconductor element 31, the substrate connecting member 40, and the underfill resin 32. The sealing resin 50 fixes the upper substrate 20 to the lower substrate 10. The sealing resin 50 functions as an adhesive for adhering the lower substrate 10 and the upper substrate 20. Further, the sealing resin 50 functions as a protective layer that protects the semiconductor element 31 and the substrate connecting member 40. Further, the sealing resin 50 enhances the mechanical strength of the entire electronic component-embedded substrate 1.

封止樹脂５０の材料としては、例えば、エポキシ系樹脂やポリイミド系樹脂などの絶縁性樹脂を用いることができる。また、封止樹脂５０の材料としては、例えば、エポキシ系樹脂やポリイミド系樹脂にシリカ等のフィラーを混入した樹脂材を用いることができる。フィラーとしては、シリカ以外に、例えば、酸化チタン、酸化アルミニウム、窒化アルミニウム、炭化珪素、チタン酸カルシウム、ゼオライト等の無機化合物、又は、有機化合物等を用いることができる。また、封止樹脂５０としては、例えば、トランスファーモールド法、コンプレッションモールド法やインジェクションモールド法などにより形成されたモールド樹脂を用いることができる。 As the material of the sealing resin 50, for example, an insulating resin such as an epoxy resin or a polyimide resin can be used. Further, as the material of the sealing resin 50, for example, a resin material in which a filler such as silica is mixed with an epoxy resin or a polyimide resin can be used. As the filler, for example, an inorganic compound such as titanium oxide, aluminum oxide, aluminum nitride, silicon carbide, calcium titanate, or zeolite, or an organic compound can be used in addition to silica. Further, as the sealing resin 50, for example, a molding resin formed by a transfer molding method, a compression molding method, an injection molding method, or the like can be used.

図１（ａ）に示すように、上基板２０において、封止樹脂５０により覆われるソルダーレジスト層２５には、複数の排出溝２７が形成されている。例えば、複数の排出溝２７は、基板本体２１の下面２１ｂを露出するように形成されている。なお、排出溝２７の深さをソルダーレジスト層２５の厚さよりも小さくして基板本体２１の下面２１ｂが薄いソルダーレジスト層２５により覆われるようにしてもよい。また、排出溝２７により、基板本体２１の下面に形成された配線層２４が露出されてもよい。 As shown in FIG. 1A, in the upper substrate 20, a plurality of discharge grooves 27 are formed in the solder resist layer 25 covered with the sealing resin 50. For example, the plurality of discharge grooves 27 are formed so as to expose the lower surface 21b of the substrate main body 21. The depth of the discharge groove 27 may be made smaller than the thickness of the solder resist layer 25 so that the lower surface 21b of the substrate main body 21 is covered with the thin solder resist layer 25. Further, the wiring layer 24 formed on the lower surface of the substrate main body 21 may be exposed by the discharge groove 27.

図１（ｂ）に示すように、上基板２０は、矩形状に形成されている。図１（ｂ）において、図１（ａ）の半導体素子３１と対向する直上領域Ａ１を一点鎖線にて示している。上基板２０のソルダーレジスト層２５は、接続パッド２６を露出する複数の開口部２５Ｘを有している。この開口部２５Ｘは、半導体素子３１より外側に形成されている。 As shown in FIG. 1B, the upper substrate 20 is formed in a rectangular shape. In FIG. 1 (b), the region A1 directly above the semiconductor element 31 of FIG. 1 (a) is shown by a alternate long and short dash line. The solder resist layer 25 of the upper substrate 20 has a plurality of openings 25X that expose the connection pad 26. The opening 25X is formed outside the semiconductor element 31.

上基板２０は、側面２０ａ，２０ｂ，２０ｃ，２０ｄを有している。側面２０ａ，２０ｂは、互いに対向する第１の側面対を構成し、側面２０ｃ，２０ｄは、互いに対向する第２の側面対を構成する。本実施形態において、開口部２５Ｘは、上基板２０の互いに対向する２対の側面２０ａ，２０ｂ，２０ｃ，２０ｄのうちの１対の側面２０ａ，２０ｂに沿って一列に配列されている。これらの開口部２５Ｘから露出する接続パッド２６に、図１（ａ）に示す基板接続部材４０が接続される。 The upper substrate 20 has side surfaces 20a, 20b, 20c, and 20d. The side surfaces 20a and 20b form a first side pair facing each other, and the side surfaces 20c and 20d form a second side pair facing each other. In this embodiment, the openings 25X are arranged in a row along a pair of side surfaces 20a, 20b of two pairs of side surfaces 20a, 20b, 20c, 20d of the upper substrate 20 facing each other. The substrate connecting member 40 shown in FIG. 1A is connected to the connection pad 26 exposed from these openings 25X.

複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１から、開口部２５Ｘの配列方向（図１（ｂ）において上方）に沿って延びるように形成されている。そして、複数の排出溝２７は、上基板２０の互いに対向する２対の辺のうち、上述の開口部２５Ｘが沿っていない１対の側面２０ｃ，２０ｄのうちの一方の側面２０ｄまで延びている。 The plurality of discharge grooves 27 are formed so as to extend from the region A1 directly above the semiconductor element 31 along the arrangement direction of the openings 25X (upper in FIG. 1B). The plurality of discharge grooves 27 extend to one side surface 20d of the pair of side surfaces 20c and 20d that the above-mentioned opening 25X does not follow among the two pairs of sides of the upper substrate 20 that face each other. ..

また、本実施形態において、複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１内の先端２７ａから側面２０ｄの端部２７ｂに向けて徐々に幅広となるように形成されている。そして、複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１に多くの排出溝２７を配置するように、側面２０ｄに向けて広がる放射状に形成されている。 Further, in the present embodiment, the plurality of discharge grooves 27 are formed so as to gradually widen from the tip 27a in the region A1 directly above the semiconductor element 31 toward the end 27b of the side surface 20d. The plurality of discharge grooves 27 are formed in a radial pattern extending toward the side surface 20d so that many discharge grooves 27 are arranged in the region A1 directly above the semiconductor element 31.

上述したように、図１（ａ）に示す封止樹脂５０は、半導体素子３１を実装し基板接続部材４０により互いに接続した下基板１０と上基板２０とを、例えば封止金型内に配設し、封止金型内に樹脂を注入して形成される。このとき、樹脂は、図１（ｂ）に示す上基板２０に対して下方から注入される。つまり、複数の排出溝２７は、幅が細い先端２７ａを樹脂の注入側として、その樹脂の注入方向に沿って幅広となるように形成されている。 As described above, in the sealing resin 50 shown in FIG. 1A, the lower substrate 10 and the upper substrate 20 on which the semiconductor element 31 is mounted and connected to each other by the substrate connecting member 40 are arranged in, for example, a sealing mold. It is formed by injecting resin into a sealing mold. At this time, the resin is injected from below into the upper substrate 20 shown in FIG. 1 (b). That is, the plurality of discharge grooves 27 are formed so as to be wide along the injection direction of the resin, with the narrow tip 27a as the injection side of the resin.

図２（ａ）及び図２（ｂ）は、上基板２０を形成するワーク基板１２０を示す。なお、図２（ａ）及び図２（ｂ）において、図１（ａ）に示す電子部品内蔵基板１の各部材を形成する部材等については同じ符号を付して説明する。 2 (a) and 2 (b) show the work substrate 120 forming the upper substrate 20. In addition, in FIG. 2A and FIG. 2B, the members and the like forming each member of the electronic component built-in substrate 1 shown in FIG. 1A will be described with the same reference numerals.

このワーク基板１２０は、複数（図２（ａ）では６つ）の上基板２０として個片化される領域（以下、単に上基板２０を用いる）を含む大判の基板である。
ワーク基板１２０には、上基板２０がマトリックス状（図２（ａ）では、２×３）に配置されている。ワーク基板１２０には、シート切断の工程において上基板２０を個片化するための切断領域Ａ２が設定されている。切断領域Ａ２は、各上基板２０を囲むように設定されている。 The work substrate 120 is a large-sized substrate including a plurality of regions (six in FIG. 2A) that are fragmented as the upper substrate 20 (hereinafter, the upper substrate 20 is simply used).
On the work substrate 120, the upper substrate 20 is arranged in a matrix (2 × 3 in FIG. 2A). The work substrate 120 is provided with a cutting region A2 for separating the upper substrate 20 into pieces in the sheet cutting process. The cutting region A2 is set so as to surround each upper substrate 20.

図２（ｂ）に示すように、ワーク基板１２０は、基板本体１２１と、基板本体１２１の下面のソルダーレジスト層１２５とを有している。なお、ワーク基板１２０は、上述の上基板２０の配線層２４に対応する配線層と、上基板２０のソルダーレジスト層２３に対応するソルダーレジスト層とを有しているが、図２（ｂ）では省略している。 As shown in FIG. 2B, the work substrate 120 has a substrate main body 121 and a solder resist layer 125 on the lower surface of the substrate main body 121. The work substrate 120 has a wiring layer corresponding to the wiring layer 24 of the upper substrate 20 and a solder resist layer corresponding to the solder resist layer 23 of the upper substrate 20. FIG. 2B I'm omitting it.

ソルダーレジスト層１２５には、上述したように、図１（ａ）に示す配線層２４の一部を接続パッド２６として露出する開口部２５Ｘと、直上領域Ａ１から延びる複数の排出溝２７が形成されている。ワーク基板１２０において、排出溝２７は、各上基板２０における直上領域Ａ１の内側から、各上基板２０の外側の切断領域Ａ２まで延びるように形成されている。排出溝２７と開口部２５Ｘは、例えば、フォトリソグラフィ法により形成される。 As described above, the solder resist layer 125 is formed with an opening 25X that exposes a part of the wiring layer 24 shown in FIG. 1A as a connection pad 26, and a plurality of discharge grooves 27 extending from the directly above region A1. ing. In the work substrate 120, the discharge groove 27 is formed so as to extend from the inside of the region A1 directly above the upper substrate 20 to the cutting region A2 outside the upper substrate 20. The discharge groove 27 and the opening 25X are formed by, for example, a photolithography method.

ワーク基板１２０は、側面１２０ａ，１２０ｂ，１２０ｃ，１２０ｄを有している。側面１２０ａ，１２０ｂは、互いに対向する第１の側面対を構成し、側面１２０ｃ，１２０ｄは、互いに対向する第２の側面対を構成する。本実施形態のワーク基板１２０において、開口部２５Ｘは、ワーク基板１２０の互いに対向する２対の側面１２０ａ，１２０ｂ，１２０ｃ，１２０ｄのうちの１対の側面１２０ａ，１２０ｂと平行に配列されている。ワーク基板１２０は、これらの開口部２５Ｘから露出する接続パッド２６を有している。 The work board 120 has side surfaces 120a, 120b, 120c, and 120d. The side surfaces 120a and 120b form a first side pair facing each other, and the side surfaces 120c and 120d form a second side pair facing each other. In the work substrate 120 of the present embodiment, the openings 25X are arranged in parallel with a pair of side surfaces 120a, 120b of two pairs of side surfaces 120a, 120b, 120c, 120d facing each other of the work substrate 120. The work substrate 120 has a connection pad 26 exposed from these openings 25X.

複数の排出溝２７は、図１に示す半導体素子３１の直上領域Ａ１から、開口部２５Ｘの配列方向（図２（ａ）において左右方向）に沿って延びるように形成されている。そして、複数の排出溝２７は、ワーク基板１２０の互いに対向する２対の辺のうち、上述の開口部２５Ｘが沿っていない１対の側面１２０ｃ，１２０ｄのうちの一方の側面１２０ｄに向って、隣接する上基板２０の間の切断領域Ａ２まで延びている。 The plurality of discharge grooves 27 are formed so as to extend from the region A1 directly above the semiconductor element 31 shown in FIG. 1 along the arrangement direction of the openings 25X (the left-right direction in FIG. 2A). Then, the plurality of discharge grooves 27 are directed toward one side surface 120d of the pair of side surfaces 120c and 120d that the above-mentioned opening 25X does not follow among the two pairs of sides of the work substrate 120 that face each other. It extends to the cutting region A2 between the adjacent upper substrates 20.

また、本実施形態のワーク基板１２０において、複数の排出溝２７は、図１（ａ）に示す半導体素子３１と対向する直上領域Ａ１内の先端２７ａから切断領域Ａ２の端部２７ｂに向けて徐々に幅広となるように形成されている。そして、複数の排出溝２７は、直上領域Ａ１に多くの排出溝２７を配置するように、側面１２０ｄ側の切断領域Ａ２に向けて広がる放射状に形成されている。 Further, in the work substrate 120 of the present embodiment, the plurality of discharge grooves 27 are gradually formed from the tip 27a in the region A1 directly above the semiconductor element 31 shown in FIG. 1A toward the end 27b of the cutting region A2. It is formed to be wide. The plurality of discharge grooves 27 are formed in a radial pattern extending toward the cutting region A2 on the side surface 120d side so that many discharge grooves 27 are arranged in the directly above region A1.

図３（ａ）及び図３（ｂ）は、シート切断前のシート基板１００を示す。シート基板１００には複数（図３（ａ）では６つ）の電子部品内蔵基板１がマトリックス状に形成されている。なお、図３（ａ）及び図３（ｂ）において、図１（ａ）に示す電子部品内蔵基板１の各部材を形成する部材等については同じ符号を付して説明する。なお、図３（ａ）及び図３（ｂ）では、図１（ａ）に示す半導体素子３１を接続するバンプ３３、アンダーフィル樹脂３２、等が省略されている。 3 (a) and 3 (b) show the sheet substrate 100 before cutting the sheet. A plurality of electronic component-embedded substrates 1 (six in FIG. 3A) are formed in a matrix on the sheet substrate 100. In addition, in FIGS. 3A and 3B, the members and the like forming each member of the electronic component built-in substrate 1 shown in FIG. 1A will be described with the same reference numerals. In addition, in FIG. 3A and FIG. 3B, the bump 33 connecting the semiconductor element 31 shown in FIG. 1A, the underfill resin 32, and the like are omitted.

このシート基板１００は、図２（ａ）及び図２（ｂ）に示すワーク基板１２０と、図１（ａ）に示す下基板１０を形成するワーク基板１１０とが、図３（ａ）に示す基板接続部材４０により接続されている。図３（ｂ）に示すように、下基板１０の上面に半導体素子３１が実装されている。上基板２０のソルダーレジスト層１２５に形成された排出溝２７は、半導体素子３１の直上領域から、一点鎖線にて示す切断領域Ａ２まで延びている。そして、下基板１０を形成するワーク基板１１０と、上基板２０を形成するワーク基板１２０の間に、封止樹脂５０が形成されている。 In the sheet substrate 100, the work substrate 120 shown in FIGS. 2 (a) and 2 (b) and the work substrate 110 forming the lower substrate 10 shown in FIG. 1 (a) are shown in FIG. 3 (a). It is connected by a board connecting member 40. As shown in FIG. 3B, the semiconductor element 31 is mounted on the upper surface of the lower substrate 10. The discharge groove 27 formed in the solder resist layer 125 of the upper substrate 20 extends from the region directly above the semiconductor element 31 to the cutting region A2 indicated by the alternate long and short dash line. Then, the sealing resin 50 is formed between the work substrate 110 forming the lower substrate 10 and the work substrate 120 forming the upper substrate 20.

封止樹脂５０は、半導体素子３１を実装し基板接続部材４０により互いに接続したワーク基板１１０と上述のワーク基板１２０とを、例えば封止金型内に配設し、封止金型内に樹脂を注入して形成される。このとき、樹脂は、図３（ａ）に示すように、ワーク基板１２０に対して側面１２０ｃの側から注入される。つまり、複数の排出溝２７は、幅が細い先端２７ａを樹脂の注入側として、その樹脂の注入方向にそって幅広となるように形成されている。 In the sealing resin 50, the work substrate 110 on which the semiconductor element 31 is mounted and connected to each other by the substrate connecting member 40 and the above-mentioned work substrate 120 are arranged, for example, in a sealing mold, and the resin is formed in the sealing mold. Is formed by injecting. At this time, as shown in FIG. 3A, the resin is injected from the side surface 120c with respect to the work substrate 120. That is, the plurality of discharge grooves 27 are formed so as to be wide along the injection direction of the resin, with the narrow tip 27a as the injection side of the resin.

封止樹脂５０を形成したシート基板１００は、シート切断にて切断領域Ａ２が切断され、図１（ａ）に示す電子部品内蔵基板１が形成される。
（作用）
図１（ａ）に示すように、電子部品内蔵基板１は、下基板１０と上基板２０とを有している。下基板１０には半導体素子３１が実装されている。上基板２０は下基板１０の上方に配置され、基板接続部材４０により接続されている。下基板１０と上基板２０との間には、半導体素子３１と基板接続部材４０を封止する封止樹脂５０が形成されている。上基板２０は、基板本体２１と、基板本体２１の下面２１ｂに形成されたソルダーレジスト層２５とを有し、ソルダーレジスト層２５には、少なくとも半導体素子３１と対向する直上領域Ａ１から、上基板２０の側面２０ｄまで延びる排出溝２７が形成されている。この排出溝２７により、封止樹脂５０の形成時に生じるボイドの残存を抑制する。これを、比較例と比較して説明する。 In the sheet substrate 100 on which the sealing resin 50 is formed, the cutting region A2 is cut by sheet cutting, and the electronic component built-in substrate 1 shown in FIG. 1A is formed.
(Action)
As shown in FIG. 1A, the electronic component built-in substrate 1 has a lower substrate 10 and an upper substrate 20. A semiconductor element 31 is mounted on the lower substrate 10. The upper substrate 20 is arranged above the lower substrate 10 and is connected by a substrate connecting member 40. A sealing resin 50 for sealing the semiconductor element 31 and the substrate connecting member 40 is formed between the lower substrate 10 and the upper substrate 20. The upper substrate 20 has a substrate main body 21 and a solder resist layer 25 formed on the lower surface 21b of the substrate main body 21, and the solder resist layer 25 has an upper substrate from at least a region A1 directly above the semiconductor element 31. A discharge groove 27 extending to the side surface 20d of 20 is formed. The discharge groove 27 suppresses the residual voids generated when the sealing resin 50 is formed. This will be described in comparison with a comparative example.

図４（ａ）、図４（ｂ）は、比較例の電子部品内蔵基板２００，２１０を示す。
図４（ａ）に示す電子部品内蔵基板２００は、下基板１０と上基板２０との間の距離（ギャップ）は、半導体素子３１と上基板２０との間に封止樹脂５０を十分に充填するように設定されている。図４（ｂ）に示す電子部品内蔵基板２１０は、小型化のため、図４（ａ）に示す電子部品内蔵基板２００のギャップＧ１と比べ、下基板１０と上基板２０との間のギャップＧ２が狭く設定されている。この電子部品内蔵基板２１０では、半導体素子３１と上基板２０との間に十分に封止樹脂５０が充填されず、上基板２０の下面にボイド（気泡）Ｂ１が発生する。 4 (a) and 4 (b) show the electronic component built-in substrates 200 and 210 of the comparative example.
In the electronic component-embedded substrate 200 shown in FIG. 4A, the distance (gap) between the lower substrate 10 and the upper substrate 20 is such that the sealing resin 50 is sufficiently filled between the semiconductor element 31 and the upper substrate 20. It is set to do. The electronic component-embedded substrate 210 shown in FIG. 4B has a gap G2 between the lower substrate 10 and the upper substrate 20 as compared with the gap G1 of the electronic component-embedded substrate 200 shown in FIG. 4A for miniaturization. Is set narrowly. In the electronic component-embedded substrate 210 , the sealing resin 50 is not sufficiently filled between the semiconductor element 31 and the upper substrate 20, and voids (bubbles) B1 are generated on the lower surface of the upper substrate 20.

図４（ｃ）は、図３（ａ）に示すシート基板１００の一部を示す。なお、図４（ｃ）では、上基板２０を形成するワーク基板１２０を、ソルダーレジスト層１２５の側から示している。このワーク基板１２０と、図３（ｂ）に示す下基板１０を形成するワーク基板１１０との間に封止樹脂５０を形成する。封止樹脂５０は、封止金型内において、図４（ｃ）に示すワーク基板１２０の左型から注入される。このとき、図４（ｂ）に示す電子部品内蔵基板２１０と同様に、ボイドＢ１が発生する場合がある。ボイドＢ１は、上基板２０の下面、つまり排出溝２７に入り、注入される封止樹脂５０によって排出溝２７内を移動する。そして、ボイドＢ１は、切断領域Ａ２まで延びる排出溝２７の端部２７ｂに留まる。封止樹脂５０を硬化した後、この切断領域Ａ２を切断して上基板２０を含む電子部品内蔵基板１が個片化される。これにより、ボイドの残存が抑制された電子部品内蔵基板１が得られる。 FIG. 4C shows a part of the sheet substrate 100 shown in FIG. 3A. In FIG. 4C, the work substrate 120 forming the upper substrate 20 is shown from the side of the solder resist layer 125. A sealing resin 50 is formed between the work substrate 120 and the work substrate 110 forming the lower substrate 10 shown in FIG. 3 (b). The sealing resin 50 is injected into the sealing mold from the left mold of the work substrate 120 shown in FIG. 4 (c). At this time, the void B1 may be generated as in the case of the electronic component built-in substrate 210 shown in FIG. 4 (b). The void B1 enters the lower surface of the upper substrate 20, that is, the discharge groove 27, and moves in the discharge groove 27 by the sealing resin 50 injected. Then, the void B1 stays at the end portion 27b of the discharge groove 27 extending to the cutting region A2. After the sealing resin 50 is cured, the cutting region A2 is cut to separate the electronic component-embedded substrate 1 including the upper substrate 20. As a result, the electronic component built-in substrate 1 in which the residual voids are suppressed can be obtained.

以上記述したように、本実施形態によれば、以下の効果を奏する。
（１）電子部品内蔵基板１は、下基板１０と上基板２０とを有している。下基板１０には半導体素子３１が実装されている。上基板２０は下基板１０の上方に配置され、基板接続部材４０により接続されている。下基板１０と上基板２０との間には、半導体素子３１と基板接続部材４０を封止する封止樹脂５０が形成されている。上基板２０は、基板本体２１と、基板本体２１の下面２１ｂに形成されたソルダーレジスト層２５とを有し、ソルダーレジスト層２５には、少なくとも半導体素子３１と対向する直上領域Ａ１から、上基板２０の側面２０ｄまで延びる排出溝２７が形成されている。 As described above, according to the present embodiment, the following effects are obtained.
(1) The electronic component built-in substrate 1 has a lower substrate 10 and an upper substrate 20. A semiconductor element 31 is mounted on the lower substrate 10. The upper substrate 20 is arranged above the lower substrate 10 and is connected by a substrate connecting member 40. A sealing resin 50 for sealing the semiconductor element 31 and the substrate connecting member 40 is formed between the lower substrate 10 and the upper substrate 20. The upper substrate 20 has a substrate main body 21 and a solder resist layer 25 formed on the lower surface 21b of the substrate main body 21, and the solder resist layer 25 has an upper substrate from at least a region A1 directly above the semiconductor element 31. A discharge groove 27 extending to the side surface 20d of 20 is formed.

この排出溝２７により、封止樹脂５０の形成時に生じるボイドＢ１は、注入される封止樹脂５０によって、半導体素子３１に対する直上領域Ａ１から上基板２０の側面２０ｄに向けて移動する。このため、ボイドＢ１の残存が抑制された電子部品内蔵基板１が得られる。ボイドＢ１は、近傍の樹脂の剥がれを生じさせ、信頼性を低下させる。これに対し、本実施形態の電子部品内蔵基板１は、ボイドＢ１の残存が抑制されるため、信頼性の低下を抑制できる。 The void B1 generated during the formation of the sealing resin 50 by the discharge groove 27 moves from the region A1 directly above the semiconductor element 31 toward the side surface 20d of the upper substrate 20 by the sealing resin 50 injected. Therefore, the electronic component built-in substrate 1 in which the residual void B1 is suppressed can be obtained. The void B1 causes peeling of the resin in the vicinity and lowers the reliability. On the other hand, in the electronic component built-in substrate 1 of the present embodiment, since the residual void B1 is suppressed, the decrease in reliability can be suppressed.

（２）複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１内の先端２７ａから側面２０ｄの端部２７ｂに向けて徐々に幅広となるように形成されている。従って、封止樹脂５０の形成工程において、複数のボイドＢ１が発生しても、端部２７ｂが幅広に形成されているため、その端部２７ｂに続く切断領域Ａ２に多くのボイドＢ１を収容することができる。このため、ボイドＢ１が電子部品内蔵基板１の中に残存し難くなる。 (2) The plurality of discharge grooves 27 are formed so as to gradually widen from the tip 27a in the region A1 directly above the semiconductor element 31 toward the end 27b of the side surface 20d. Therefore, even if a plurality of voids B1 are generated in the process of forming the sealing resin 50, since the end portion 27b is formed to be wide, many voids B1 are accommodated in the cutting region A2 following the end portion 27b. be able to. Therefore, the void B1 is less likely to remain in the electronic component built-in substrate 1.

（３）複数の排出溝２７は、半導体素子３１と対向する直上領域Ａ１に多くの排出溝２７を配置するように、側面２０ｄに向けて広がる放射状に形成されている。これにより、半導体素子３１に対する直上領域Ａ１に多くの排出溝２７を形成することができ、よりボイドＢ１を排出し易くなる。 (3) The plurality of discharge grooves 27 are formed in a radial pattern extending toward the side surface 20d so that many discharge grooves 27 are arranged in the region A1 directly above the semiconductor element 31. As a result, many discharge grooves 27 can be formed in the region A1 directly above the semiconductor element 31, and the void B1 can be more easily discharged.

（変形例）
尚、上記各実施形態は、以下の態様で実施してもよい。
・上記実施形態に対し、上基板２０の構成や、排出溝２７の本数、形状、等を適宜変更してもよい。 (Modification example)
In addition, each of the above-mentioned embodiments may be carried out in the following embodiments.
-The configuration of the upper substrate 20, the number and shape of the discharge grooves 27, and the like may be appropriately changed with respect to the above embodiment.

図５は変形例の上基板３００を示し、図６は、図５の上基板３００を形成するワーク基板３１０の一部を示す。上基板３００のソルダーレジスト層３０１には、４つの排出溝３０２が形成されている。各排出溝３０２は、直上領域Ａ１から側面３００ｄまで延び、互いに平行に形成されている。 FIG. 5 shows the upper substrate 300 of the modified example, and FIG. 6 shows a part of the work substrate 310 forming the upper substrate 300 of FIG. Four discharge grooves 302 are formed in the solder resist layer 301 of the upper substrate 300. Each discharge groove 302 extends from the region A1 directly above to the side surface 300d and is formed parallel to each other.

図７に示すように、上基板３２０のソルダーレジスト層３２１には、５つの排出溝３２２が形成されている。これらの排出溝３２２は、上記実施形態と同様に、直上領域Ａ１から側面３２０ｄに向って放射状に形成されている。また、各排出溝３２２は、全体に亘って同一幅にて形成されている。 As shown in FIG. 7, five discharge grooves 322 are formed in the solder resist layer 321 of the upper substrate 320. Similar to the above embodiment, these discharge grooves 322 are formed radially from the directly above region A1 toward the side surface 320d. Further, each discharge groove 322 is formed to have the same width as a whole.

図８に示すように、上基板３３０のソルダーレジスト層３３１には、４つの排出溝３３２が形成されている。各排出溝３３２は、また、直上領域Ａ１から側面３３０ｄまで延び、互いに平行に形成されている。また、各排出溝３３２は、全体に亘って同一幅にて形成されている。 As shown in FIG. 8, four discharge grooves 332 are formed in the solder resist layer 331 of the upper substrate 330. Each discharge groove 332 also extends from the directly above region A1 to the side surface 330d and is formed parallel to each other. Further, each discharge groove 332 is formed to have the same width as a whole.

図９に示すように、上基板３４０のソルダーレジスト層３４１には、４つの排出溝３４２が形成されている。各排出溝３４２は、直上領域Ａ１を通り、一対の側面３４０ｃ，３４０ｄの一方の側面３４０ｃから他方の側面３４０ｄまで延び、互いに平行に形成されている。また、各排出溝３４２は、全体に亘って同一幅にて形成されている。 As shown in FIG. 9, four discharge grooves 342 are formed in the solder resist layer 341 of the upper substrate 340. Each discharge groove 342 passes through the region A1 directly above and extends from one side surface 340c of the pair of side surfaces 340c and 340d to the other side surface 340d, and is formed parallel to each other. Further, each discharge groove 342 is formed to have the same width as a whole.

図１０は、図９の上基板３４０を形成するワーク基板３５０の一部を示す。このワーク基板３５０において、排出溝３４２は、上基板３４０を通過して、側面３４０ｃ（上基板３４０となる領域の辺）の側の切断領域Ａ２から、側面３４０ｄの側の切断領域Ａ２まで延びるように形成されている。さらに、複数の上基板３４０に対して、排出溝３４２が連続するように形成されている。 FIG. 10 shows a part of the work substrate 350 forming the upper substrate 340 of FIG. In this work substrate 350, the discharge groove 342 passes through the upper substrate 340 and extends from the cutting region A2 on the side surface 340c (the side of the region to be the upper substrate 340) to the cutting region A2 on the side surface 340d. Is formed in. Further, the discharge grooves 342 are formed so as to be continuous with respect to the plurality of upper substrates 340.

図１１は、変形例のワーク基板３６０を示す。このワーク基板３６０は、図１（ａ）に示す上基板２０を形成するために用いられる。このワーク基板３６０のソルダーレジスト層３６１には、上基板２０の周囲の切断領域Ａ２に、環状の溝部３６２が形成されている。溝部３６２は、各上基板２０の排出溝２７と連続するように形成されている。 FIG. 11 shows a work board 360 of a modified example. This work substrate 360 is used to form the upper substrate 20 shown in FIG. 1 (a). In the solder resist layer 361 of the work substrate 360, an annular groove portion 362 is formed in the cutting region A2 around the upper substrate 20. The groove portion 362 is formed so as to be continuous with the discharge groove 27 of each upper substrate 20.

ソルダーレジスト層を複数の層構造とし、複数層の一部に排出溝を形成してもよい。一例を図１２に示す。
図１２に示すように、上基板３７０のソルダーレジスト層３７１は、基板本体２１の下面２１ｂと配線層２４の一部を覆う第１レジスト層３７２と、第１レジスト層３７２の一部を覆う第２レジスト層３７３を有している。第２レジスト層３７３には、第１レジスト層３７２の開口部３７２Ｘにより露出された接続パッド２６を露出する開口部３７３Ｘと、第１レジスト層３７２の下面３７２ｂの一部を露出するように形成された排出溝３７４とを有している。 The solder resist layer may have a plurality of layer structures, and a discharge groove may be formed in a part of the plurality of layers. An example is shown in FIG.
As shown in FIG. 12, the solder resist layer 371 of the upper substrate 370 has a first resist layer 372 that covers a part of the lower surface 21b of the substrate main body 21 and a wiring layer 24, and a first resist layer 372 that covers a part of the first resist layer 372. It has 2 resist layers 373. The second resist layer 373 is formed so as to expose an opening 373X that exposes the connection pad 26 exposed by the opening 372X of the first resist layer 372 and a part of the lower surface 372b of the first resist layer 372. It has a discharge groove 374.

・上記実施形態では、シート基板１００に複数の電子部品内蔵基板１をマトリックス状に形成したが、一列状に電子部品内蔵基板１を形成したシート基板としてもよい。
・接続パッド２６は上記実施形態の形状に限定されず、例えば、四角形状、つまり開口部２５Ｘの形状を四角形状としてもよい。 -In the above embodiment, a plurality of electronic component-embedded substrates 1 are formed in a matrix on the sheet substrate 100, but a sheet substrate in which the electronic component-embedded substrates 1 are formed in a row may be used.
The connection pad 26 is not limited to the shape of the above embodiment, and may have a quadrangular shape, that is, the shape of the opening 25X may be quadrangular.

・接続パッド２６の配列は上記実施形態に限定されず、例えば、ソルダーレジスト層２５に複数列の開口部２５Ｘを形成し、複数列の接続パッド２６を形成してもよい。また、半導体素子３１を囲むように開口部２５Ｘを形成して接続パッド２６を配列してもよい。 The arrangement of the connection pads 26 is not limited to the above embodiment, and for example, a plurality of rows of openings 25X may be formed in the solder resist layer 25 to form a plurality of rows of connection pads 26. Further, the connection pads 26 may be arranged by forming an opening 25X so as to surround the semiconductor element 31.

１０ 下基板
２０ 上基板
２１ 基板本体
２５ ソルダーレジスト層
２７ 排出溝（溝）
３１ 半導体素子（電子部品）
４０ 基板接続部材
１００ シート基板
１１０、１２０ ワーク基板
Ａ１ 直上領域
Ａ２ 切断領域 10 Lower board 20 Upper board 21 Board body 25 Solder resist layer 27 Discharge groove (groove)
31 Semiconductor elements (electronic components)
40 Board connection member 100 Sheet board 110, 120 Work board A1 Directly above area A2 Cutting area

Claims (5)

下基板と、
前記下基板上に実装された電子部品と、
前記下基板と前記電子部品との間に充填されたアンダーフィル樹脂と、
前記電子部品及び前記下基板の上方に設けられた上基板と、
前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、
前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、
を有し、
前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層とを有し、
前記ソルダーレジスト層には、前記電子部品と対向する直上領域に先端が配置され、前記先端から、前記上基板の側面まで延びる複数の溝が形成され、
複数の前記溝の互いの間隔が前記側面に向って徐々に広くなるように設定されていること、
を特徴とする電子部品内蔵基板。 With the lower board
The electronic components mounted on the lower board and
An underfill resin filled between the lower substrate and the electronic component,
An upper substrate provided above the electronic component and the lower substrate, and
A substrate connecting member provided between the lower substrate and the upper substrate and connecting the lower substrate and the upper substrate,
A sealing resin that is filled between the lower substrate and the upper substrate and seals the electronic component and the substrate connecting member.
Have,
The upper substrate has a substrate main body and a solder resist layer formed on the lower surface of the substrate main body.
Wherein the solder resist layer, before SL is disposed distal to the electronic component facing the region immediately above, from the tip, a plurality of grooves extending to the side surface of the substrate is formed,
The distance between the plurality of grooves is set so as to gradually increase toward the side surface.
A board with built-in electronic components. 前記上基板は、互いに対向する２対の第１の側面対及び第２の側面対を有し、
前記基板接続部材は、前記第１の側面対に沿って配列され、
前記溝は、前記第２の側面対のうちの一方の側面まで延びるように形成されていること、
を特徴とする請求項１に記載の電子部品内蔵基板。 The upper substrate has two pairs of first side surface pairs and second side surface pairs facing each other.
The substrate connecting members are arranged along the first side pair and are arranged.
The groove is formed so as to extend to one side surface of the second side surface pair.
The electronic component built-in substrate according to claim 1. 前記溝は、前記直上領域内の先端から前記側面に向けて徐々に幅広となるように形成されていること、を特徴とする請求項１又は２に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1 or 2, wherein the groove is formed so as to gradually widen from the tip end in the region directly above the region toward the side surface. 前記溝は、前記直上領域内の先端から前記側面まで等しい幅にて形成されていること、を特徴とする請求項１又は２に記載の電子部品内蔵基板。 The electronic component built-in substrate according to claim 1 or 2, wherein the groove is formed with the same width from the tip end in the region directly above to the side surface. 複数の電子部品内蔵基板と、
隣接する２つの前記電子部品内蔵基板の間に設定された切断領域と、
を有し、
前記電子部品内蔵基板は、
下基板と、
前記下基板上に実装された電子部品と、
前記下基板と前記電子部品との間に充填されたアンダーフィル樹脂と、
前記電子部品及び前記下基板の上方に設けられた上基板と、
前記下基板と前記上基板との間に設けられ、前記下基板と前記上基板とを接続する基板接続部材と、
前記下基板と前記上基板との間に充填され、前記電子部品及び前記基板接続部材を封止する封止樹脂と、
を有し、
前記上基板は、基板本体と、基板本体の下面に形成されたソルダーレジスト層とを有し、
前記ソルダーレジスト層には、前記電子部品と対向する直上領域に先端が配置され、前記先端から、前記切断領域まで延びる複数の溝が形成され、
複数の前記溝の互いの間隔が前記切断領域に向って徐々に広くなるように設定されていること、
を特徴とするシート基板。 With multiple boards with built-in electronic components
A cutting area set between two adjacent electronic component built-in substrates, and
Have,
The electronic component built-in substrate is
With the lower board
The electronic components mounted on the lower board and
An underfill resin filled between the lower substrate and the electronic component,
An upper substrate provided above the electronic component and the lower substrate, and
A substrate connecting member provided between the lower substrate and the upper substrate and connecting the lower substrate and the upper substrate,
A sealing resin that is filled between the lower substrate and the upper substrate and seals the electronic component and the substrate connecting member.
Have,
The upper substrate has a substrate main body and a solder resist layer formed on the lower surface of the substrate main body.
Wherein the solder resist layer, before SL is disposed distal to the electronic component facing the region immediately above, from the tip, a plurality of grooves extending to the cutting region is formed,
The distance between the plurality of grooves is set so as to gradually increase toward the cutting region .
A sheet substrate characterized by.
JP2017247790A 2017-12-25 2017-12-25 Electronic component built-in board, sheet board Active JP6917295B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017247790A JP6917295B2 (en) 2017-12-25 2017-12-25 Electronic component built-in board, sheet board
US16/210,050 US10727175B2 (en) 2017-12-25 2018-12-05 Electronic component-incorporating substrate and sheet substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017247790A JP6917295B2 (en) 2017-12-25 2017-12-25 Electronic component built-in board, sheet board

Publications (2)

Publication Number Publication Date
JP2019114686A JP2019114686A (en) 2019-07-11
JP6917295B2 true JP6917295B2 (en) 2021-08-11

Family

ID=66948974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017247790A Active JP6917295B2 (en) 2017-12-25 2017-12-25 Electronic component built-in board, sheet board

Country Status (2)

Country Link
US (1) US10727175B2 (en)
JP (1) JP6917295B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7163162B2 (en) * 2018-12-10 2022-10-31 新光電気工業株式会社 semiconductor package
US11637055B2 (en) * 2020-08-03 2023-04-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62287652A (en) * 1986-06-05 1987-12-14 Fujitsu Ltd Formation resin thin film for semiconductor device
JP3129960B2 (en) * 1996-02-27 2001-01-31 シャープ株式会社 Resin sealing structure of bare chip IC on FPC and method of manufacturing the same
EP1962342A4 (en) 2005-12-14 2010-09-01 Shinko Electric Ind Co Substrate with built-in chip and method for manufacturing substrate with built-in chip
JP2010147153A (en) * 2008-12-17 2010-07-01 Shinko Electric Ind Co Ltd Semiconductor apparatus and method of manufacturing the same
JP2011096865A (en) * 2009-10-30 2011-05-12 Sharp Corp Substrate member, module, electric equipment, and manufacturing method of modules
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
JP5785760B2 (en) * 2011-04-11 2015-09-30 日本特殊陶業株式会社 Component mounting board
JP6230794B2 (en) * 2013-01-31 2017-11-15 新光電気工業株式会社 Electronic component built-in substrate and manufacturing method thereof
US9947642B2 (en) * 2015-10-02 2018-04-17 Qualcomm Incorporated Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
JP6454384B2 (en) * 2017-08-01 2019-01-16 新光電気工業株式会社 Electronic component built-in substrate and manufacturing method thereof

Also Published As

Publication number Publication date
US10727175B2 (en) 2020-07-28
US20190198432A1 (en) 2019-06-27
JP2019114686A (en) 2019-07-11

Similar Documents

Publication Publication Date Title
CN110277381B (en) Semiconductor package and method for manufacturing the same
KR100800478B1 (en) Stack type semiconductor package and method of fabricating the same
TWI662668B (en) Fan-out semiconductor package and electronic device including the same
KR102492796B1 (en) Semiconductor package
JP6576383B2 (en) Fan-out semiconductor package
US10186500B2 (en) Semiconductor package and method of fabricating the same
US7663250B2 (en) Wafer level package and manufacturing method thereof
US8580608B2 (en) Fabrication method of package structure having embedded semiconductor component
US8994168B2 (en) Semiconductor package including radiation plate
JP6764666B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
US9935029B2 (en) Printed wiring board for package-on-package
US20150228571A1 (en) Wiring Substrate, Semiconductor Package, and Method for Manufacturing Semiconductor Package
US11569175B2 (en) Semiconductor package
CN111785695A (en) Semiconductor package
US11610864B2 (en) Chip package structure and method of forming the same
US20170358557A1 (en) Package-on-package structure and manufacturing method thereof
JP6917295B2 (en) Electronic component built-in board, sheet board
JP6713289B2 (en) Semiconductor device and method of manufacturing semiconductor device
KR102179167B1 (en) Semiconductor package
CN114551415A (en) Semiconductor package
CN113284862A (en) Semiconductor package
KR20220078131A (en) Hybrid semiconductor device and electronic device including the same
JP7338114B2 (en) Package substrate and its manufacturing method
US11894333B2 (en) Semiconductor package
US11764120B2 (en) Chip packaging structure and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200722

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210412

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210420

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210614

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210629

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210719

R150 Certificate of patent or registration of utility model

Ref document number: 6917295

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150