JP3129190B2 - Digital modulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulation circuit, and in particular, converts two systems of data corresponding to an I signal and a Q signal into analog signals, respectively, and converts the converted I and Q signals for quadrature modulation. The present invention relates to an output digital modulation circuit.

[0002]

2. Description of the Related Art Conventionally, this type of digital modulation circuit has
As described in JP-A-3-35640,
It is used for outputting an analog waveform according to a digital modulation method.

FIG. 8 is a block diagram showing an example of a conventional digital modulation circuit, in which the circuit described in the above publication is shown by functional blocks. In the figure, a conventional digital modulation circuit includes a digital signal processing unit 101 that outputs digital data corresponding to an I signal and a Q signal in analog waveforms, respectively, and converts the digital data output from the digital signal processing unit 101 into an analog signal. D / A converters 102 and 103 for conversion;
Each of these D / A converters is provided with a low pass filter (hereinafter abbreviated as LPF) 106 and 107 which receives the output of the corresponding D / A converter as an input.

Further, in the conventional digital modulation circuit, the I signal i 'and the Q signal q' having analog waveforms have the same amplitude and differ only in phase (phase difference π / 2). And Q signals are provided with gain / offset adjustment circuits 104 and 105, respectively. Then, by inputting a control signal x ′ to the gain / offset adjustment circuits 104 and 105, the gain and offset are adjusted.

In such a configuration, in the digital signal processing section 101, waveform data according to the digital modulation method is generated, and the waveform data is adjusted by the gain / offset adjustment circuits 104 and 105 to a value given by the control signal x '. After this adjustment, the D / A converters 102 and 103
The signals are converted into analog signals of the
Signal i by an analog signal for digital modulation through
'And the Q signal q'.

The generated I signal i 'and Q signal q'
Is input to a quadrature modulator (not shown) at the next stage to perform quadrature modulation.

[0007]

In the above-described conventional digital modulation circuit, until the spectrum characteristics of the output of the quadrature modulator at the next stage of the I signal i 'and the Q signal q' are improved,
By repeatedly inputting the control signal x ', the adjustment circuit 1
Adjustments according to 04 and 105 need to be made. For this reason, there is a disadvantage that it takes time to adjust the gain / offset.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a digital modulation circuit capable of shortening a gain / offset adjustment time.

[0009]

A digital modulation circuit according to the present invention has conversion means for respectively converting two types of data corresponding to an I signal and a Q signal into analog signals. A digital modulation circuit for outputting an I signal and a Q signal, wherein the digital modulation circuit is provided in common for the data of the two systems, and outputs a DC voltage value corresponding to a target amplitude value of each of the I signal and the Q signal. It is characterized by including data generating means for generating adjustment data according to the difference, and adjusting means for respectively adjusting the values of the two systems of data in accordance with the generated adjustment data.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.

A circuit provided in common for the two systems of data of the I signal and the Q signal generates adjustment data according to the difference between each amplitude value of the I signal and the Q signal and a target amplitude value. Then, the values of the two systems of data are adjusted in accordance with the generated adjustment data. There is no need to measure the spectrum characteristics, and the gain / offset can be adjusted with only one control, reducing the number of adjustment steps.

A / D conversion is performed alternately on I and Q signals by analog signals, the output data is subjected to arithmetic processing, a relative difference between the two signals is detected, and the result is used as a gain / offset adjustment circuit. Used as adjustment data. As a result, it is not necessary to measure the spectrum characteristic, and the gain / offset can be adjusted with a single control.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital modulation circuit according to a first embodiment of the present invention. Referring to FIG. 1, a digital modulation circuit according to a first embodiment of the present invention includes a digital signal processing unit 1 for outputting digital data corresponding to an I signal i and a Q signal q in analog waveform, respectively. D / A converters 4 and 5 for converting output digital data into analog signals, and LPFs 6 and 7 provided corresponding to the respective D / A converters and receiving the outputs of the corresponding D / A converters as inputs. It is composed of

In the digital modulation circuit according to the present embodiment, the I signal i and the Q signal q having analog waveforms have the same amplitude and differ only in phase (phase difference π / 2). Gain / offset adjustment circuits 2 and 3 are provided for the Q signal, respectively.

Further, the digital modulation circuit according to the present embodiment has a switch 8 for alternately inputting an I signal i and a Q signal q of an analog waveform, and an I signal i or Q input via the switch 8. A / D converter 9 for converting a signal into a digital value, and gain / offset control circuit 10 for generating data d and e for gain / offset adjustment circuits 2 and 3 based on the converted data
It is comprised including.

As shown, the switch 8, the A / D converter 9, and the gain / offset control circuit 10 are provided commonly to the I signal and the Q signal.
If two systems are provided for the I signal and the Q signal without providing them in common, the characteristics of the A / D converter and the like differ between the two systems, making it difficult to adjust the gain / offset. Also, providing these in common has the effect of reducing the amount of hardware.

In FIG. 1, during normal operation, a digital signal processing section 1 generates modulated waveform data according to a target modulation method, and a two-system gain / offset adjusting circuit 2
And give to 3. Gain / offset adjustment circuits 2 and 3
The data processed by the gain / offset value determined at the time of adjustment is supplied to D / A converters 4 and 5. The D / A converters 4 and 5 output the result of the conversion through the LPFs 6 and 7 as I signals i and Q signals q of analog signals for digital modulation.

On the other hand, at the time of the adjustment operation, first, the control signal x is supplied to the gain / offset control circuit 10. Then, the control circuit 10 generates control signals a to c, enters the adjustment mode, and the digital signal processing unit 1 generates a predetermined signal. At the same time, the gain / offset adjustment circuits 2 and 3 are initialized, and I and Q signals in an unadjusted state are output.

The I signal and the Q signal based on these analog signals are given to a switch 8, and an A / D converter 9 alternately A / D converts the analog signal selected by the switch 8, and controls the result by gain / offset control. To the circuit 10. The gain / offset control circuit 10 calculates the relative difference between the signal i and the signal q by arithmetic processing, and generates data d and data e for canceling the difference. Then, by giving these as adjustment data of the gain / offset control circuits 2 and 3, the adjustment is completed.

Next, the operation of the circuit of this embodiment having the above configuration will be described. FIG. 2 is a time chart showing the operation of each part of the digital modulation circuit of FIG.

FIG. 1 shows a gain / offset control circuit 1.
Control signal x to 0 and gain / offset control circuit 10
, B and c, I signal i and Q signal q, and data D output from A / D converter 9.
OUT and data d to the gain / offset adjustment circuit 2
When the data e to gain offset adjustment circuit 3 is shown <br/>.

In FIG. 1, first, when an adjustment command X is input to the gain / offset control circuit 10 by a control signal x, a control signal a indicating that the adjustment mode has been entered is input to the digital signal processing unit 1. In response to this command, the digital signal processing unit 1 alternately outputs a predetermined signal, for example, data DH and data DL having a difference equal to the upper and lower sides from the data at the time of no output to both systems. The data DH is the maximum value of the modulated waveform data during the normal operation, and the data DL is the minimum value of the modulated waveform data during the normal operation.

By outputting the data DH and the data DL, the I signal i and the Q signal q by analog signals become DC voltages VIH, VQH, VIL and VQL corresponding to the two kinds of data DH and DL. At this time, D / A
VIH ≠ VQH VIL ≠ VQL due to the relative deviation of the characteristics of converters 4 and 5 and LPFs 6 and 7. Therefore, this difference is corrected by the gain / offset adjustment circuits 2 and 3.

I signal i and Q signal q by analog signal
By controlling the switch 8 with the control signal b, A
/ D converter 9 alternately inputs. The A / D converter 9 performs A / D conversion of VIH, VQH, VIL, and VQL in response to the control signal c, thereby converting the converted data D
Get IH, DQH, DIL and DQL. In this case, the A / D converter 9 performs conversion in the order of data DIH, DQH, DIL, and DQL, and sequentially sends out the data as DOUT.

The gain / offset control circuit 10 performs arithmetic processing on these four data. As a result of the arithmetic processing, gain / offset adjustment data d (d1, d2) and e (e1, e) which are outputs of the gain / offset control circuit 10
The content of 2) is not an initial value, but becomes adjustment data after calculation. This gain / offset adjustment data d (d
By giving (1, d2) and e (e1, e2) to the gain / offset adjustment circuits 2 and 3, the adjustment is completed. At this time, the control signal a changes, and the mode shifts from the adjustment mode to the normal mode.

Here, for example, A / D conversion data expected in the case of having ideal characteristics is set in advance as DHR and DLR (common to signal i and signal q), and the difference between them is determined. Consider an adjustment value. In short, these data DHR and DLR become target values (reference values) for adjustment.

First, the offset adjustment data is obtained by taking the average value of two data of each of the signal i and the signal q, and taking the difference between this and the average value of the two data of the ideal value. The gain adjustment data is obtained by taking the difference between the two data of the signals i and q, and taking the ratio between the difference and the ideal two data.

The relationship between these data will be described with reference to FIG.

FIG. 3 shows target values DHR and DHR.
The relationship between LR and the data DOUT obtained by A / D conversion of the I signal i by the A / D converter 9 is shown. In the following description, for convenience, the value of the data DHR is expressed as “DHR”, and the value of the data DLR is expressed as “DLR”. Other data is similarly expressed.

In the figure, the maximum target value is the data DHR
And the minimum value is the data DLR. The maximum value of data DOUT after A / D conversion is data DIH, and the minimum value is data DIL.

Therefore, the ratio of the difference between the maximum value and the minimum value is the gain adjustment value. If this is d1, d1 = (DHR-DLR) / (DIH-DIL) (1) Similarly, the gain adjustment value for the Q signal q is e
Assuming that 1, e1 = (DHR-DLR) / (DQH-DQL) (2) That is, the ratio of the difference between the maximum value and the minimum value of the target amplitude value to the difference between the maximum peak value and the minimum peak value of the two systems of data corresponding to the I signal and the Q signal is used as the gain adjustment data. is there.

Incidentally, the average value of the data DHR and the data DLR, which are the target values, is (DHR + DLR) / 2 (3). The average of the maximum value and the minimum value of the data DOUT after the A / D conversion is (DIH + DIL) / 2 (4). Therefore, the difference between the above equations (3) and (4) is
An offset adjustment value for the I signal i. This is d
Assuming that 2, d2 = {(DHR + DLR) / 2} − {(DIH + DIL) / 2} (5) Similarly, assuming that the offset adjustment value for the Q signal q is e2, e2 = {(DHR + DLR) / 2} − {(DQH + DQL) / 2} (6) That is, the difference between the average value of the maximum peak value and the minimum peak value of the data of the two systems corresponding to the I signal and the Q signal and the average value of the maximum value and the minimum value of the target amplitude value is represented by the offset adjustment data. That is.

The calculations for the above equations (1), (2), (5) and (6) are performed in the gain / offset control circuit 10 as described later. When the above adjustment is completed, the mode returns to the normal mode, but the gain / offset adjustment value is held in a register described later until the adjustment mode is entered again.

FIG. 4 is a block diagram showing a part of the configuration of a second embodiment of the digital modulation circuit according to the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals.

In this embodiment, the peak voltage between the switch 8 and the A / D converter 9 in the first embodiment described above.
This is a configuration in which the hold circuit 11 is inserted. This peak
The hold circuit 11 can hold the voltage value at the maximum point and the voltage value at the minimum point of the waveform, respectively.

The operation of the digital modulation circuit according to the second embodiment will be described with reference to FIG. In the figure,
I signal i, Q signal q, control signal b of switch 8,
The control signal c of the A / D converter 9 and the data DOUT are shown. Other signals are the same as in FIG.

In the figure, in the digital modulation circuit of this embodiment, when the adjustment mode is entered, the I signal i and the Q signal q are ideally π / 2 at a constant amplitude and a constant frequency.
A sine wave out of phase is output. The voltage value of the maximum point and the voltage value of the minimum point of these sine waves are alternately held at the peak 11 and A / D converted. As in the case of the first embodiment, the four converted data DIH, DQH, Get DIL and DQL. That is, each peak value PH1 of the I signal i and the Q signal q
~ PH4 will be held.

Then, these four data are processed in the same manner as described above, and the gain / offset adjustment data d (d
By giving (1, d2) and e (e1, e2) to the gain / offset adjustment circuits 2 and 3, the adjustment is completed.

In the above-described first embodiment, a predetermined signal is output from the digital signal processing unit 1 during the adjustment operation. However, in this embodiment, since each peak value is held, such a signal is output. do not have to.

Next, the internal configuration of the gain / offset control circuit 10 will be described.

FIG. 6 is a block diagram showing an example of the internal configuration of the gain / offset control circuit 10 in FIG. 1, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In the figure,
The gain / offset control circuit 10 includes a register 22 for holding data DOUT after A / D conversion by the A / D converter 9 and data DIH, DQH, DIL, and DQL held and output by the register 22. And an arithmetic circuit 23 for performing the operations of the equations (1), (2), (5) and (6). The output of the arithmetic circuit 23 is I signal gain adjustment data d1, I signal offset adjustment data d2, Q signal gain adjustment data e1, and Q signal offset adjustment data e2. The data d1 and d2 are input to the gain / offset adjustment circuit 2, and the data e1
And e2 are input to the gain / offset adjustment circuit 3.

The gain / offset control circuit 10
Responds to the input of the adjustment control signal x in response to the control signal a to the digital signal processing unit 1, the control signal b to the switch 8,
It also includes a timing control circuit 21 for transmitting a control signal c to the A / D converter 9, an input data latch signal f to the register 22, and an operation control signal g to the operation circuit 23, respectively.

In this configuration, when the adjustment control signal is input to the timing control circuit 21, the prosperity signals a, b and c are output at the timing as shown in FIG. At the same time, a latch signal f defining the latch timing of the data after the A / D conversion is output, and the A / D conversion data of the high level voltage and the low level voltage of each of the I signal and the Q signal is taken into the register 22. .

Data DI fetched into register 22
H, DQH, DIL and DQL are input to the arithmetic circuit 23,
The calculations of the above-described equations (1), (2), (5) and (6) are performed at the timing given by the calculation control signal g. Among the calculation results, data d1 and d2 are input to the gain / offset adjustment circuit 2 and data e1 and e
2 is input to the gain / offset adjustment circuit 3.

In the second embodiment, a similar gain / offset control circuit is provided, and a similar operation is performed.

Further, the gain / offset adjusting circuit 2
The internal configuration of (3) will be described.

FIG. 7 is a block diagram showing an example of the internal configuration of the gain / offset adjustment circuit 2 (3) in FIG.
Are denoted by the same reference numerals. In the figure, a gain / offset adjustment circuit 2 (3) includes a multiplication circuit 31 for performing gain adjustment, a register 33 for holding a gain adjustment value given to the multiplication circuit, and an addition circuit 32 for performing offset adjustment. , And a register 34 for holding a gain adjustment value to be given to the addition circuit.

In such a configuration, the data d1 (e1) from the gain / offset control circuit 10 is held in the register 33 as a gain adjustment value. The input signal Din from the digital signal processing unit 1 is converted into data d1 (e1) held in the register 33 in the multiplication circuit 31.
Is multiplied by As a result, gain adjustment is performed.

The data d2 (e2) from the gain / offset control circuit 10 is held in the register 34 as an offset adjustment value. The output of the multiplication circuit 31 is multiplied by the data d2 (e2) held in the register 34 in the addition circuit 32. Thereby, offset adjustment is performed.

The data Dout after the gain adjustment and the offset adjustment are input to the D / A converter 4 (5) and output through the LPF 6 (7).

In the second embodiment, a similar gain / offset control circuit is provided, and a similar operation is performed.

As described above, according to the present digital modulation circuit, it is not necessary to measure the spectrum characteristic, and the gain / offset can be adjusted by one-time control, and the man-hour for adjusting the gain / offset can be reduced. You can.

The present invention can also take the following aspects in connection with the description of the claims.

(4) The data generation means includes A / D conversion means for alternately converting the I signal and the Q signal into digital data, and the calculation means converts the A / D conversion result and the target amplitude value. 4. The digital modulation circuit according to claim 2, wherein the gain adjustment data and the offset adjustment data are calculated based on the data.

(5) The data generating means starts the calculation in response to an external signal.
The digital modulation circuit according to the above.

[0057]

As described above, according to the present invention, a circuit provided in common for two systems of data is provided for adjustment according to the difference between each amplitude value of the I signal and the Q signal and a target amplitude value. Data is generated, and 2 is generated according to the generated adjustment data.
By adjusting the values of the data of the respective systems, it is not necessary to measure the spectrum characteristic, and the gain / offset can be adjusted with only one control, so that the number of adjustment steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital modulation circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the digital modulation circuit of FIG. 1;

FIG. 3 is a waveform chart showing a method of adjusting a gain / offset.

FIG. 4 is a block diagram showing a part of the configuration of a second embodiment of the digital modulation circuit according to the present invention.

FIG. 5 is a time chart illustrating an operation of the digital modulation circuit of FIG. 4;

FIG. 6 is a block diagram illustrating an example of an internal configuration of a gain / offset control circuit.

FIG. 7 is a block diagram illustrating an example of an internal configuration of a gain / offset adjustment circuit.

FIG. 8 is a block diagram showing a configuration of a conventional digital modulation circuit.

[Description of Signs] 1 Digital signal processing unit 2, 3 Gain / offset adjustment circuit 4, 5 D / A converter 6, 7 Low pass filter 8 Switch 9 A / D converter 10 Gain / offset control circuit

Claims (2)

(57) [Claims] 1. Two systems of data corresponding to an I signal and a Q signal.
Data conversion means for converting data into analog signals.
To output I and Q signals for quadrature modulation after
A digital modulation circuit, common to the two systems of data
And the respective amplitude values of the I signal and the Q signal
Adjustment according to the difference from the DC voltage value corresponding to the target amplitude value
Data generating means for generating data for
The values of the two systems are adjusted in accordance with the adjustment data.
Adjustment means for adjustingSee  The data generating means includes a maximum of two systems of data corresponding to the I signal and the Q signal.
The target amplitude value for the difference between the peak value and the minimum peak value
Data for gain adjustment, which is the ratio of the difference between the maximum and minimum values of
And two systems of data corresponding to the I signal and the Q signal.
Average value of maximum peak value and minimum peak value and the target amplitude
Offset that is the difference between the average of the maximum and minimum values
Calculating means for generating adjustment data, wherein the adjusting means operates in accordance with the generated adjustment data.
And adjusting the values of the two systems of data respectively.
Digital modulation circuit. (2)Two systems of data corresponding to the I and Q signals
Data conversion means for converting data into analog signals.
To output I and Q signals for quadrature modulation after
A digital modulation circuit, common to the two systems of data
And the respective amplitude values of the I signal and the Q signal
Adjustment according to the difference from the DC voltage value corresponding to the target amplitude value
Data generating means for generating data for
The values of the two systems are adjusted in accordance with the adjustment data.
Adjusting means for adjusting The data generating means includes: Maximum peak values of the I signal and the Q signal for the quadrature modulation;
Peak hold means for respectively outputting the minimum peak value, The difference between the maximum peak value and the minimum peak value
Is the ratio of the difference between the maximum value and the minimum value of the target amplitude value.
The gain adjustment data and the I and Q signals
Of the maximum and minimum peak values of the two sets of data
Of the average value and the average value of the maximum value and the minimum value of the target amplitude value.
Arithmetic means for generating offset adjustment data as a difference
And The adjusting means responds to these generated adjustment data.
And adjusting the values of the two systems of data respectively.
Do Digital modulation circuit.