KR0135829B1 - Digital nonlinear emphasis circuit - Google Patents

Abstract

Digital non-linear emphasis circuit improves a signal-to-noise ratio, increases a system stability, and does not require a gain value regulation according to the system. The circuit includes: a delay part(110) for delaying a digital signal by a constant time; a second non-linear counter(130) for generating a value made by multiplying an input signal by a non-linearly variable coefficient according to a delay signal size from the delay part(110); a first multiplier(140) for generating a value made by multiplying a constant coefficient(b2) by a delayed signal; a first coupler(100) for generating a value made by adding an output signal of the second non-linear counter(130) to an input digital signal from the digital signal input terminal(X(n)); a second coupler(150) for generating a value made by adding an output signal of the first coupler(100) to an output signal of the first multiplier(140); and a first non-linear counter(120) for transmitting a result signal(made by multiplying an input signal by a non-linear coefficient variable according to the output signal magnitude of the second coupler(150)) to a digital signal output terminal(Y(n)).

Description

Digital Nonlinear Emphasis Circuit

1 is a circuit diagram showing an embodiment of an analog nonlinear emphasis circuit according to the prior art;

2 is an equivalent circuit diagram of FIG.

3 is a characteristic curve diagram showing frequency characteristics of a nonlinear emphasis circuit,

4 is a block diagram showing a general IIR digital configuration,

5 is a block diagram showing a first embodiment of the digital nonlinear emphasis circuit according to the present invention;

FIG. 6 is a characteristic curve diagram showing coefficient changes for the first nonlinear counter of FIG.

7 is a characteristic curve diagram showing the frequency characteristic change by the second nonlinear counter of FIG.

8 is a characteristic curve diagram showing a change in frequency characteristics by the first nonlinear counter of FIG. 5;

9 is a characteristic curve diagram showing the frequency characteristic change by the second nonlinear counter of FIG.

FIG. 10 is a characteristic curve diagram showing a frequency characteristic change by the first and second nonlinear counters of FIG.

11 is a characteristic curve showing a change in frequency characteristics of a high pass filter,

12 is a block diagram showing a second embodiment of a digital nonlinear emphasis circuit according to the present invention;

FIG. 13 is a block diagram showing a third embodiment of a digital nonlinear emphasis circuit according to the present invention;

14 is a block diagram showing a fourth embodiment of a digital nonlinear emphasis circuit according to the present invention;

FIG. 15 is a block diagram showing a fifth embodiment of a digital nonlinear emphasis circuit according to the present invention;

FIG. 16 is a characteristic curve diagram showing coefficient changes of the first nonlinear counter of FIG.

FIG. 17 is a characteristic curve diagram showing coefficient changes of the second nonlinear counter of FIG.

* Description of the symbols for the main parts of the drawings *

100: first combiner, 110: delay unit,

120: first nonlinear counter, 121: fifth nonlinear counter,

130: second nonlinear counter, 131: sixth nonlinear counter,

140: first multiplier, 141: third nonlinear counter,

150: second combiner, 160: second multiplier,

161: fourth nonlinear counter, 170: delay correction unit,

180: phase corrector, 190: third combiner,

200: first switching unit, 201: second switching unit,

300: switching pulse input terminal, X (n): digital signal input terminal, Y (n): digital signal output

Power Terminal,

R1, R2: Digital signal input terminal, C1, C2: Capacitor,

D1, D2: Diode, VR: Variable resistor,

A: high pass filter

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a digital nonlinear emphasizing circuit, and more particularly, to a digital nonlinear emphasizing circuit in which the frequency characteristic of a system is nonlinearly converted according to the magnitude of an input signal input into a high pass filter.

In general, an emphasis circuit configured in a high pass filter is an input that emphasizes high frequency components at the input and improves the signal-to-noise ratio (hereinafter referred to as SN ratio) in a frequency modulation (hereinafter referred to as 'FM') transmission system. The circuit gives a frequency characteristic to compensate for it. That is, a circuit for amplifying and outputting a high frequency component when a small high frequency is input, and outputting it as it is when a large value high frequency is input, thereby maintaining a high frequency of a predetermined value or more.

FIG. 1 is a circuit diagram showing an embodiment of a conventional analog nonlinear emphasis circuit, FIG. 2 is an equivalent circuit diagram of FIG. 1, and FIG. 3 is a special curve diagram showing the frequency characteristics of a nonlinear emphasis circuit. In FIG. 2, components identical to those of FIG. 1 will be omitted, and like elements will be denoted by like reference numerals.

Referring to FIG. 1, the digital signal input terminal X (n) is connected to the resistor R1, the resistor R1 is connected to the first coupler 100, and the first coupler 100 is digital. It is connected to the signal output terminal Y (n). Further, a branch is branched between the digital signal input terminal X (n) and the resistor R1 and one is connected between the first coupler 100.

In addition, a branch between the resistor R1 and the first coupler 100 is grounded through the resistor R2, and is branched between the resistor R2 and the ground point to the resistor R2 through the diode D1 and the capacitor C2. It is connected between the R1) and the first coupler 100, is branched between the diode (D1) and the capacitor (C2) is connected to the input terminal of the diode (D1) through the diode (D1).

When the operation is described with reference to the configuration as described above, the resistance values of the diodes D1 and D2 change nonlinearly according to the magnitude of the input signal input from the digital signal input terminal X (n). Therefore, the frequency characteristic of the high pass filter A is changed and output through the digital signal output terminal Y (n) (see FIG. 3).

Referring to FIG. 2, the variable resistor VR is configured between the node between the resistor R2 and the ground point and the capacitor C2 without using two diodes D1 and D2 in the first component of FIG. The remaining part is the same as in FIG.

However, in the conventional analog nonlinear emphasis circuit, the SN ratio decreases, the stability of the system decreases due to the change of characteristics of the active elements due to the change of the characteristics of the active elements according to the change of external factors such as the temperature of the system, and the gain value according to the system is decreased. There was a problem that needs to be adjusted.

In addition, when the non-linear pre-emphasis circuit is configured, a non-linear de-emphasis circuit must be configured to compensate for this, but the size of the product is increased because a circuit for controlling the operation must be additionally configured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonlinear emphasis circuit for digitally processing analog nonlinear pre-emphasis and de-emphasis signals.

Another object of the present invention for solving the above problems is to test the non-linear pre-emphasis and non-linear de-emphasis having the opposite characteristics of the same structure by using only switching, the digital non-linear M to simplify the size of the product It is to provide a percussion circuit.

A feature of the present invention for achieving the above object is a delay unit for delaying a digital signal input from a digital signal input terminal for a predetermined time, non-linearly according to the magnitude of the signal delayed through the delay unit connected to the delay unit A second nonlinear counter for outputting a value obtained by multiplying a changing coefficient by an input signal, a first multiplier for outputting a value obtained by multiplying a delayed signal by a predetermined coefficient through the delay unit, and a second multiplier that is connected to the second nonlinear counter A first combiner for outputting the sum of the signal output from the second nonlinear counter and the digital signal input from the digital signal input terminal; and simultaneously connected to the first combiner and the first multiplier and output from the first combiner A second combiner for outputting a sum of a signal and a signal output from the first multiplier, the second combiner The first nonlinear emulation circuit is connected to a coupler and applies a result of multiplying an input signal by a nonlinear coefficient that changes according to the magnitude of the signal output from the second combiner to a digital signal output terminal at a later stage.

Another feature of the present invention for achieving the above object is a delay unit for delaying the digital signal input from the digital signal input terminal for a predetermined time, non-linear according to the magnitude of the signal delayed through the delay unit connected to the delay unit A second nonlinear counter that outputs a value multiplied by an input signal and a second nonlinear counter connected to the second nonlinear counter to sum the sum of the signal output from the second nonlinear counter and the digital signal input from the digital signal input terminal. A first coupler for outputting, a second coupler coupled to the first coupler and the delay unit and outputting a sum of a signal output from the first combiner and a signal output from the delay unit, and connected to the second combiner Multiplying the input signal by a nonlinear coefficient that changes according to the magnitude of the signal output from the second combiner A first nonlinear counter for outputting a signal to a rear stage, a phase correction unit connected to the first nonlinear counter to correct a phase of a high pass filter, and a non-matching unit connected to the digital signal input terminal to a delay in the high pass filter. A delay correction unit for delaying a predetermined time to preserve the delay time, and a phase correction unit and the delay correction unit are simultaneously connected to combine the output signal of the phase correction unit and the output signal of the delay correction unit to non-linear pre-emphasis. There is provided a digital nonlinear emphasis circuit provided with a third coupler for applying a signal to a digital signal output terminal at a later stage.

Another feature of the present invention for achieving the above object is a delay unit connected to the digital signal input terminal for delaying the digital signal applied from the digital signal input terminal for a predetermined time, the delay unit is connected to the delay unit A second nonlinear counter that performs a nonlinear pre-emphasis function by outputting a value multiplied by an input signal by a coefficient that varies nonlinearly according to the size of the delayed signal, connected to the delay unit to a magnitude of the delayed signal through the delay unit. And a sixth nonlinear counter for performing a nonlinear de-emphasis function by outputting a value multiplied by an input signal according to a nonlinear variable, the second nonlinear counter, the sixth nonlinear counter, and a sixth nonlinear counter and a switching pulse input terminal simultaneously. An output signal of the second nonlinear counter and an output signal of the sixth nonlinear counter Is applied simultaneously and when the system performs nonlinear pre-emphasis under control of the pulse signal applied from the switching pulse input terminal, when the output of the second nonlinear counter is applied to the rear end and the system performs nonlinear de-emphasis. The first multiplier for switching the output by applying the output of the sixth non-linear counter to the rear stage, the first multiplier connected to the delay unit for outputting the signal multiplied by the delayed signal through the delay unit, the first switching A first coupler coupled to a first coupler for coupling a signal selected by the first switching unit and a digital signal applied from a digital signal input terminal, and simultaneously connected to the first combiner and the first multiplier and outputting from the first combiner A second coupler connected to the second coupler according to the magnitude of the signal output from the second coupler A first nonlinear counter for outputting a result of multiplying a nonlinear coefficient by a change in an input signal, and outputting a result of multiplying an input signal by a nonlinear coefficient which is connected to the second coupler and varies according to a magnitude of a signal output from the second combiner The first nonlinear counter, the first nonlinear counter and the fifth nonlinear counter and the switching pulse input terminal at the same time when the system performs the nonlinear pre-emphasis according to the control signal input from the pulse signal input terminal; When the output of the nonlinear counter is applied to the rear stage and the system performs the nonlinear de-emphasis, the output of the fifth nonlinear counter is applied to the digital signal output terminal of the rear stage to provide a second switching unit which performs a switching action. Non-linear pre-emphasis and non-linear de-emphasis with switching Digital non-linear emphasis circuitry with a high pass filter adapted for control.

Hereinafter, a preferred embodiment of the digital nonlinear emphasis circuit according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram showing the configuration of a general IIR filter.

4, the digital signal input terminal X (n) is connected to the combiner, the combiner is connected to the delay unit, the delay unit is connected in parallel to the two multipliers, and each multiplier It is connected to the coupler.

Each coupler is also connected to the digital signal output terminal Y (n) via a multiplier. As a result, the above-described configuration is connected to N to form one IIR filter.

The system function according to the above configuration is as follows.

In this case, since the resistance value of the diode of FIG. 1 varies according to the magnitude of the input signal, a digital nonlinear emphasis function can be obtained by changing the coefficient of the digital IIR filter according to the magnitude of the input signal.

FIG. 5 is a block diagram showing a first embodiment of a digital nonlinear emphasis circuit according to the present invention, and FIG. 6 is a characteristic curve showing a coefficient change with respect to the counter for the first nonlinear counter of FIG. 5, and FIG. Characteristic curve diagram showing coefficient change for the first nonlinear counter of 5 degrees. 8 is a characteristic curve showing the frequency characteristic change by the first nonlinear counter of FIG. 5, FIG. 9 is a characteristic curve showing the frequency characteristic change by the second nonlinear circuit of FIG. 5, and FIG. It is a characteristic curve figure which shows the frequency characteristic change by the 1st, 2nd nonlinear counter of 5 degrees.

Referring to FIG. 5, the digital signal input terminal X (N) is branched between the second coupler 15 through the first coupler 100 and connected to the delay unit 110, and the first coupler 100. ) Is branched between the second coupler 150 and connected to the delay unit 110, and branched from the delay unit 110 is connected to the first coupler 100 through the second nonlinear counter 130. And the other is connected to the second coupler 150 via the first multiplier 140.

In addition, the second coupler 15 is connected to the digital signal output terminal Y (n) through the first nonlinear counter 120.

The system function is obtained by referring to the configuration as described above.

The digital signal input through the digital signal input terminal X (n) is input to the first combiner 100, and the first combiner 100 supplies an input signal to the delay unit 110 and the second combiner 150. Output The delay unit 110 delays the input signal for a predetermined time, and the delayed signal is simultaneously input to the second nonlinear counter 130 and the first multiplier 140. The second nonlinear counter 130 outputs a result of multiplying the input signal by a coefficient that varies nonlinearly according to the magnitude of the input signal (see FIGS. 7 and 9). The output of the second nonlinear counter 130 is fed back to the other input terminal of the first combiner 100 and combined with the input signal applied from the digital signal input terminal X (n).

The first multiplier 14 outputs a result of multiplying the output signal of the delay unit 110 by a predetermined coefficient b2. The output of the first multiplier 140 is input through another input terminal of the second combiner 15 to be coupled with the output of the first combiner 100. The signal coupled through the second combiner 150 is input to the first nonlinear counter 120. The first nonlinear counter 120 outputs a result of multiplying the input signal by a nonlinear coefficient that changes according to the magnitude of the input signal (see FIGS. 6 and 8).

The two nonlinear counters exhibit the same characteristic change in frequency as the tenth degree.

Here, the gain of the DC component is not 0 but 1 is obtained. Therefore, when the coefficients of the first and second nonlinear counters have nonlinear de-emphasis characteristics, they become nonlinear de-emphasis circuits.

1 is a block diagram showing a second embodiment of the digital nonlinear emphasis circuit according to the present invention. In FIG. 11, the same components as those in FIG. 5 will be denoted by the same reference numerals.

Referring to FIG. 11, the second multiplier 160 is additionally configured between the first coupler 100 and the second coupler 150 in the configuration of FIG. 5, and the remaining components are the same as the fifth diagram.

Referring to the configuration of Figure 11, the system function is as follows.

The difference between Eq. (3) and Eq. (2) is that the zero coefficient of the molecular term is any number other than one.

12 is a block diagram showing a third embodiment of the digital nonlinear emphasis circuit according to the present invention. In FIG. 12, the same components as those in FIG. 5 use the same reference numerals.

Referring to FIG. 12, a fourth nonlinear counter 161 is further configured between the first coupler 100 and the second coupler 150 among the components of FIG. 5, and the first multiplier 140 is removed and the first Three nonlinear counters 141 are configured, and the remaining parts are the same as in the fifth degree.

Referring to the above configuration, the system function is as follows.

FIG. 12 is a block diagram generalizing the system blocks of FIGS. 5 and 6 described above. The difference between FIGS. 5 and 6 is that both the coefficients of the numerator term and the denominator are changed according to the magnitude of the input signal.

This means that the coefficient of the molecular term also changes according to the magnitude of the input signal when the frequency characteristic change of the system that defines the recording format cannot be approximated only by the coefficient change of the denominator. If the frequency characteristic change of the system defined by the recording format cannot be approximated in the form of FIG. 12, the system can be approximated by increasing the order of the system.

FIG. 13 is a block diagram showing a fourth embodiment of the digital emulation circuit according to the present invention, and FIG. 14 is a characteristic curve diagram showing the frequency characteristic change of the high pass filter A. FIG. In Fig. 13, the same components as those in Fig. 5 have the same reference numerals.

Referring to FIG. 13, a branch between the digital signal input terminal X (n) and the first coupler 100 of the configuration of FIG. 5 is connected to the third coupler 190 through the delay correction unit 170. The output of the first nonlinear counter 120 is connected to the third combiner 190 through the phase correction unit 180, and the output of the third combiner 190 is connected to the digital signal output terminal Y (n). It is connected.

In addition, the first multiplier 140 is removed, and the remaining part is the same as the fifth degree.

Referring to the configuration as described above, the input signal is input to the high pass filter (A) having a frequency characteristic that varies nonlinearly according to the magnitude of the input signal. The operations of the first and second nonlinear counters 120 and 130, the delayers 110, and the first and second couplers 100 and 150 constituting the high pass filter A are the same as those of FIG. 5. Here, the difference between FIG. 13 and FIG. 5 is that the gain of the DC voltage component is determined to have a frequency characteristic of zero.

The output of the high pass filter A is applied to the phase correction unit 180 to correct the phase. The phase correction unit 180 corrects the delayed value through the plurality of delay units in the high pass filter A because the delayed value is not constant.

In addition, the delay correction unit 170 delays the input signal by a delay time generated by the high pass filter A and the phase correction unit 180, and then applies the delayed signal to the third combiner 190. The output of the phase corrector 180 is applied to the other input terminal of the third combiner 190. As a result, the output of the third coupler 190 is a nonlinear pre-emphasized signal (see FIG. 14).

FIG. 15 is a block diagram showing a fifth embodiment of a digital nonlinear emphasis circuit according to the present invention, FIG. 16 is a characteristic curve showing a coefficient change of the first nonlinear coefficient of FIG. 15, and FIG. 2 is a characteristic curve showing nonlinear coefficient change, and the same components as those in FIG. 15 in FIG. 15 use the same symbols.

Referring to FIG. 15, the digital signal input terminal X (n) is connected to the second coupler 150 through the first coupler 100, and between the first coupler 100 and the second coupler 150. Branched at and connected to the delay unit 110. In addition, the output of the delay unit 110 is branched so that one is connected to the second combiner 150 through the first multiplier 140, and the other branch is again branched through the second nonlinear counter 130. It is connected to the first switching unit 200, the other is connected to the first switching unit 200 through the sixth non-linear counter 131.

Meanwhile, the switching pulse input terminal 300 is connected to the first switching unit 200, and the first switching unit 200 is connected to the first coupler 100. In addition, the output of the second coupler 150 is branched so that one is connected to the second switching unit 201 through the first nonlinear counter 120, and the other is connected to the second switch 201 through the fifth nonlinear counter 121. It is connected to the switching unit 201, branched between the switching pulse input terminal 300 and the first switching unit 200 is connected to the second switching unit 201. In addition, the output of the second switching unit 201 is connected to the digital signal output terminal X (n).

Referring to the above configuration, the digital signal input through the digital signal input terminal X (n) is input to the first combiner 100. The output of the first coupler 100 is applied to the delay unit 110 and the second coupler 150.

The delay unit 110 receives a signal and delays the signal for a predetermined time, and then inputs it to the second nonlinear counter 130, the sixth nonlinear counter 131, and the first multiplier 140.

In addition, the second nonlinear counter 130 and the six six nonlinear counters 131 output the result of multiplying the input signal by a coefficient that varies nonlinearly according to the magnitude of the input signal to the first switching unit 200. The switching unit 200 receives the control of the switching pulse applied from the switching pulse input terminal 300, and when performing the nonlinear pre-emphasis, inputs the output of the second nonlinear counter 130 to the first combiner 100. When the nonlinear de-emphasis is performed, the output of the sixth nonlinear counter 131 is input to the first combiner 100 (see FIG. 17).

Meanwhile, the first multiplier 140 outputs a result of multiplying an input signal by a predetermined coefficient b2. The output of the first multiplier 140 is input to the second combiner 150 and input to the first nonlinear counter 120 and the fifth nonlinear counter 121. It is input to the first nonlinear counter 120 and the fifth nonlinear counter 121. The first nonlinear counter 120 and the fifth nonlinear counter 121 output a result of multiplying the input signal by a coefficient that varies nonlinearly according to the magnitude of the input signal to the second switching unit 201. Reference).

When the second switching unit 201 performs the nonlinear pre-emphasis under the control of the switching pulse applied from the switching pulse input terminal 300, the second switching unit 201 outputs the output of the first nonlinear counter 120 to the digital signal output terminal Y ( n)), and when performing nonlinear de-emphasis, the output of the fifth nonlinear counter 121 is applied to the digital signal output terminal Y (n).

As described above, according to the digital nonlinear emphasis circuit according to the present invention, the signal-to-noise ratio is improved by converting the analog signal processing method into the digital signal processing method, and the stability of the system is not changed even if external factors change. Is improved and there is no need to adjust the gain value depending on the system.

In addition, there is an advantage that the size of the product can be reduced by selecting and operating only a switch without additionally configuring a control unit for the operation of the nonlinear de-emphasis configured to compensate for the non-linear pre-emphasis.

Claims (5)

A delay unit 110 for delaying the digital signal input from the digital signal input terminal X (n) for a predetermined time, and is connected to the delay unit 110 to be non-linear according to the magnitude of the delayed signal through the delay unit 110; A second nonlinear counter 130 that outputs a value that is multiplied by an input signal multiplied by a signal that changes, and a value that is multiplied by a predetermined coefficient b2 to a signal delayed through the delay unit 110 by being connected to the delay unit 110. Is connected to the first multiplier 140 and the second nonlinear counter 130 and outputs the signal output from the second nonlinear counter 130 and the digital signal input from the digital signal input terminal X (n). Is coupled to the first combiner 100, the first combiner 100, and the first multiplier 140 simultaneously to output the sum value, and the signal output from the first combiner 100 and the first multiplier 140. A second combiner 150 for outputting the sum of the signals output from The result of multiplying an input signal by a nonlinear coefficient that is connected to the second combiner 150 and varies according to the magnitude of the signal output from the second combiner 150 is applied to the digital signal output terminal Y (n) at a later stage. And a high pass filter (A) comprising a first nonlinear counter (120). 2. The high pass filter (A) of claim 1, further comprising a second multiplier (160) between the first coupler (100) and the second coupler (150) so as to obtain zero among the molecular terms in the system function. A digital nonlinear emphasis circuit, in which a change in frequency characteristic starts at 0 decibels by causing the coefficient to be other than one. 2. The high pass filter (A) of claim 1, wherein the high pass filter (A) comprises a third non-linear counter (141) after removing the first multiplier (140) and is formed between the first combiner (100) and the second combiner (150). A digital non-linear emphasis circuit comprising four non-linear counters (161) so that both frequency and gain values can be adjusted according to an input signal. A delay unit 110 for delaying the digital signal input from the digital signal input terminal X (n) for a predetermined time, and is connected to the delay unit 110 to be non-linear according to the magnitude of the delayed signal through the delay unit 110; A signal output from the second nonlinear counter 130 and the digital signal input connected to the second nonlinear counter 130 to output a value obtained by multiplying an input signal by an input signal; A first combiner 100 that outputs a value multiplied by a digital signal input from the terminal X (n), and is simultaneously connected to the first combiner 100 and the delay unit 110 to be connected to the first combiner 100. The second combiner 150 and the second combiner 150 for outputting the sum of the signal output from the signal output from the delay unit 110 and the second combiner 150 of the signal output from the second combiner 150 Multiply the input signal by the nonlinear coefficient that varies with magnitude The delayed value is not constant through a plurality of delay units configured in the high pass filter A connected to the first nonlinear counter 120 and the first nonlinear counter 120 that outputs a second stage. A delay correction unit 170 connected to the phase correction unit 180 to correct and the digital signal input terminal X (n) and delayed by a delay time generated by the high pass filter A and the phase correction unit 180. ) Is connected to the phase correction unit 180 and the delay correction unit 170 simultaneously to combine the output signal of the phase correction unit 180 and the output signal of the delay correction unit 170 to form a nonlinear pre-emphasis. And a third coupler (190) for applying the received signal to a digital signal output terminal (Y (n)) at a later stage. A delay unit 110 connected to the digital signal input terminal X (n) for delaying a digital signal applied from the digital signal input terminal X (n) for a predetermined time, and connected to the delay unit 110 The second nonlinear counter 130 and the delay unit 110 to perform a nonlinear pre-emphasis function by outputting a value multiplied by the input signal by a coefficient that varies nonlinearly according to the magnitude of the delayed signal through the delay unit 110. A sixth nonlinear counter 131 connected to the sixth nonlinear counter to output a value obtained by multiplying an input signal by a coefficient that varies nonlinearly according to the magnitude of the delayed signal through the delay unit 110, and performs a nonlinear de-emphasis function. A second nonlinear counter 130, a sixth nonlinear counter 131, and a switching pulse input terminal 300 are simultaneously connected to output signals of the second nonlinear counter 130 and an output signal of the sixth nonlinear counter 131. Dong When the system performs the nonlinear pre-emphasis under the control of the pulse signal applied from the switching pulse input terminal 300, the output of the second nonlinear counter 130 is applied to the rear end and the system is applied to the nonlinear DM. In the case of performing the perforation, the first switching unit 200 having a switching action for applying the output of the sixth non-linear counter 131 to the rear stage and the delay unit 110 are connected to the delay unit 110. The first multiplier 140 outputs a value obtained by multiplying the delayed signal by a predetermined coefficient b2 and the digital signal input terminal connected to the first switching unit 200 and selected by the first switching unit 200. A first coupler 100 for coupling the digital signal applied from X (n)), a signal simultaneously connected to the first combiner 100 and the first multiplier 140 and output from the first combiner 100 And exit from the first multiplier 140 As a result of multiplying an input signal by a nonlinear coefficient that is connected to the second combiner 150 and the second combiner 150 that outputs the sum of one signal, and varies according to the magnitude of the signal output from the second combiner 150. A first nonlinear counter 120 for outputting the second nonlinear coefficient connected to the second combiner 150 and outputting a result of multiplying an input signal by a nonlinear coefficient that varies according to the magnitude of the signal output from the second combiner 150; A five nonlinear counter 121, the first nonlinear counter 120, the fifth nonlinear counter 121, and a switching pulse input terminal 300 are simultaneously connected to output signals of the first nonlinear counter 120 and the first signal. 5 When the output signal of the nonlinear counter 121 is simultaneously applied and the system performs nonlinear pre-emphasis according to the control signal input from the pulse signal input terminal 300, the output of the first nonlinear counter 120 is rear-end. On In addition, when the system performs nonlinear de-emphasis, the second switching unit 201 that performs a switching action of applying the output of the fifth nonlinear counter 121 to the digital signal output terminal Y (n) at the rear stage is provided. And a high pass filter (A) configured to control the nonlinear pre-emphasis and the nonlinear de-emphasis having opposite characteristics to each other by a switching unit.