JPH0557767B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Tone control circuits are generally constructed from a combination of capacitors and resistors. Therefore, in such a tone control circuit, for example, as shown in FIG. 2A, the high frequency component S _H and the low frequency component
When an audio signal having S _L is supplied, for example, if tone control is performed to enhance the low frequency range, the low frequency component S _L
At the same time as the level of increases, the phase shift τ,
In other words, phase distortion occurs.

The present invention aims to provide a tone control circuit that takes into consideration the phase of each signal component.

An example of this will be explained below. In addition, in the following example, as shown in Figure 3, the low range is
Can be adjusted below 100Hz over a range of ±10dB,
The high frequency range is 25kHz and can be adjusted over a range of ±10dB.

In FIG. 1, an analog audio signal is supplied to an A/D converter 2 through an input terminal 1, sampled at a frequency of, for example, 50 kHz, and converted into a digital signal S _2. This signal S ₂ is supplied to a low-pass filter 11. be done.

This filter 11 includes 98 delay circuits D ₀ to D ₉₇
, 50 coefficient circuits a ₀ to a ₄₉ , and 49 adder circuits
A ₀ to A ₄₈ constitute a 98th order FIR type with symmetrical coefficients. That is, the delay circuits _D0 to _D97 are connected in cascade, the signal _S2 is supplied to the 0th delay circuit _D0 , and the nth (0<n<49) and (98-n)th delay circuits _D0 , D _98-o is supplied to the (49-n)th coefficient circuit a _49-o , and the signal S ₂ and the output of the delay circuit D ₉₈ are supplied to the coefficient circuit a ₄₉ , and the 48th delay The output of circuit D ₄₈ is fed to coefficient circuit a ₀ ,
The outputs of the coefficient circuits a ₀ -a ₄₉ are supplied to adder circuits A ₀ -A ₄₈ and a signal S ₁₁ is taken out.

In this case, the delay time of delay circuits D ₀ to D ₉₇ is
It is assumed to be the reciprocal of the sampling frequency in the A/D converter 2, that is, 20 μsec. Further, the coefficients of the coefficient circuits _a0 to _a49 are selected as shown in FIG. 8, for example. In addition, in this FIG. 8, the number next to the letter E indicates a multiplier of 10. For example, the coefficient a ₄₉ of the coefficient circuit a ₄₉ is a ₄₉ = 2.58303E-3 = 2.58303 × 10 ^-3 .

Therefore, the frequency characteristic of the filter 11 is a low-pass characteristic (the loss in the stop band is
47 dB or more), and the output signal S ₁₁ is the low frequency component of the input signal at terminal 1.

Then, this low frequency component signal _S11 is sent to the multiplier circuit 1.
At the same time, the control signal _S13 is supplied from the control circuit 13 to the multiplication circuit 12, and the signal _S11 is supplied to the multiplication circuit 12.
The level of the signal S ₁₁ is controlled by S ₁₃ as shown in FIG. 4, and its output signal S ₁₂ is supplied to the adder circuit 3.

Also, the signal S ₂ from the converter 2 is transmitted to the delay circuit 2
1 to the adder circuit 3. This delay circuit 21 connects the signal S ₂ supplied to the adder circuit 3 and the signal
This is to eliminate the difference in delay time with S ₁₂ ,
Therefore, the delay circuit 21 is composed of 49 delay circuits D ₀ to D ₄₈ similar to the delay circuit D _o in the filter 11.

Furthermore, a signal from the delay circuit D ₄₇ of the filter 21 is
S ₂ is extracted and this signal S ₂ is supplied to the high pass filter 31 . This filter 31 is also configured in a quadratic FIR type with symmetrical coefficients, and includes delay circuits D ₀ , D ₁ , coefficient circuits b ₀ , b ₁ , and an adder circuit B _{0 .}
and has. Note that the coefficients of the coefficient circuits b ₀ and b ₁ are selected as shown in FIG. 9, for example.

Therefore, the frequency characteristic of the filter 31 is a high-pass characteristic (the loss in the stop band is
54 dB or more), and its output signal S ₃₁ is the high frequency component of the input signal at terminal 1. Also, this signal S ₃₁
There is no difference in delay time between the signals S ₁₂ and S ₂ supplied to the adder circuit 3.

Then, this high frequency component signal _S31 is sent to the multiplier circuit 3.
At the same time, the control signal _S33 is supplied from the control circuit 33 to the multiplication circuit 32, and the signal _S31 is supplied to the multiplication circuit 32.
The level of the signal S ₃₁ is controlled by S ₃₃ as shown in FIG. 5, and its output signal S ₃₂ is supplied to the adder circuit 3.

Therefore, from the adder circuit 3, the signals S ₁₂ , S ₂ , S ₃₂
The sum signal S ₃ of S 3 is taken out, and this signal S ₃
has a frequency characteristic as shown in FIG. That is, the level of the low-frequency component _S12 changes as shown in FIG. 4 by the control signal _S13 , and this low-frequency component
Since S ₁₂ is added to the signal S ₂ having a flat characteristic, the low frequency component S ₁₂ included in the added signal S ₃ changes as shown in FIG. Furthermore, the level of the high frequency component S ₃₂ changes as shown in FIG. 5 by the control signal S ₃₃ .
Since this high frequency component _S32 is added to the signal _S2 having a flat characteristic, the high frequency component _S32 included in the added signal _S3 changes as shown in FIG. Therefore, the signal S ₃
has a frequency characteristic that changes as shown in FIG. 3 depending on the control signals S ₁₃ and S ₃₃ .

This signal S ₃ is then supplied to the D/A converter 4 and converted into an analog audio signal, which is taken out to the output terminal 5 .

Thus, according to the present invention, it is possible to perform tone control of an audio signal. In this case, in particular, according to the present invention, the low frequency component S ₁₂ and the high frequency component S ₃₂ are added to the signal S ₂ having a flat characteristic. In addition to obtaining the desired frequency characteristics, since the filters 11 and 31 that form both components S ₁₂ and S ₃₂ are constructed of FIR type filters with symmetrical coefficients, the filter 1
The phase characteristics of 1 and 31 become flat, and the signals S ₁₂ and S ₃₂
Therefore, there is no phase shift between the low-frequency component _S12 , the middle-frequency component, and the high-frequency component _S32 included in the output signal of the terminal 5, that is,
No phase distortion occurs.

In the example shown in FIG. 10, the phase (delay) of the low, middle, and high ranges can also be adjusted.

That is, the low frequency component _S11 from the filter 11,
The signal S ₂ with a flat characteristic from the delay circuit 21 and the high frequency component S ₃₁ from the filter 31 are supplied to the subtraction circuit 6, and both components S ₁₁ and S ₃₁ are subtracted from the signal S ₂ to obtain the mid frequency component. S ₆ is taken out. These components S ₁₁ , S ₆ , and S ₃₁ are connected to variable delay circuits 14, 24, and 34.
and the control circuits 15, 25, 35
The delay times of the delay circuits 14 to 34 are controlled by control signals from the respective delay circuits 14 to 34.

Then, the low frequency component S ₁₁ from the delay circuit 14 is supplied to the multiplication circuit 12, the mid frequency component S ₆ from the delay circuit 24 is supplied to the adding circuit 3, and the high frequency component S ₃₁ from the delay circuit 34 is supplied to the adding circuit 3. is supplied to the multiplication circuit 32.

Therefore, a tone-controlled audio signal is outputted to the terminal 5, and the delay of each band component is adjusted to a desired magnitude.

[Brief explanation of the drawing]

FIGS. 1 and 10 are system diagrams of an example of this invention,
FIGS. 2 to 9 are diagrams for explaining the same. 11 is a low pass filter, and 31 is a high pass filter.

[Claims]

1. A plurality of charging transistors connected in parallel and having a common connection point at one end connected to a first power source, and a plurality of discharge transistors connected in parallel between a common connection point at the other end of these charging transistors and a second power source. a transistor, and a first signal transmission means for supplying a signal from an internal circuit to the gates of the plurality of charging transistors, turning on the charging transistors almost simultaneously, and sequentially setting them in a non-conducting state at predetermined time intervals; and second signal transmission means for supplying a signal from an internal circuit to the gates of the plurality of discharge transistors, turning on the discharge transistors almost simultaneously, and sequentially setting them in a non-conduction state at predetermined time intervals. Features an output buffer circuit. 2. When the signal from the internal circuit sets the charging transistor to a conductive state, the first signal transmission means supplies the signal from the internal circuit to the gates of the plurality of charging transistors almost simultaneously.