JPH0955646A - Pulse width modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a signal with a spectrum of a high frequency by providing a counter, a fundamental wave generating means, and a pulse width modulation means generating a pulse width modulation signal with a product sum arithmetic operation between a data signal and a fundamental wave signal to the pulse width modulator. SOLUTION: Based on an operating clock CLK received by a binary count circuit 9, n-bit binary count signals c1 -cn whose period is a multiple of a period of the clock CLK are generated by the circuit 9 and given to a fundamental wave generating circuit 26. The fundamental wave generating circuit 26 generate n-sets of fundamental waves b1 -bn used for generating a pulse width modulation(PWM) wave from the signals c1 -cn and give the fundamental waves b1 -bn as a parallel signal to a PWM wave generating circuit 11. The circuit 11 generates a PWM wave (q) subject to pulse width modulation from the fundamental waves b1 -bn and a data signal SD received in n-bit parallel. As a result, the circuit 11 generates a signal (b) with a spectrum of a high frequency consisting of thin pulse widths to output the signal (q) with a thin pulse width.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD The invention belongs to the related art (FIGS. 8 to 13). Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (FIGS. 1 to 7) (1) Configuration of Frequency Error Correction Device (FIGS. 1 and 2) (2) Configuration of pulse width modulator (FIGS. 3 to 7)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulator, which is suitable for demodulating a received signal of a mobile phone by a CDMA (Code Division Multiple Access) system, for example.

[0003]

2. Description of the Related Art Conventionally, a CDMA mobile phone that generates a spread spectrum signal by a DS (Direct Sequence) system is called a PN (Pseudorandom Noise) sequence for a digital signal that has undergone primary modulation on the transmission side. Spreads modulation by multiplying special waveforms. On the other hand, on the receiving side, the spread spectrum modulated signal is demodulated to the original primary modulation signal by multiplying the spread modulated modulated signal by the same signal as the PN sequence used for spreading on the transmitting side. . At this time, on the receiving side, it is necessary to detect the frequency error of the demodulated signal using a frequency error correction device in order to match the generation timing of the PN sequence with the received signal.

As shown in FIG. 8, a frequency error correction device 1
Is controlled by the clock CLK output from the voltage controlled oscillator (VCXO) 2 which controls the oscillation frequency by the voltage.
The generation timing of the PN code generated by the N code generator 3 is determined. From this PN code generator 3, a PN code PN whose frequency error has been corrected is sent to the multiplication unit 4. The multiplication unit 4
The received signal S _R is demodulated by performing an exclusive OR operation on the received signal S _R using the PN code PN, and is sent to the frequency error detection unit 5. Frequency error detection unit 5, a pulse width modulation detection signal S _DT to detect a frequency error (PW
M) Send to the unit 6. The PWM unit 6 outputs the PWM signal p by performing pulse width modulation on the detection signal S _DT .

A PWM signal p output from the PWM unit 6
Contains the error amount as a DC component. So PWM
The signal p is sent to a low pass filter (LPF) 7 for extracting a DC component. The DC component obtained through the LPF 7 is sent to the VCXO 2 as the control signal S _CT ,
The oscillation frequency of the clock CLK sent to the PN code generator 3 is corrected.

Here, as shown in FIG. 9, the PWM device 8 forming the PWM unit 6 continuously changes the attribute of the pulse according to the change in the amplitude of the modulation signal. The PWM device 8 is
Based on the operation clock CLK input to the n-bit binary counting circuit 9, the cycle n is a multiple of the operation clock CLK.
Binary count signal c of bits: delivering c ₁ to c _n to the basic waveform generating circuit 10.

[0007] The basic waveform generating circuit 10, binary count signal c ₁ to c _n is used to generate the PWM waveforms from the n basic waveforms a: generate a ₁ ~a _n, the PWM waveform generation circuit 11 in parallel Send out. The basic waveform a is a waveform that allows pulse width modulation by the product of the data signal S _D and each bit. The PWM waveform generation circuit 11 generates a PWM signal p which is pulse width modulated from the basic waveforms a _{1 to} a _n input in n bits and the data signal S _D input in parallel in n bits.

As shown in FIG. 10, the basic waveform generating circuit 10
Is the count signal c ₁ to c _n of n bits to the most significant bit (MSB) is input from the least significant bit (LSB), MSB from the LSB of the basic waveform signal a ₁ ~a _n used in this PWM
Is output in correspondence with. The Figure 11 shows one cycle of the waveform of the binary count signals c ₁ to c ₄ of 4 bits. FIG.
Shows a waveform of one cycle of the basic waveform signals a _{1 to} a ₄ used for generating the PWM waveform obtained by synthesizing the binary count signals c _{1 to} c ₄ described above. For example, the basic waveform signal a ₄ has a time ratio of high level “Hi” and low level “Lo” of 1/2, and the basic waveform signals a ₃ , a ₂ and a ₁ have ratios of 1/4 and 1/8, respectively. , 1/16. Moreover, each of the basic waveform signals a _{1 to} a ₄ is a signal that does not overlap with each other where "Hi" is present in time.

The PWM signal p is an n-bit data signal S
A waveform signal consisting of m = 2 ⁿ kinds of PWM signals p ₁ ~p _m depending on _D. FIG. 13 shows a 4-bit data signal S _D
The PWM signal p after the pulse width modulation is shown, and the PWM signals p _{1 to} p ₁₆ correspond to “0000” to “1111” of the binary data signal S _D input in parallel. For example, if the data signal S _D is “0101” (MSB ← LSB), the PWM signal p ₆ is output by combining the basic waveform signals a ₁ and a ₃ .

[0010]

By the way, in the pulse width modulator 1 as described above, since the PWM waveform has a low frequency spectrum, there is a problem in that the loss of the DC component due to the low-pass filter of the PWM waveform is large. It was In addition, since the low frequency component remains in the PWM waveform, the cutoff frequency of the low pass filter cannot be increased. The present invention has been made in view of the above points, and an object thereof is to propose a pulse width modulation device that generates a PWM waveform having a spectrum of a high frequency.

[0011]

In order to solve such a problem, according to the present invention, a counter for multiplying a clock signal to generate a plurality of count signals having different frequencies, and a counter having the highest frequency among the plurality of count signals. The lowest bit having the spectrum of is the basic waveform signal of the highest bit, and thereafter, the inverted output of each count signal is sequentially calculated, and the accumulation with each count signal corresponding to the higher bit is sequentially repeated. Basic waveform generating means for sequentially generating basic waveform signals lower than the most significant bit according to the predetermined count signal by integrating the integrated value and the predetermined count signal, the data signal and the basic waveform. And a pulse width modulation means for generating a pulse width modulation waveform signal by a product-sum operation with the signal.

Pulse width modulation having a spectrum of high frequency by pulse-width modulating the data signal by product-sum calculation with the basic waveform signal having a spectrum of high frequency characteristic thus generated A signal can be generated.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Configuration of Frequency Error Correction Device In FIG. 1, in which parts corresponding to those in FIG.
Is a frequency error correction device, and determines the generation timing of the PN code generated by the PN code generator 3 by the clock CLK output from the VCXO 2 which controls the oscillation frequency by the voltage. From this PN code generator 3, a PN code PN whose frequency error has been corrected is output to the multiplication unit 4. Multiplying unit 4 demodulates the I connexion received signal S _R to be subjected to exclusive OR operation is sent to the frequency error detection unit 5 with respect to the received signal S _R by using a PN code PN. The frequency error detector 5
When the frequency error is detected, the detection signal S _DT is sent to the PWM unit 21. The PWM unit 21 outputs the PWM signal q by performing pulse width modulation on the detection signal S _DT . By the way, P
The WM signal q is m = in accordance with the n-bit data signal S _D.
There are 2 ⁿ types of waveform signals.

A PWM signal q output from the PWM unit 21
Contains the error amount as a DC component. So PWM
The signal q is sent to the LPF 7 to extract the DC component. The DC component obtained through the LPF 7 is the control signal S
The oscillation frequency of the clock CLK sent to the VCXO 2 as _CT and sent to the PN code generator 3 is corrected.

The PWM signal q input to the LPF 7 is shown in FIG.
And the control signal S _CT for controlling the frequency of the VCXO2 output from the LPF 7 are shown. According to this graph, for example, in the case of the PWM signal q ₂ , the voltage VT of the control signal S _CT output from the LPF 7 becomes V ₂ .

(2) Configuration of Pulse Width Modulator In FIG. 3, in which parts corresponding to those in FIG.
Reference numeral 5 denotes a PWM device forming the PWM unit 21, and FIG.
Operation clock CL input to the binary counting circuit 9 shown in
Binary count signal c n bits obtained by multiplying the cycle of the operation clock CLK based on K: generate c ₁ to c _n, and sends to the basic waveform generating circuit 26. Basic waveform generation circuit 26
The basic waveform of the n used in generating the binary count signals c ₁ to c _n from PWM waveform b: generate a b ₁ ~b _n sends the PWM waveform generation circuit 11 in parallel. The PWM waveform generation circuit 11 generates and outputs a pulse width-modulated PWM waveform q from an n-bit input basic waveform b and an n-bit parallel input data signal S _D.

As shown in FIG. 4, the basic waveform generating circuit 26
First, the binary count signal c ₁ which is the least significant bit (LSB) of the binary count signal c is set to the most significant bit of the basic waveform signal.
The basic waveform signal b _n of (MSB) is output from the first output unit 30 as it is. Next, the basic waveform signal b which is the MSB
_The AND element A ₁ outputs the basic waveform b _n-1 which is one bit lower than _n as a product of the binary count signal c ₁ and the binary count signal c ₂ inverted by the NOT element I ₁ .

Subsequently, the NOT element I ₁ and the NOT element I ₂
The two inverted outputs of the binary count signals c ₁ and c ₂ inverted by are input to the AND element AN ₁ to calculate the product of the two inverted outputs. Next, by the AND element A ₂ , the binary count signal c ₃ corresponding to the upper bit and the AND element A 2
The product with the output of N ₁ is calculated and output as the basic waveform b _n-2 .

Hereinafter, the basic waveform signal b is first generated by NO.
The T element I calculates all inverted outputs of the binary count signal c which is a lower bit with respect to the predetermined binary count signal c. Next, the AND element AN sequentially calculates all products of the inverted outputs from the least significant bit. Then A
The ND element A calculates the product of the output of all products of the inverted output and a predetermined binary count signal c. This gives LS
AND element A ₁ comprising a binary count signal c ₁ to c basic waveform signal MSB to LSB in correspondence with _n b _n ~b ₁ a first output portion 30 and a second output section 31 to MSB from B ~
It can be sequentially output from A _n .

Here, all bit signals of the basic waveform signal b are generated.
The high-frequency LSB binary count signal c₁
Will be used. As a result, the basic waveform signal b₁
~ B _nMust have a high frequency spectrum
You. Here, the binary count signal c₁~ C_nTo basic waveform b
₁~ B_nThe general formula for deriving

[Equation 1] Is represented by

FIG. 5 shows a waveform for one period of basic waveforms b _{1 to} b ₄ from LSB to MSB when the binary count signal c is a 4-bit signal. The basic waveform signal b ₄ is a waveform in which the time ratio of “Hi” and “Lo” is 1/2, and the basic waveform signals b ₃ , b
_The ratios of ₂ and b ₁ are 1/4, 1/8, 1/16, and the portions of “Hi” do not overlap each other in terms of time. As a result, the basic waveform signals b _{1 to} b ₄ having a high frequency spectrum with a fine pulse width can be generated.

As shown in FIG. 6, the PWM waveform generation circuit 11
Inputs the LSB to MSB of the basic waveform signals b _{1 to} b _n and the LSB to MSB of the data signal S _D , and inputs them to the AND elements A _{1 to} A _n as two input values. As a result,
The AND elements A _{1 to} A _n output the products of the basic waveform signals b _{1 to} b _n and the LSB to MSB of the data signal S _D for each corresponding bit. Next, the output values of the AND elements A _{1 to} A _n are input to the OR elements R _{1 to} R _n-1 and the sum is calculated, so that the PWM signal q corresponding to the data signal S _D can be generated.

FIG. 7 shows PWM waveforms q _{1 to} q ₁₆ after the pulse width modulation of the data signal S _D when the data signal S _D is 4 bits and the data range is 2 ⁴ = 16 values. The PWM signals q _{1 to} q ₁₆ correspond to the binary data signals S _D [0000] to [1111] input in parallel. For example, when the data signal S _D is [0101] (MSB ← LSB), the basic waveform signal b ₁
And b ₃ are combined, and as a result, the PWM signal q ₆ is output. These PWM waveforms q _{1 to} q ₁₆ are generated by using a basic waveform signal having a pulse width as fine as possible and a frequency as high as possible. As a result, the PWM signal q
As a PWM signal q ₄ which is a part of the PWM waveform
The cutoff frequency of the LPF 7 can be increased by using q ₁₃ or the like.

As a result, the PWM waveform generation circuit 11 generates the basic waveform signal b having a high frequency spectrum with a fine pulse width, and the PWM signal having a fine pulse width in which the "Hi" state does not continue. It is possible to output q. As a result, the pulse width of the signal waveform of the PWM signal q can be shortened without changing the operation clock of the counting circuit and without increasing the device scale. As a result, the high frequency component of the PWM signal can be shifted to a high frequency band, and the loss of the DC component of the PWM signal due to the LPF 7 can be reduced.

Further, when the dynamic range of the pulse width modulated data signal S _D is narrow, the frequency error correction device 20 is provided by making the PWM signal having a high frequency spectrum correspond to the dynamic range of the data signal S _D. Since the cutoff frequency of the LPF 7 can be set high, the loss of the DC component can be further reduced.

In the above-mentioned configuration, the reception signal S _R is demodulated by being subjected to the exclusive OR operation with the PN code PN in the multiplication unit 4 and sent to the frequency error detection unit 5. The detection signal S _DT due to the frequency error detected by the frequency error detection unit 5 is sent to the PWM unit 21. The PWM unit 21 generates a binary count signal c ₁ to c _n of the original n-bit operation clock CLK in binary count circuit 9,
It is sent to the basic waveform generation circuit 26.

The basic waveform generating circuit 26 first sequentially calculates each inverted output of the binary count signal c which is a lower bit with respect to the predetermined binary count signal c. Then, all products of the inverted outputs are calculated, and the product and a predetermined binary count signal c
The basic waveform signal b corresponding to the predetermined binary count signal c is generated by taking the product of the two. As a result, the lower bit binary count c having a high frequency spectrum is used to synthesize all the basic waveform signals b.

The PWM waveform generation in parallel thus generates a fundamental waveform b ₁ ~b _n of n types used to generate the basic waveform generating circuit 26 to Yotsute binary count signal c ₁ to c _n from PWM waveform It is sent to the circuit 11. The PWM waveform generation circuit 11 outputs the product of each bit by associating the LSB to MSB of the basic waveform signals b _{1 to} b _n with the LSB to MSB of the data signal S _D , and calculates the sum of all products. Thus, PWM waveforms q _{1 to} q _m according to the data signal S _D are generated.

The PWM section 21 outputs a PWM signal q having a pulse-width modulated high frequency spectrum. The PWM signal q is sent to the VCXO 2 via the LPF 7 and corrects the oscillation frequency of the clock CLK sent to the PN code generator 3.

According to the above configuration, the binary counting circuit 9
Then, the basic waveform signal b is generated by multiply-add operation from each binary count signal c generated by multiplying the operation clock CLK. Here, the higher-order bits are sequentially inverted from the LSB of the binary count signal having a high frequency, and the basic waveform signal b is generated by summing all products of the inverted outputs and the predetermined binary count signal c. By doing so, the basic waveform signal b can be formed to have a high frequency spectrum.

As a result, the PWM waveform generation circuit 11 can generate a PWM signal q having a high frequency spectrum with a fine pulse width in which "Hi" does not continue, and the frequency component of the PWM signal is increased. Can be shifted to the zone. In this way, the pulse width of the signal waveform of the PWM signal q can be shortened without changing the operation clock CLK of the counting circuit and without increasing the device scale. This makes the PWM signal L
The loss of the DC component due to the PF 7 can be reduced.

Further, according to the present invention, for example, PWM signals q _{4 to} q ₁₃ having a high frequency spectrum are used in correspondence with the dynamic range of the data signal S _D. As a result, the control voltage S _CT of the frequency error correction device 20 is
It is possible to raise the cutoff frequency of the LPF 7 for generating the signal, and it is possible to further reduce the loss of the DC component of the PWM signal.

In the above-described embodiment, the case where the present invention is used for demodulating a received signal by a CDMA mobile phone has been described, but the present invention is not limited to this and may be widely used for general pulse width modulation.

[0035]

As described above, according to the present invention, the lowest bit having the spectrum of the highest frequency among the plurality of count signals transmitted from the counter and having different frequencies is used as the basic waveform signal of the highest bit. , And the following, sequentially, by calculating the inverted output of each count signal and sequentially repeating the integration with each count signal corresponding to the upper bit, and the predetermined count signal by integrating the integrated value obtained A basic waveform signal having a high frequency spectrum is generated by sequentially generating basic waveform signals corresponding to the signals, and the pulse width modulation of the data signal is performed by multiply-add operation with the basic waveform signal. Thus, it is possible to realize a pulse width modulation device capable of generating a pulse width modulation signal having a high frequency spectrum.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a frequency error correction device according to an embodiment.

FIG. 2 is a graph for explaining a control voltage with respect to a pulse width modulation waveform.

FIG. 3 is a block diagram showing the overall configuration of a pulse width modulation device according to the present invention.

FIG. 4 is a schematic diagram showing a configuration of a basic waveform generation circuit according to the present invention.

FIG. 5 is a schematic diagram for explaining a basic waveform signal according to the present invention.

FIG. 6 is a schematic diagram for explaining a PWM waveform generation circuit.

FIG. 7 is a schematic diagram for explaining a pulse width modulation waveform.

FIG. 8 is a block diagram showing a configuration of a conventional frequency error correction device.

FIG. 9 is a block diagram showing a configuration of a conventional pulse width modulation device.

FIG. 10 is a schematic diagram showing a configuration of a conventional basic waveform generation circuit.

FIG. 11 is a schematic diagram for explaining a 4-bit count signal.

FIG. 12 is a schematic diagram for explaining a conventional basic waveform signal.

FIG. 13 is a schematic diagram for explaining a conventional pulse width modulation waveform.

[Explanation of symbols]

1 ... Frequency error correction device, 2 ... VCXO, 3 ... P
N generator, 4 ... Multiplier, 5 ... Frequency error detector,
6, 21 ... PWM section, 7 ... LPF, 8, 25 ... P
WM device, 9 ... Binary counting circuit, 10, 26 ... Basic waveform generation circuit, 11 ... PWM waveform generation circuit, I ₁ ...
I _n-1 ...... NOT element, AN _{1 to} AN _n-1 , A _{1 to} A _n
...... AND _{element, R 1 ~R n-1 ......} OR element.

Claims (3)

[Claims] 1. A counter for multiplying a clock signal to generate a plurality of count signals having different frequencies, and a basic waveform signal of a highest bit of a lowest bit having a spectrum of the highest frequency among the plurality of count signals. In the following, the predetermined value is obtained by sequentially calculating the inverted output of each count signal and sequentially repeating the integration with each count signal corresponding to the upper bit and the integration value obtained by multiplying the predetermined count signal. Basic waveform generating means for sequentially generating a basic waveform signal lower than the most significant bit basic waveform signal according to the count signal of the pulse width modulation waveform by a product-sum operation of the data signal and the basic waveform signal. And a pulse width modulating means for generating a signal. 2. The basic waveform generating means includes a first output section for outputting the most significant bit of the basic waveform signal, and a plurality of NOTs for calculating inverted outputs of the count signals lower than the most significant bit. An element and a plurality of first AND elements for calculating a product of inverted outputs of the NOT elements, and a product of each of the inverted outputs calculated by the plurality of first AND elements and the predetermined value. A second output section for outputting a lower bit than the uppermost bit of the basic waveform signal, which is composed of a plurality of second AND elements for calculating respective products with the count signal, and the first output section counts the above The least significant bit is output to the output as the most significant bit of the basic waveform signal, and a plurality of NOT signals are provided for a predetermined count signal higher than the least significant bit of the count signal. A plurality of said first AND sequentially calculated from the least significant bit of the I connexion each the inverted output to the child
All the products of each of the inverted outputs are calculated by the elements, and the product of the product and the predetermined count signal is added to the second AND.
2. The pulse width modulation according to claim 1, wherein a basic waveform signal lower than the basic waveform signal of the highest bit is generated according to the predetermined count signal by calculating by a device. apparatus. 3. The pulse width modulation means executes a product-sum operation with the data signal using the basic waveform signal corresponding to a predetermined range, which corresponds to a part of the dynamic range of the data signal. The pulse width modulator according to claim 1.