JPH0626345B2 - FSK signal demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention is an FSK (Frequency Shift Key) system that encodes information by assigning predetermined frequencies to two types of information called marks and spaces. The present invention relates to a demodulator for demodulating a modulated signal into a signal represented by original marks and spaces.

[Prior Art] In FSK modulation, for example, as shown in FIG. 4, digital data (mark) having a logical value "1" has a frequency f1, and digital data (space) having a logical value "0" has a frequency f2.
(However, f1 = f2) is a kind of frequency modulation method represented by an FM wave.

Conventionally, a signal modulated by this FSK modulation (hereinafter, F
In order to demodulate the signal (referred to as SK signal) to the signal represented by the original mark and space, in a radio receiver or the like, a high frequency FSK signal is divided into two types of low frequency signals by heterodyne. It was general to convert the signal into a frequency FSK signal and perform mark / space discrimination demodulation for these signals.

For example, in the demodulator of the conventional example shown in FIG. 5, an FSK signal composed of a high-frequency FM wave is supplied to a pair of tuning circuits 1 and 2 having different resonance frequencies, and each tuning circuit is supplied. The signals S1 and S2 generated in the rectifier circuits 3 and 4 continuously connected to 1 and 2 are added by the voltage adding circuit 5, and the output signal S3 of the voltage adding circuit 5 is compared with a preset reference voltage by the comparator 6. Then, the binary level signal of the mark and the space is discriminated from the magnitude relationship with the reference voltage.

Further, as shown in FIG. 6, a phase comparison circuit 7 for comparing the phases of the FSK signal SIN and the signal from the voltage controlled oscillation circuit,
The low-pass filter 8 and the voltage-controlled oscillation circuit 9 whose oscillation frequency changes in proportion to the output voltage of the low-pass filter are provided, and the frequency of the input FSK signal and the oscillation frequency of the voltage-controlled oscillation circuit are always the same. There is known a demodulator that generates a demodulated signal S0 by forming a phase-locked loop that is fed back so as to keep it.

Further, in order to improve the sensitivity in wireless communication or the like, it is necessary to remove various noises generated during transmission and efficiently detect the mark signal and space signal to be demodulated. Therefore, in the FSK signal demodulator as shown in FIG. 5, the pass band is narrowed by increasing the Q of the tuning circuit that discriminates between the frequencies f1 and f2, and
In the PLL type demodulator as shown in the figure, the S / N ratio of the signal is increased by adopting a technique such that the pass band is narrowed equivalently by increasing the time constant of the loop filter.
The ratio was improved to improve the sensitivity of the demodulator.

[Problems to be Solved by the Invention] However, in such a conventional FSK signal demodulator, the discrimination ability is deteriorated due to the occurrence of a transient phenomenon such as ringing as the Q of the tuning circuit is increased. There was a problem inviting. According to the experiment by the inventor of the present application,
For example, when Q is set to 20 or more for an FSK signal of 45.5 baud and 170 Hz shift, an increase in the error rate is recognized.

Further, conventionally, since the analog technology is used, there are drawbacks such that the adjustment peculiar to the analog circuit is complicated, the number of parts is increased, and the size of the entire apparatus is increased.

In addition, an ideal FSK signal demodulator based on information theory
Assuming that the analog signal technology is used, for example, as shown in FIG. 7, in the reference signal generator 10, sinusoidal wave signals Sf1 and Sf having the same frequency with a mutual phase difference of 90 ° are different.
2 is generated, the multiplier 11 multiplies the FSK signal SIN and the sine wave signal Sf1, and then the output is integrated by the integrator 13, thereby performing the cross-correlation calculation process of the signals SIN and Sf1. Similarly, in the multiplier 12, the FSK signal SIN is multiplied by the sine wave signal Sf2, and then the output is integrated by the integrator 14, thereby performing the cross-correlation calculation process of the signals SIN and Sf2. To do.

Then, the square operation of the cross-correlation value output output from each of the integrators 13 and 14 is performed by the square operators 15 and 16, and the operation outputs are added by the adder 17, and then the square root operator 18 is used. Obtain the square root, and use this output as the demodulated signal.

With such a demodulator, an extremely narrow pass band corresponding to the reciprocal of the time constant of the integrator can be realized without causing signal distortion, and high-sensitivity signal detection can be realized. .

However, in order to realize such a demodulator, a signal generator for forming a sine wave signal having a phase difference of 90 °, a plurality of multipliers for multiplying an analog signal, and a square root operation are required. There is a problem that the circuit is complicated and adjustment is difficult because an analog calculator for performing the operation is required.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a FSK signal demodulator that is easy to manufacture and is extremely small, by applying digital circuit technology.

[Means for Solving the Problem] FIG. 1 is a block diagram showing the principle of the present invention. The principle of the present invention will be described with reference to the figure. The transmitted FSK signal S
A waveform shaping circuit 19 for controlling the amplitude of IN to a constant level and converting it to a binary signal of "H" and "L" is provided, and the digital signal output from the waveform shaping circuit 19 is multiplied by four multipliers 20. , 21, 22, 23.

The reference signal generator 24 supplies the reference signal S11 having a frequency f _m equal to the FM wave corresponding to the mark to the multiplier 20, and the frequency f having a phase difference of 90 ° from the reference signal S11.
The reference signal S12 of _m is supplied to the multiplier 21.

The reference signal generator 25 supplies the reference signal S21 of the frequency f _s equal to the FM wave corresponding to the space to the multiplier 22, and also generates the reference signal S22 of the frequency f _s having a phase difference of 90 ° from the reference signal S21. It is supplied to the multiplier 23.

The multipliers 20, 21, 22, and 23 implement a multiplication process by performing a negation operation of the exclusive OR.

Then, each multiplier 20, 21, 22, 23 performs a product operation of the input signal, and outputs the respective outputs by integrators 26, 27, 28,
29, and the respective integration results are compared by comparators 30, 31, 32, 33 having a predetermined threshold value, and a binary value digital value signal according to the magnitude relationship with the threshold value is formed. Then, the logical sum operation of the digital value signals output from the comparators 30 and 31 is performed in the determination circuit 34, and the logical sum operation of the digital value signals output from the comparators 32 and 33 is performed in the determination circuit 35, respectively. If the output is true and the output of the determination circuit 35 is false, the output of the "H" level, the determination circuit 3
If the output of 4 is false and the output of the determination circuit 35 is true, "L"
If the level output and the outputs of the determination circuits 34 and 35 are both true or false, the synthesizing circuit 36 generates an output of the same level as the previous determination result.

[Operation] In the present invention having such a configuration, the determination circuit 3
Since the outputs of 4 and 35 are the detection results of the respective frequencies f _m and f _s , the mark and the space are judged from the relationship of the logical values of the respective outputs, and “H” is given to the mark and “H” is given to the space. Discrimination demodulation can be performed by outputting a logic signal of L ″ level.

Further, when the outputs of the determination circuits 34 and 35 both have the same logical value, it is decided to follow the previous demodulation result, so that noise and the like during transmission can be removed.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

First, the configuration will be described with reference to FIG. 2. Reference numeral 37 denotes a waveform shaping circuit having a limiter function. As shown in FIG. 3, the input FSK signal SIN is amplitude-limited to "H" and "L". The digital signal SD of the level is converted.

38 4 times the frequency 4 × _{f m} of the FM wave corresponding to the mark
Is a multi-vibrator that oscillates a rectangular signal sequence, and the rectangular signal sequence is divided by a quarter frequency dividing circuit 39 to form a first reference signal S11 having a frequency of f _m . Delay circuit 40 consisting of a flip-flop
Then, the second reference signal S12 having a frequency f _m and a phase difference of 90 ° is formed by delaying by one cycle and then dividing by the quarter frequency dividing circuit 41.

The digital signal SD and the first reference signal S11 are logically operated by the exclusive OR circuit (hereinafter, EXOR) 42, and then are negatively operated by the inverter circuit 43, and the resistor 44 and the capacitive element 4 are operated.
5 is supplied to an integrating circuit having a predetermined time constant.

The digital signal SD and the second reference signal S12 are EXOR
After being logically operated by 46, the inverter circuit 47 performs a negative operation, and the result is supplied to an integrating circuit having a predetermined time constant composed of a resistor 48 and a capacitive element 49.

The inverters 43 and 47 can be moved to another part or omitted by performing an appropriate logic conversion.

Reference numeral 50 denotes a logical sum circuit in which a predetermined threshold value TH is set in advance by the CMOS structure, and compares the magnitude relationship between the integrated signals D11 and D12 ″ generated at both ends of the capacitive elements 45 and 49 with the threshold value TH, and at the same time logically compares them. A sum operation process is performed, so that a logical output D13 shown in the following table is generated.

51 is a frequency 4 × f which is four times as high as the FM wave corresponding to the space.
is a multivibrator that oscillates a rectangular signal sequence of _s ,
This rectangular signal sequence is divided by a quarter divider 52 to form a third reference signal S21 having a frequency f _s , while the delay circuit 5 including a JK flip-flop is used.
After delaying one cycle in 3, the quarter divider circuit 54
By dividing by, a fourth reference signal S22 having a frequency of f _s and a phase difference of 90 ° is formed.

The digital signal SD and the third reference signal S21 are EXOR56
Then, the inverter circuit 57 performs a negative operation, and the result is supplied to an integrating circuit having a predetermined time constant composed of a resistor 58 and a capacitive element 59.

The digital signal SD and the fourth reference signal S22 are EXOR
After being logically operated by 60, the inverter circuit 61 performs a negative operation, and the result is supplied to an integrating circuit having a predetermined time constant composed of a resistor 62 and a capacitive element 63. The inverter circuits 57, 61
Can be moved or omitted like 43 and 47 described above.

Reference numeral 64 denotes a logical sum circuit in which a predetermined threshold value TH is set in advance by the CMOS structure, and compares the magnitude relation between the integrated signals D21 and D22 generated at both ends of the capacitive elements 59 and 63 with the threshold value TH, and at the same time, performs a logical sum. Perform arithmetic processing. Therefore, the logical output D23 shown in the following table is generated.

Next, a circuit corresponding to the decision circuits 34 and 35 and the synthesizing circuit 36 of FIG. 1 will be described. A logical product circuit 65 performs a logical product operation of the signal D'23 and the signal D13 inverted by the inverter circuit 66. The AND circuit 67 performs the AND operation on the signal D'13 and the signal D'23 inverted by the inverter circuit 68, and the AND circuit 69 performs the AND operation on the signals D13 and D23,
A logical sum circuit 70 performs a logical sum operation on the logical outputs of the logical product circuits 67 and 69.

Reference numeral 71 is an analog switch for controlling the opening / closing operation between the output of the logical product circuit 65 and the output terminal 72 according to the output signal of the logical sum circuit 70, and the capacitance element 73 is connected to the output side contact.

Then, the demodulated signal S ₀ shown in the following table is output to the output terminal 72 according to the logic level of the signals D13 and D23.

When D13 = "H" and D23 = "H", or when D13 =
When “L” and D23 = “L”, the output of the OR circuit 70 becomes “L” level, so that the analog switch 71 becomes non-conductive, and the voltage of the level held in the capacitive element 73 at the previous timing. Becomes the demodulated signal S0 as it is, and erroneous demodulation due to noise components is prevented.

As described above, according to this embodiment, the pass band of the signal in the demodulator is determined by the time constant of the integrator, which is compared in the demodulation of the FSK signal modulated with the code of the same speed. In this case, this embodiment is about 5 times narrower than the conventional analog system, and the S / N ratio is improved by that amount, and at the same time the demodulation sensitivity is improved.

Further, since the conventional analog technology is not used, the adjustment becomes easy, the circuit becomes simple, and the device can be downsized.

In this embodiment, the case where each processing function is configured by an individual circuit is shown. However, a part or all of the circuit includes an electronic arithmetic processing by an electronic computer, that is, a microprocessor for performing arithmetic processing according to a computer program. The same processing function may be achieved by replacing

[Effects of the Invention] As described above, since the present invention is configured by the digital logic operation technique, the number of parts such as the capacitive element, the resistance, and the inductance element as in the conventional analog method is significantly reduced, and It can be miniaturized. Also, since no inductance element is required, an integrated circuit (IC,
Suitable for LSI). In addition, it is easy to realize a device including a microcomputer and the like. Further, it can be easily realized by using an electronic arithmetic unit such as a microcomputer, and it is suitable for high performance and miniaturization of the unit.

Also, since adjustments such as temperature compensation peculiar to analog technology are almost eliminated, adjustments are easy and reliability can be improved.

Based on the above, the present invention can provide an FSK signal demodulator which is superior in performance, small in size and light in weight and excellent in economical efficiency as compared with the conventional analog system.

[Brief description of drawings]

FIG. 1 is a principle explanatory diagram for explaining the principle of the present invention; FIG. 2 is a circuit diagram showing a configuration of an embodiment of the present invention; FIG. 3 is an explanatory diagram for explaining the function of a waveform shaping circuit; FIG. 4 is an explanatory diagram showing the relationship between FSK modulation and demodulation signals; FIGS. 5, 6 and 7 are conventional configuration explanatory diagrams showing the configuration of a conventional demodulator. Reference numerals in the figure: 19, 37; waveform shaping circuit 20, 21, 22, 23; multiplier 24, 25; reference signal generator 26, 27, 28, 29; integrator 30, 31, 32, 33; comparator 34, 35; Judgment circuit 36; Combining circuit 38, 51; Multivibrator 40, 53; Delay circuit 39, 41, 52, 54; Quarter divider circuit 42, 46, 56, 60; Exclusive OR circuit 43 , 47, 57, 61, 66, 68; Inverter circuit 44, 48, 58, 62; Resistor 45, 49, 59, 63, 73; Capacitance element 50, 64, 70; OR circuit 65, 67, 69; Logic Product circuit

Claims (2)

[Claims] 1. An FSK signal demodulator for demodulating an FSK signal obtained by modulating a time-series signal of a mark and a space into two kinds of signals having different frequencies into an original time-series signal, and an amplitude modulation component of the FSK signal. , A waveform shaping means for generating a digital signal consisting only of frequency components, and an exclusive OR between the first reference signal consisting of a rectangular pulse wave equal to the first frequency to be detected and the digital signal. After performing an operation and integrating an output signal by the logical operation, the integrated operation output value is compared with a specific threshold value and converted into a first digital value signal of a level according to the magnitude of each value. And the second reference signal equal to the first frequency to be detected and having a phase difference of 90 ° with each other between the first reference signal and the digital signal of the waveform shaping means. Logical sum And integrating the output signal by the logical operation, comparing the integrated operation output value with a specific threshold value, and converting into a second digital value signal of a level according to the magnitude of each value. It comprises a conversion means, a first operation means for performing a logical sum operation of the first and second digital value signals outputted from the first and second conversion means, and a rectangular pulse wave having a second frequency to be detected. An exclusive OR operation is performed between the third reference signal and the digital signal output from the waveform shaping means, and the output signal is integrated by the logical operation, and then the integrated operation output value is compared with a specific threshold value. Then, the third converting means for converting into the third digital value signal of the level corresponding to the magnitude of each value and the second reference signal equal to the second frequency to be detected and having the second reference signal of 90 ° to each other. Fourth reference signal having a phase difference and the above waveform shaping After performing an exclusive OR operation with the digital signal of the stage and integrating the output signal by the OR operation, the output value of the integration operation is compared with a specific threshold value, and according to the magnitude of each value. Fourth converting means for converting into a fourth digital value signal of the level; second calculating means for performing a logical sum operation of the third and fourth digital value signals output from the third and fourth converting means; When the output of the first arithmetic means is true and the output of the second arithmetic means is false, it is determined to be true, and when the output of the first arithmetic means is false and the output of the second arithmetic means is false. When both the first and second arithmetic means are true or false, the previous determination result is applied to generate a mark signal for true determination and a space signal for false determination. FSK signal demodulator, characterized in that: 2. The FSK signal demodulator according to claim 1, wherein a part or all of the respective means are processed by an electronic arithmetic means.