JPH0385948A - Fsk signal demodulator - Google Patents

Abstract

PURPOSE:To obtain a signal demodulator formed easily with small size by deciding a mark and a space according to the logical value of each output of a deciding circuit and outputting an H level logic signal to the mark and an L level logic signal to the space to attain discrimination and demodulation. CONSTITUTION:The output signal of a waveform shaping circuit 19 converting an FSK(frequency shift keying) signal into a digital signal is fed to multipliers 20-23, the output signals are integrated and each integration result is compared with a threshold level at a comparator to form the digital signal of a binary level according to the relation of quantity with respect to the threshold level. A deciding circuit 35 ORs the output signals of comparators 32, 33, and when the output of the deciding circuit 34 is true and the output of the deciding circuit 34 is false, an H level is outputted and when the output of the deciding circuit 34 is false and the output of the deciding circuit 35 is true, an L level is outputted from a synthesis circuit 36. Thus, the number of components is considerably reduced and the miniaturization of the device is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses the FSK (Frequency Shift Keying) method, which encodes information by assigning predetermined frequencies to two types of information called marks and spaces. The modulated signal is
This invention relates to a demodulator for demodulating a signal represented by original marks and spaces.

[Prior art] For example, as shown in FIG.
"Digital data (mark) of frequency fl, logical value"
0” digital data (space) at frequency f2 (
However, it is a type of frequency modulation method expressed by FM waves of fl=f2).

Conventionally, a signal modulated by this FSK modulation (hereinafter referred to as FSK modulation)
In order to demodulate a high-frequency FSK signal into the original signal represented by marks and spaces, a wireless receiver uses a hetero gain to convert the high-frequency FSK signal into two types of low-frequency signals with different frequencies. It has been common practice to convert the frequency into FSK signals and perform mark and space differential demodulation on these signals.

For example, in the conventional example demodulator shown in FIG. The signal S1.1.2 generated in the rectifier circuit 3.4 is continuously connected to S1.1.2. S2 is added by a voltage adder circuit 5, and a comparator 6 compares the output signal S3 of the voltage adder circuit 5 with a preset reference voltage, and calculates the binary value of mark and space based on the magnitude relationship with the reference voltage. Discriminate into bell signal.

Further, as shown in FIG. 6, a phase comparison circuit 7 compares the phase of the FSX signal SIN and the signal from the voltage controlled oscillation circuit.
, a low-pass filter 8, and a voltage-controlled oscillation circuit 9 whose oscillation frequency changes in proportion to the output voltage of the low-pass filter,
The demodulated signal SO
A demodulator that generates is known.

Furthermore, in order to improve sensitivity in wireless communications, etc., it is necessary to remove various noises generated during transmission and efficiently detect mark signals and space signals to be demodulated. Therefore, in the FSK signal demodulator shown in Fig. 5, the passband is narrowed by increasing the Q of the tuning circuit that discriminates between fl and fl frequencies, or the PLL signal demodulator shown in Fig. 6 is used. In this type of demodulator, by increasing the time constant of the loop filter to equivalently narrow the passband, the S/N ratio of the signal is improved and the sensitivity of the demodulator is improved. was aiming for

[Problems to be Solved by the Invention] However, in such a conventional FSK signal demodulator, as the Q of the tuning circuit is increased, transient phenomena such as ringing occur, resulting in a decrease in discrimination ability. There was a problem that led to

According to the inventor's experiments, for example, 45.5 baud 170
When Q was set to 20 or more for the Hz-shifted FSX signal, the error rate was found to increase.

Furthermore, since analog technology has been used in the past, there have been disadvantages such as complicated adjustments specific to analog circuits, an increase in the number of parts, and an increase in the size of the entire device.

In addition, an ideal FSX signal demodulator based on information theory,
If the structure is constructed using analog technology, for example, as shown in FIG.
2, the multiplier 11 multiplies the FSK signal SIN and the sine wave signal Sfl, and the output is integrated by the integrator 13 to obtain the signals SIN and Sfl.
Similarly, the multiplier 12 multiplies the FSK signal SIN and the sine wave signal Sf2, and the output is integrated by the integrator 14 to obtain the signals SIN and SF3. Performs cross-correlation calculation processing with

Then, the cross-correlation value output from each integrator 13.14 is squared by a square calculator 15.16, the calculated outputs are added by an adder 17, and then a square root calculator 18 is used. The square root (S squareRoot ) is calculated and the output is used as a demodulated signal.

According to such a demodulator, an extremely narrow passband corresponding to the reciprocal of the integrator time constant can be realized without causing signal distortion, and highly sensitive signal detection can be achieved. .

However, in order to realize such a demodulator, a signal generator for forming sine wave signals with a phase difference of 90 degrees, multiple multipliers for multiplying analog signals, and a square root operation are required. Since an analog arithmetic unit and the like are required to carry out the calculation, the circuit becomes complicated and there are problems such as difficulty in adjustment.

The present invention has been made in view of these problems, and an object of the present invention is to provide an FSK signal demodulator that is easy to manufacture and extremely compact by applying digital circuit technology.

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle configuration of the present invention. To explain the present invention in detail based on the figure, the transmitted FSK signal S
Control the amplitude of IN to a constant level and
It is equipped with a waveform shaping circuit 19 that converts the digital signal into a value level digital signal, and converts the digital signal outputted from the waveform shaping circuit 19 into
multipliers 20°21.22.23.

The reference signal generator 24 supplies a reference signal 811 with a frequency fm equal to the FM wave corresponding to the mark to the multiplier 20, and also supplies a reference signal SI2 with a frequency f+n having a phase difference of 90° from the reference signal Sll to the multiplier 20. 21.

The reference signal generator 25 supplies a reference signal S2+ with a frequency fs equal to the FM wave corresponding to the space to the multiplier 22, and also supplies a reference signal 322 with a frequency fs having a phase difference of 90 degrees from the reference signal S21 to the multiplier 22. 23.

Note that these multipliers 20, 21, 22, and 23 realize multiplication processing by performing a negative operation of exclusive OR.

Then, each multiplier 20, 21, 22, 23 performs a product operation of the input signals, and the respective outputs are sent to an integrator 26, 27, 28, 26, 27, 28, .
29, and each integration result is integrated by a comparator 30 having a predetermined threshold value. 31. 32. 33 to form a binary level digital value signal according to the magnitude relationship with the threshold value. Then, a logical sum operation of the digital value signals output from the comparators 30, 31 is performed in the determination circuit 34, and the comparators 32, 32, .
The logical sum operation of the digital value signals outputted in step 33 is performed in the judgment circuit 35, and if the output of the judgment circuit 34 is true and the output of the judgment circuit 35 is false, the output is n'' level, and the output of the judgment circuit 34 is false and false. If the output of the judgment circuit 35 is true, “
If the L'' level output and the outputs of the determination circuits 34 and 35 are both true or false, the synthesis circuit 36 generates an output of the same level as the previous determination result.

[Operation] In the present invention having such a configuration, the determination circuit 3
Since the outputs of 4 and 35 are the detection results of each frequency fm and fS, mark and space are determined from the relationship of the logical values of each output, and the level is set to "H" for marks and "L" for spaces. Discriminative demodulation can be performed by outputting a logical signal.

Further, when the outputs of the determination circuits 34 and 35 both have the same logical value, the previous demodulation result is followed, so that noise during transmission can be removed.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

First, the configuration will be explained based on FIG. 2. 37 is a waveform shaping circuit having a limiter function, and as shown in FIG. is converted into a digital signal SD.

38 is the frequency 4Xfm, which is four times the frequency of the FM wave corresponding to the mark.
This is a multivibrator that oscillates a rectangular signal train, and by dividing this rectangular signal train by a quarter frequency dividing circuit 39, a first reference signal 811 having a frequency fIll is formed. After the delay circuit 40 consisting of the
By dividing the frequency by 1-, a second reference signal 812 having a frequency of fIll and a phase difference of 90° is formed.

The digital signal SD and the first reference signal Sll are subjected to a logical operation in an exclusive OR circuit (hereinafter referred to as EXOR) 42, then inverted in an inverter circuit 43, and integrated with a predetermined time constant consisting of a resistor 44 and a capacitive element 45. Supplied to the circuit.

Moreover, the digital signal SD and the second reference signal S12 are EXO
After a logical operation is performed in R46, a negative operation is performed in an inverter circuit 47, and the resultant signal is supplied to an integrating circuit having a predetermined time constant and consisting of a resistor 48 and a capacitive element 49.

Incidentally, the inverters 43, 47 can be moved to another part or can be omitted by performing appropriate logic conversion.

Reference numeral 50 denotes an OR circuit in which a predetermined threshold value TH is set in advance using a CMO8 structure, and each integrated signal D1 . At the same time as comparing the magnitude relationship between I, [2'' and the threshold value TH, a logical sum calculation process is performed. Therefore, the logical output DI3 shown in the following table is generated.

51 is the frequency 4Xf, which is four times the frequency of the FM wave corresponding to the space.
It is a multivibrator that oscillates a rectangular signal train of s,
A third reference signal S21 having a frequency of fs is formed by dividing this rectangular signal train by a quarter frequency divider circuit 52, and a delay circuit 53 consisting of a JK flip-flop delays one period. After performing 1/4 frequency divider circuit 5
By dividing the frequency by 4, the frequency becomes fs and the phase difference is 90°.
A fourth reference signal 822 is formed.

Digital signal SD and third reference signal S21 are EXOR5
After the logic operation is performed in step 6, the signal is inverted in an inverter circuit 57, and is supplied to an integrating circuit with a predetermined time constant, which is made up of a resistor 58 and a capacitive element 59.

Moreover, the digital signal SD and the fourth reference signal 822 are EXO
After a logical operation is performed in R60, a negative operation is performed in an inverter circuit 61, and the resultant signal is supplied to an integrating circuit having a predetermined time constant, which includes a resistor 62 and a capacitive element 63. In addition, the inverter circuit 57.6
1 can be moved or omitted like 43.47 described above.

64 is an OR circuit in which a predetermined threshold value TH is set in advance using a CMO8 structure, and each integrated signal D21 . At the same time as comparing the magnitude relationship between D22 and the threshold value TH, a logical sum calculation process is performed. Therefore, the logic output D23 shown in the following table is generated.

Next, to explain the circuits corresponding to the determination circuits 34 and 35 and the synthesis circuit 36 in FIG. , the AND circuit 67 is the inverter circuit 6
The AND circuit 69 performs an AND operation on the signal D'13 inverted at 8 and the signal D'23, and the AND circuit 69 performs an AND operation on the signal DH and D23. Performs a logical OR operation.

Reference numeral 71 denotes an analog switch that controls the opening/closing operation between the output of the AND circuit 65 and the output terminal 72 according to the output signal of the OR circuit 70, and a capacitive element 73 is connected to the output side contact.

Then, depending on the logical value levels of signals D13 and D23,
A demodulated signal So shown in the following table is output to the output terminal 72.

In addition, DI3="H", D23="H" (7), l or G
i, D13="L", D23="L", the output of the OR circuit 70 becomes "L@ level", so the analog switch 71 becomes non-conductive, and the signal is held in the capacitive element 73 at the previous timing. The voltage at the same level is the demodulated signal S.
0, thereby preventing erroneous demodulation due to noise components.

Thus, according to this embodiment, the passband of the signal in the demodulator is determined by the time constant of the integrator, and this is compared by demodulating FSK signals modulated with codes of the same speed. Then, compared to the conventional analog system, this embodiment becomes about five times narrower, and the S/N ratio improves accordingly, and at the same time, the demodulation sensitivity improves.

Further, since conventional analog technology is not used, adjustment is easy, and the circuit is simple, making it possible to downsize the device.

Although this embodiment shows a case in which each processing function is configured with individual circuits, a part or all of the circuit may include a microprocessor that performs electronic arithmetic processing by an electronic computer, that is, arithmetic processing according to a computer program. It is also possible to perform the same processing function by replacing it with .

[Effects of the Invention] As explained above, since the present invention is constructed using digital logic operation technology, the number of components such as capacitive elements, resistors, and inductance elements that are required in conventional analog systems can be significantly reduced, and the number of components of the device can be improved. It becomes possible to downsize. Also, since no inductance element is required, the integrated circuit (IC1
Suitable for LSI implementation. Furthermore, it is easy to realize a device that also includes a microcomputer or the like. Furthermore, it is easy to implement using an electronic arithmetic device such as a microcomputer, and is suitable for increasing the functionality and downsizing of the device.

Furthermore, since adjustments such as temperature compensation, which are unique to analog technology, are almost eliminated, adjustments are easy and reliability can be improved.

In summary, the present invention can provide an excellent FSX signal demodulator that is high-performance, compact, lightweight, and economical compared to the conventional analog system.

[Brief explanation of drawings]

Fig. 1 is a principle explanatory diagram for explaining the present invention in detail; Fig. 2 is a circuit diagram showing the configuration of an embodiment of the present invention; Fig. 3 is an explanatory diagram explaining the function of the waveform shaping circuit; Figure 4 is FS
Explanatory diagram showing the relationship between K-scheme modulation and demodulation signals; FIGS. 5, 6, and 7 are conventional configuration explanatory diagrams showing the configuration of a conventional demodulator. Codes in the figure: 19.37; Waveform shaping circuit 20.21.22, 23; Multiplier 24.25; Reference signal generator 26.27, 28.29; Integrator 30.31.32.33; Comparator 34.35; Judgment circuit 36; Synthesizing circuit 38.51; Multivibrator 40.53; Delay circuit 39.41.52, 54; 1/4 frequency divider circuit 42.46.
56.60; Exclusive OR circuit 43, 47. 57.
61°66.68; Inverter circuit 44.48, 58.62; Resistor 45.49.59.63.73; Capacitive element 5O, 64,
70, OR circuit 65゜67゜69; AND circuit

Claims (2)

[Claims] (1) In an FSK signal demodulator that demodulates an FSK signal obtained by modulating mark and space time series signals into two types of signals with different frequencies into the original time series signal, the amplitude modulation component of the FSK signal is removed. waveform shaping means for generating a digital signal consisting only of frequency components; and performing an exclusive OR operation between the digital signal and a first reference signal consisting of a rectangular pulse wave equal to the first frequency to be detected. and after integrating the output signal of the logical operation, a first conversion of comparing the output value of the integral operation with a specific threshold value and converting it into a first digital value signal of a level corresponding to the magnitude of each value. and a second reference signal which is equal to the first frequency to be detected and has a phase difference of 90 degrees from the first reference signal, and the digital signal of the waveform shaping means. After performing the calculation and integrating the output signal resulting from the logical calculation, a second digital value signal that compares the output value of the integral calculation with a specific threshold value and converts it into a second digital value signal having a level corresponding to the magnitude of each value. a first calculation means that performs an OR operation of the first and second digital value signals output from the first and second conversion means; and a rectangular pulse wave equal to the second frequency to be detected. After performing an exclusive OR operation between the third reference signal and the digital signal output from the waveform shaping means, and integrating the output signal by the logical operation, the integral operation output value and a specific threshold value are A third conversion means that compares and converts the signal into a third digital value signal having a level corresponding to the magnitude of each value, and the second reference signal that is equal to the second frequency to be detected and is at an angle of 90 degrees from each other. After performing an exclusive OR operation between the fourth reference signal having a phase difference of 1 and the digital signal of the waveform shaping means, and integrating the output signal from the OR operation, a fourth conversion means that compares the signal with a threshold value and converts the signal into a fourth digital value signal having a level corresponding to the magnitude of each value; and third and fourth digital value signals output from the third and fourth conversion means. a second arithmetic means for performing a logical sum operation; and a state in which the output of the first arithmetic means is true and the output of the second arithmetic means is false, it is determined to be true, and the output of the first arithmetic means is false; If the output of the second calculation means is true, it is determined to be false, and when both the first and second calculation means are true or false, the previous determination result is applied and a mark is made for the determination of true. An FSK signal demodulator comprising: synthesis means for synthesizing demodulated signals by generating a space signal in response to a false determination. (2) The FSK signal demodulator according to claim 1, wherein processing of some or all of the means is performed by electronic calculation means.