JP2517028B2 - Frequency detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frequency detection circuit used for demodulating a signal frequency-modulated by an analog signal or a data signal, measuring a frequency deviation of an input signal, and the like.

[Conventional technology and its problems]

Conventionally, a ceramic discriminator, a quadrature detection circuit, etc. have been widely used as a frequency detection circuit for detecting a deviation amount of an instantaneous frequency of an input signal with respect to a predetermined center frequency.

However, these require devices such as ceramic elements and inductance elements for 90 ° phase shift that are not suitable for IC integration, and the carrier wave to be processed is limited to a specific intermediate frequency, so they can only be applied to heterodyne receivers. There was a problem in downsizing and generalization.

For this reason, in recent years, two local oscillation waves having the same frequency as the received wave or the intermediate frequency which is the input signal and having phases different from each other by π / 2 radians and the input signal are frequency-mixed. The frequency detection output is obtained by extracting baseband signals that are orthogonal to each other, phase-shifting each of these two baseband signals by π / 2 radians, and then performing analog multiplication with each of the other baseband signals. The so-called quadrature detection waveform is attracting attention as one of the circuit systems suitable for IC implementation.

Since this method can be applied even when no intermediate frequency is used, it has the advantage of being suitable for generalization and miniaturization, but it requires two analog multipliers. In order to realize an analog multiplier, it is possible to use a multiplier by analog operation that uses the physical characteristics of semiconductors, or an application of a digital multiplier via an A / D converter and a D / A converter. The temperature of
There is a problem of aging, and the latter has a problem that the circuit scale and the power consumption increase, and the practical problems are large.

[Means for solving problems]

The present invention was made in order to remove the obstacle in the circuit of the conventional quadrature detection waveform, the frequency detection characteristic is theoretically distortion-free, does not include unnecessary harmonics, and in realizing this, It is intended to provide a circuit that has a small circuit scale and is suitable for IC implementation.

That is, the circuit of the present invention generates first and second local oscillation outputs L _I and L _Q having the same frequency as the center frequency of the input signal R and having a phase difference of π / 2 radian with each other as shown in the first diagram. The local oscillator circuit 1 and the phase difference between the input signal R and the first local oscillation output L _{I and} the phase difference between the input signal R and the second local oscillation output L _Q are linearly raised and lowered for each π radian. 1st and 2nd with phase difference detection output characteristics repeated at 2π radians
Phase difference detection circuits 21, 22 and first and second phase difference detection circuits 21, 22
Output _{Q I} and θ _Q of each of the first and second level comparators 41 and 42, respectively, and the output C _{Q of} the second level comparator 42.
Input the output of either one of the first and second phase difference detection circuits 21 and 22 and the logic inverter 5 that logically inverts the A level judgment circuit 7 for making a binary judgment as to whether or not the input level is sandwiched between two threshold values located, and first and second phase difference detection circuits 2
First and second cascade connection parts 71, 72 each of which is connected to 1, 22 and is composed of a differentiator 31, 32 and a polarity switching circuit 61, 62 for switching and outputting the analog polarity of the input by the polarity switching input. , A switching circuit 8 for switching and outputting one of the outputs D ′ _I and D ′ _Q of the first and second cascade connection parts 71 and 72 according to the output C of the level determination circuit 7, and the output D of the switching circuit 8 to the base. A low pass filter 9 for extracting a band signal component, and the output ▲ ▼ of the logic inverter 5 is connected to the polarity switching input of the polarity switching circuit 61 of the first cascade connection portion 71, and the second cascade connection portion 72. The output C _I of the first level comparator 41 is connected to the polarity switching input of the polarity switching circuit 62, and the switching operation of the switching circuit 8 is such that the output level of the first phase difference detection circuit 21 is within the level determination circuit 7. When sandwiched between two threshold values, the output D' _I of the first cascade connection portion 71 is changed to the second phase difference. When the output level of the detection circuit 22 is sandwiched between two threshold values in the level determination circuit 7, the output D' _Q of the second cascade connection portion 72 is switched and output. 21,22
The frequency detection output S in which the influence of the differential discontinuity point of the phase difference detection characteristic of 1 is eliminated is obtained from the low-pass filter 9.

[Work]

It has the same frequency as the center frequency of the input signal R and has π
First and second local oscillation outputs L _I , L _Q with a phase difference of / 2 radian
Is taken out from the local oscillator circuit 1 and linearly rises every π radian with respect to the phase difference between the input signal R and the first local oscillation output L _{I and} the phase difference between the input signal R and the second local oscillation output L _Q , Phase difference detection outputs θ _I and θ _Q , which repeat the fall with a period of 2π radians, are obtained from the first and second phase difference detection circuits 21 and 22, respectively. These phase difference detection outputs θ _I and θ _Q are shaped into binary logic values by the first and second level comparators 41 and 42, respectively, and the output C _Q of the second level comparator 42 is inverted by the logic inverter 5. Then, the logic inversion output ▲ ▼ is obtained.

The output of one of the first and second phase difference detection circuits 21 and 22 is determined by the level determination circuit 7 between the maximum value and the average value,
In addition, whether or not the input level is sandwiched between two threshold values located between the minimum value and the average value is binary-determined, and the level determination circuit 7 obtains the level determination output C.

Further, the outputs θ _I and θ _{Q of} the first and second phase difference detection circuits 21 and 22
Are input to the first and second cascade connection parts 71 and 72, which are combinations of differentiators 31 and 32 and polarity switching circuits 61 and 62,
The polarity switching circuits 61, 62 of the first and second cascade connection parts 71, 72 are respectively fed with the output ▲ ▼ of the logic inverter 5 and the output C _{I of} the first level comparator 41 to input analog signals. The polarity is switched, and one of the outputs D ′ _I and D ′ _Q of the first and second cascade connection parts 71 and 72 is switched and output by the switching circuit 8 according to the output C of the level determination circuit 7.

That is, when the output level of the first phase difference detection circuit 21 is sandwiched between the two threshold values in the level determination circuit 7, the switching circuit 8 changes the output D' _I of the first cascade connection portion 71 to the second level. When the output level of the phase difference detection circuit 22 is sandwiched between the two threshold values in the level determination circuit 7, the output D' _Q of the second cascade connection portion 72.
And output. The low-pass filter 9 extracts a baseband signal component from the output D' _I or D' _Q (represented by the output D), and differentiates the phase difference detection characteristics of the first and second phase difference detection circuits 21 and 22. The frequency detection output S in which the influence of continuous points is eliminated is output.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the circuit of the present invention.

In FIG. 1, reference numeral 1 denotes a local oscillation circuit which generates first and second local oscillation outputs L _I and L _Q having the same frequency as the center frequency of the input signal R and having a phase difference of π / 2 radian. In this example, the second local oscillation output L _Q has a phase delay of π / 2 radian with respect to the first local oscillation output L _I.

Reference numerals 21 and 22 denote the first and second phase difference detection circuits, which input the input signal R and the first local oscillation output L _I , and the input signal R and the second local oscillation output L _Q, and input the phase difference θ between them. For period 2π
It has a phase difference detection characteristic that shows a linear rise and a fall for every π radian, and outputs phase difference detection outputs θ _I and θ _Q , respectively. The characteristics of these detection circuits 21 and 22 are as shown in FIG.

The first and second phase difference detection circuits 21 and 22 having such characteristics
Is a circuit configuration for performing an on / off switching operation based on an input signal R and a first local oscillation output L _I using a transistor, an input signal R and a second local oscillation output L _Q, or the first and second local oscillation outputs L _I , L _This can be easily realized by a circuit configuration for low-pass filtering the exclusive OR output of _Q and the input signal R. θ _I , θ _Q
Are the phase difference detection outputs of the first and second phase difference detection circuits 21 and 22, respectively, and the relationship of the phase difference detection characteristics of FIG.

31 and 32 respectively input the phase difference detection outputs θ _I and θ _Q ,
This is a differentiator that differentiates it, and D _I and D _Q are the differential outputs. 41 and 42 are first and second level comparators, respectively θ _I and θ
_Q is input, the magnitude relationship is determined by using each average value as a threshold value, and the binary value (H, L level) is converted. C _I ,
C _Q is the output of each comparison.

Reference numeral 5 is a logic inverter (inverter), which inputs the comparison output C _Q and outputs its logic inversion output ▲ ▼. 61 and 62 are differential output D _I , logical inversion output ▲ ▼, and differential output, respectively.
Input D _Q and comparative output C _I, and input ▲ ▼ and C _I respectively.
It is a polarity switching circuit for switching and outputting the polarities of D _I and D _Q according to the value states H level and L level. D' _I D' _Q are respective polarity switching outputs.

Such a function is such that the output of the polarity reversing circuit by the operational amplifier and its input are switched and output by the analog switch, and the reference input on the positive side of the operational amplifier is opened and grounded by the analog switch to invert or non-invert. This can be easily realized by a configuration for switching the operation.

7 is one of the phase difference detection outputs θ _I and θ _Q of the first and second phase difference detection circuits 21 and 22, and in this example, θ _Q is input, and the maximum value (+ V) and the average value (O ) And the intermediate value (+
V _T), and the minimum value of the input (intermediate value -V) and the average value (O) (whether the input level for two thresholds -V _T) is sandwiched between these thresholds This is a level determination circuit having a function of performing binary determination of whether or not. The level determination circuit 7 includes two level comparison circuits having thresholds of + V _T and −V _T ,
It can be easily configured by using an OR circuit or an AND circuit. C is the level judgment output. FIG. 2B shows an example of output characteristics of the level judgment circuit 7.

Reference numeral 8 denotes a switching circuit which inputs the polar positive switching outputs D' _I and D' _Q and switches and outputs either D' _I or D' _Q according to the polarity of the level determination output C, which can be realized by an analog switch. D is the switching output. Reference numeral 9 is a low-pass filter which inputs the switching output D, extracts the baseband signal component contained in the output D, and removes the noise component mixed in from the transmission line, and S is composed of the extracted baseband signal. This is the frequency detection output.

The operation of the embodiment of the present invention having the above configuration will be described.

FIGS. 2 (a) and 2 (b) are diagrams showing the phase difference detection characteristic examples of the first and second phase difference detection circuits 21 and 22 and the output characteristic example of the level determination circuit 7 in FIG. 1, respectively. The vertical axis represents the binary states of the phase difference detection outputs θ _I and θ _Q and the level determination output C, and the horizontal axis represents the phase difference θ (radian).

The characteristic shown by the solid line in FIG.
It is a characteristic example of the phase difference detection output θ _I when the phase difference of the input signal R with respect to the local oscillation output L _I , is based on the exclusive OR operation, and is the minimum value at the same phase (θ = 0). The V-shaped polygonal line characteristic that reaches V and reaches the maximum value + V in the reverse phase (θ = ± π) has one cycle.

At this time, the second local oscillation output L _Q is the first local oscillation output L _I
Because for a certain phase delay of [pi / 2 radians, the characteristics of the phase difference detection output theta _Q is the phase difference theta between said L _I, the theta characteristics of _I [pi / 2 as shown by a broken line The characteristics are shifted by radians.

The characteristic of the level determination output C in FIG. 2 (b) is that the level of θ _{Q in} FIG. 2 (a) is between two threshold values + V _T and −V _T , and is above + V _T , or An example in which binary states of “L” and “H” are exhibited corresponding to the case of −V _T or less is shown.

When the input of the level determination circuit 7 is θ _I ,
It is apparent from FIG. 2 (a) that the characteristics are completely equivalent if the circuit 7 is configured so as to obtain the binary state output of "H" and "L" opposite to the above with respect to the input. .

The principle of the frequency detection operation according to the configuration example of FIG. 1 will be specifically described first by using mathematical formulas based on the various characteristic examples shown in FIG.

Now, the time waveforms of the signals θ _I , θ _Q , D _I , D _Q , D ′ _I , D ′ _Q , D of FIG. 1 and θ of FIG. 2 are respectively θ _{I (t)} , θ _{Q ( t)} , D
_{I (t)} , D _{Q (t)} , D ′ _{I (t)} , D ′ _{Q (t)} , D _(t) , θ _(t) , and C
_The time waveforms obtained by replacing the binary states “H” and “L” of _Q and C _I with +1 and −1 rectangular waves are designated as C _{Q (t)} and C _{I (t)} . At this time, the following relational expressions can be derived from FIGS. 1 and 2.

D' _I = -D _{I (t)}・ C _{Q (t)} ………… (5) D ′ _{Q (t)} ＝ D _{Q (t)}・ C _{I (t)} ………… (6) where Since {C _{Q (t)} } ² = {C _{I (t)} } ² = 1, D ′ _{I (t)} can be _calculated from Eqs. (1), (3), and (5), and (2), From equations (4) and (6), D' _{Q (t)} is given as follows.

From equations (7) and (8), D ′ _{I (t)} and D ′ _{Q (t)} are theoretically the same waveform, and dθ _(t) / d _t , that is, the center of the input signal R Since D ′ _{I (t)} and D ′ _{Q (t)} are both proportional to the angular frequency deviation Δω with respect to the angular frequency, the frequency detection output S
Can be easily understood.

However, in the actual circuit operation, the time waveforms of the differential output waveforms D _{I (t)} , D _{I (t)} and the rectangular time waveforms C _{Q (t)} , C _{I (t) of the} comparison outputs C _Q , C _I Means that there is a slight change in the change time due to the difference in circuit operation delay.
In the output waveforms D' _{I (t)} and D' _{Q (t)} of, the thin pulses can be generated alternately in time. The period of this pulse is C _{Q (t)} , C _{I (t)}
Is equal to the period of the rectangular change point of, and occurs once every phase difference θ changes by π radians.

A specific example of the above frequency detection operation and the pulse generation phenomenon on D' _{I (t)} , D' _{Q (t) and} an operation example in which the influence thereof is eliminated by the level determination circuit 7 and the switching circuit 8 are shown in FIG. It will be described next.

FIGS. 3A and 3B show that the absolute value of the angular frequency deviation Δω of the input signal R with respect to the central angular frequency is relatively large (Δω = ± Δω _H ) and small (Δω = ±). 9 is a time chart showing an example of each time waveform of Δω _L ), that is, (Δω _H > Δω _L ). In the figure, the waveform shown by the solid line shows the case of Δω = + Δω _H , + Δω _L > 0, and the waveform shown by the broken line shows the case of Δω = −Δω _H , −Δω _L <0.

In FIG. 3 (a), since the change (phase rotation) of the phase difference θ is faster than that in (b ₎ , the triangular wave-like changes in θ _{I (t)} and θ _{Q (t)} are (b) in (a). ) Will be faster than. For this reason, the amplitude of the rectangular wave of these time differential waveforms D _{I (t)} and D _{Q (t)} is larger in (a) than in (b).

This means that the maximum and minimum values of D _{I (t)} and D _{Q (t)} are + v _H , and −v _H in the case of (a), and + v _H in the case of (b).
_{If L} and + v _L are set, the relation of the following equation is obtained from the equations (1) to (4). It is also clear from the fact that

On the other hand, C _{Q (t)} and C _{I (t)} are not shown in the figure, but
_Since it is equal to the binary shaped wave of _{Q (t)} and θ _{I (t)} to ± 1 level, it is almost equal to the waveform of −D _{I (t)} and D _{Q (t)} , respectively.
(5), and D 'I _(t) and D' Q _(t) is the waveform respectively D _{I (t)} and D _{Q (t)} is full-wave rectified from the relationship (6). However, in the case of Δω <0 (broken line), the phase of θ _{Q (t) based on} θ _{I (t)} is different from that of Δω> 0 (solid line) by π radian, so D ′ _{I (t)} , D ′ _{Q (t)} are both full-wave rectified in the negative direction.

In both cases of Δω> 0 and Δω <0, the commutation points in full-wave rectification operation are −D _{I (t)} and C _{Q (t)} , and D _{Q (t)} and C _{I (t).}
Since the changes in S do not exactly coincide with each other and there is a slight time difference, a narrow reverse polarity pulse is generated as shown in the figure.

Since this pulse is generated at an angular frequency of 2Δω, when Δω is small, the fundamental wave falls into the baseband signal band of the frequency detection output S and becomes a distortion component that cannot be removed by the low-pass filter 9, thus affecting the transmission quality. give.

When the binary logic waveform of the level judgment output C of the level judgment circuit 7 is C _(t) , C _(t) is + V _T > θ _{Q (t)} > −V _T as described in FIG. At “L”, θ _{Q (t)} ＞ ＋ V _(t) , θ _{Q (t)} <
Since it shows the movement to "H" at -V _T , Fig. 3 (a), (b)
The waveform is as shown in the second row from the bottom. Therefore, in this case, the switching output waveform D _{(t) of the} switching circuit 8 is If the operation logic of the switching circuit 8 is configured so that
_The alternate switching output that avoids the pulse generation points of _{I (t)} and D' _{Q (t)} is set as D _(t), and as shown in the bottom row of FIG.
_(t) is a frequency detection output signal having no distortion in the baseband signal band.

It should be noted that, due to the effect of eliminating unnecessary pulses by the level determination circuit 7 and the switching circuit 8 described above, the differentiator 31 or 32 shown in FIG.
Even in the configuration in which the cascade connection order of the positive polarity switching circuit 61 or 62 is switched, a completely equivalent operation can be obtained with respect to D _(t) .

That is, when the polarity switching circuits 61 and 62 are first connected to θ _I and θ _Q , respectively, differentiators 31, 3 that follow the polarity switching circuits 61 and 62 are connected.
The equivalent phase difference detection characteristic seen from the input of 2 is the sawtooth characteristic of the period π radian (of the characteristic of θ _{1 in} FIG. 2 (a),
(0>θ> −π), and the input waveforms of the differentiators 31 and 32 are sawtooth waves with an angular frequency of 2Δω. Therefore, the differential output thereof, that is, the input to the switching circuit 8 is Δω.
And a large impulse train having a large angular frequency 2Δω. Therefore, by the switching operation that avoids the impulse train by the switching circuit 8, the output D _(t) equivalent to the above can be obtained.

〔The invention's effect〕

As described in detail above, according to the present invention, it is possible to obtain a frequency detection operation that is theoretically distortion-free and does not include unnecessary harmonics. In addition, in order to realize this, there is no need for an analog arithmetic unit or the like, and it can be configured by an existing linear IC mainly including an operational amplifier, a level comparator, an analog switch, etc. Since the circuit scale is small, it is suitable for IC. Further, the application is not limited to the super-heterodyne receiver, and can be directly applied to a quadrature detection waveform receiver.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the circuit of the present invention, and FIG.
FIGS. 3A and 3B are diagrams showing examples of phase difference detection characteristics of the first and second phase difference detection circuits and an example of output characteristics of the level determination circuit according to the present invention, and FIGS. 3A and 3B, respectively. Is a time chart showing each time waveform example when the absolute value of the angular frequency deviation of the input signal is relatively large, and a time chart showing each time waveform example when the absolute value of the angular frequency deviation of the input signal is relatively small. It is a chart. R: input signal, L _I , L _Q: 1st, 2nd local oscillation output, 1
...... Local oscillator circuit, 21,22 …… First and second phase difference detection circuit, θ _I , θ _Q …… Phase difference detection output, 31,32 …… Differentiator, D
_I , D _Q ...... differential output, 41,42 …… First and second level comparator, C
_I , C _Q …… Comparison output, 5 …… Logical inverter, ▲ ▼ …… Logical inverse output, 61,62 …… Polarity switching circuit, D ′ _I , D ′ _Q ……
Polarity switching output, 7 ... Level determination circuit, C ... Level determination output, 71,72 ... First and second cascade connection parts, 8 ... Switching circuit, D ... Switching output, 9 ... Low-pass filtering Instrument, S ... Frequency detection output.

Claims (1)

(57) [Claims] 1. A local oscillator circuit 1 for generating first and second local oscillation outputs L _I , L _Q having the same frequency as the center frequency of an input signal R and having a phase difference of π / 2 radians with each other, and an input. Phase difference detection that repeats linearly rising and falling every π radian with a period of 2π radians for the phase difference between the signal R and the first local oscillation output L _{I and} the phase difference between the input signal R and the second local oscillation output L _Q First and second phase difference detection circuits 21 and 22 having output characteristics,
First and second level comparators 41 and 42 for shaping the outputs θ _I and θ _Q of the first and second phase difference detection circuits 21 and 22 into binary logical values, respectively.
, The logic inverter 5 which logically inverts the output C _Q of the second level comparator 42, and the output of either one of the first and second phase difference detection circuits 21 and 22, and the maximum and average values thereof are inputted. , And a first and second phase difference detection circuit 21, which makes a binary decision as to whether or not the input level is sandwiched between two threshold values located between the middle and the minimum value and the mean value. 22. The first and second cascade connection parts 71 and 72, each of which is connected to 22, and includes a differentiator 31, 32 and a polarity switching circuit 61, 62 for switching and outputting the analog polarity of the input by the polarity switching input, and a level According to the output C of the judgment circuit 7, the first and second cascade connection parts 71, 72
A switching circuit 8 for switching and outputting one of the outputs D' _I and D' _Q of the switching circuit 8 and a low-pass filter 9 for extracting a baseband signal component from the output D of the switching circuit 8;
The output ▲ ▼ of the logic inverter 5 is connected to the polarity switching input of the polarity switching circuit 61 of 71, and the output C of the first level comparator 41 is connected to the polarity switching input of the polarity switching circuit 62 of the second cascade connection portion 72. _I
When the output level of the first phase difference detection circuit 21 is sandwiched between two threshold values in the level determination circuit 7, the output D'of the first cascade connection portion 71 is connected. _I is a first configuration for switching and outputting the output D ′ _Q of the second cascade connection portion 72 when the output level of the second phase difference detection circuit 22 is sandwiched between two threshold values in the level determination circuit 7. A frequency detection circuit configured to obtain the frequency detection output S from the low pass filter 9 in which the influence of the differential discontinuity point of the phase difference detection characteristics of the second phase difference detection circuits 21 and 22 is eliminated.