JPH01162402A - Frequency detecting circuit - Google Patents

Abstract

PURPOSE:To attain frequency detection not to include an unnecessary higher harmonic wave by providing a switching circuit, which switches and outputs any one of the outputs of first and second cascade connecting parts, and an LPF to extract a base band component from the output of the switching circuit. CONSTITUTION:Phase difference detecting outputs theta1 and theta2 of first and second phase difference detecting circuits 21 and 22 are inputted to the first and second cascade connecting parts 71 and 72. When the output of the circuit 21 goes to be between two thresholds in a level deciding circuit 7, a switching circuit 8 outputs a polarity switching output D'1 of the connecting part 71. When the output level of the circuit 22 goes to be between the two thresholds in the circuit 7, a polarity switching output theta'Q is switched and outputted. In an LPF9, the base band component is extracted from the output D'1 or an output D'Q and a frequency detecting output S, in which an influence due to the differential uncontinuous point of the phase difference detecting characteristic of the circuits 21 and 22 is removed, is outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a
This invention relates to a frequency detection circuit used for measuring frequency deviation of an input signal.

[Conventional technology and its problems]

Conventionally, ceramic discriminators, quadrature detection circuits, and the like have been widely used as frequency detection circuits that detect the amount of deviation of the instantaneous frequency of an input signal from a predetermined center frequency.

However, these methods require devices that are not suitable for IC implementation, such as ceramic elements and inductance elements for 90° phase shift, and the carrier waves to be processed are limited to a specific intermediate frequency, so they can only be applied to heterodyne receivers. There were problems with miniaturization and generalization.

For this reason, in recent years, two local oscillation waves that have the same frequency as the received wave or intermediate frequency that are input signals, and whose phases differ by π/2 radians from each other and the input signal are frequency-mixed. The frequency detection output is the difference between the two multiplication outputs obtained by extracting baseband signals that are orthogonal to each other, shifting the phase of one of these two baseband signals by π/2 radians, and then performing analog multiplication with each of the other baseband signals. The so-called orthogonal detection waveform is attracting attention as one of the circuit systems suitable for IC implementation.

This method can be applied even when no intermediate frequency is used, so it has the advantage of being suitable for general use and miniaturization, but it requires two analog multipliers. To realize an analog multiplier, it is possible to use a multiplier with analog operation that utilizes the physical characteristics of semiconductors, or to apply a digital multiplier via an A/D converter or a D/^ converter, but the former depends on the characteristics. There are problems with temperature and aging, and the latter has problems with circuit scale,
These methods have many disadvantages, such as increased power consumption, and both pose major obstacles to practical application.

[Means for solving problems]

The present invention was made in order to eliminate the obstacles in the conventional quadrature detection waveform circuit, and the frequency detection characteristics are theoretically distortion-free and do not contain unnecessary harmonics, and in realizing this, The aim is to provide a circuit that is small in scale and suitable for IC implementation.

That is, as shown in the first diagram, the circuit of the present invention has a first . A local oscillation circuit 1 that generates first local oscillation outputs L+ and Lo, a phase difference between an input signal R and the first local oscillation output 1, and an input signal R and a second local oscillation output. The first . second phase difference detection circuits 21 and 22;
1st. Outputs θ8. of the second phase difference detection circuits 21 and 22. θ
. The first step is to format each into binary logical values. The second level comparators 41 and 42 and the output C0 of the second level comparator 42
a logic inverter 5 which inverts the logic of the first . The output of either one of the second phase difference detection circuits 21 and 22 is input, and the input level is sandwiched between two threshold values located between the maximum value and the average value and between the minimum value and the average value. a level determination circuit 7 for making a binary determination as to whether or not the first . It is connected to the second phase difference detection circuits 21 and 22.

Differentiators 31 and 32, respectively, and a polarity switching circuit 61 that switches and outputs the analog polarity of the input based on the polarity switching input.
, 62. According to the second cascade connection portion 71, 72 and the output C of the level determination circuit 7, the first
．． Output D′1°D J of the second cascade connection portions 71 and 72
, and a low-pass filter 9 that extracts a baseband signal component from the output of the switching circuit 8. The output enable of the logic inverter 5 is connected to the switching input, and the output C4 of the second level comparator 41 is connected to the polarity switching input of the polarity switching circuit 62 of the second cascade connection part '72. As for the switching operation, the first phase difference detection circuit 2
When the output level of 1 is sandwiched between two threshold values in the level determination circuit 7, the output DI of the first cascade connection part 71,
When the output level of the second phase difference detection circuit 22 is sandwiched between the two threshold values in the level determination circuit 7, the output D Jo of the second cascaded portion 72 is switched and output. The configuration is such that a frequency detection output S is obtained from the low-pass filter 9 in which the influence of differential discontinuities in the phase difference detection characteristics of the second phase difference detection circuits 21 and 22 is eliminated.

[For production]

It has the same frequency as the center frequency of the input signal R and is π/
The first one has a phase difference of 2 radians. 1st local oscillation output L+
, Lo are taken out from the local oscillation circuit 1, and the phase difference between the input signal R and the first local oscillation output L+ and the input signal R
and second local oscillation output. linearly increases by π radians for each phase difference.

Phase difference detection output θ1 that repeats falling with a period of 2π radians
, θ. are the first. second phase difference detection circuit 21,
Obtained from 22. These phase difference detection outputs θ1, θ
0 is the first. The output C of the second level comparator 42 is shaped into a binary logical value by the second level comparators 41 and 42.
6 is inverted by the logic inverter 5 and becomes a logic inverted output -.

1st. The output of one of the second phase difference detection circuits 21 and 22 is determined by the level determination circuit 7 so that the input level is between two thresholds located between the maximum value and the average value, and between the minimum value and the average value. A binary judgment is made to determine whether or not it is pinched,
A level determination output C is obtained from the level determination circuit 7.

Also, 1st. Output θ of the second phase difference detection circuits 21 and 22
1, θ. are composed of a combination of differentiators 31, 32 and polarity switching circuits 61, 62, respectively. is input to the second cascade connection portions 71, 72, and this first . The polarity switching circuits 61 and 62 of the second cascade connection portions 71 and 72 include the output of the logic inverter 5 and the second level comparator 41, respectively.
The analog polarity of the input is switched by inputting the output CI of the first . Output Dr of the second cascade connection portions 71 and 72;

Either one of D and I is switched and outputted by the switching circuit 8.

That is, when the output level of the first phase difference detection circuit 21 is sandwiched between two threshold values in the level determination circuit 7, the switching circuit 8 selects the output V of the first cascade connection portion 71.

When the output level of the second phase difference detection circuit 22 is sandwiched between two threshold values in the level determination circuit 7, the output D'Q of the second cascaded portion 72 is switched and output.

The low-pass filter 9 extracts the baseband signal component from this output nl or D' (1 (expressed as output)), and calculates the differential difference of the phase difference detection characteristics of the first and second phase difference detection circuits 21 and 22. A frequency detection output S that eliminates the influence of continuous points is output.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the circuit of the present invention.

In FIG. 1, reference numeral 1 denotes a local oscillation circuit, and a first . Outputs the second local oscillation and generates 1 and Lo. In this example, the second local oscillation output 0 is delayed in phase by π/2 radians with respect to the first local oscillation output.

21 and 22 are the first. The second phase difference detection circuit detects the input signal R and the first local oscillation output L+, and the input signal R and the second local oscillation output L+.
Local oscillation output. are input, and each has a phase difference detection characteristic that shows a linear rise and fall every π radian with a period of 2π radian for the phase difference θ between the two, and the phase difference detection outputs θ1 and θ, respectively. emits. The characteristics of these detection circuits 21 and 22 are as shown in FIG.

The first type having such characteristics. Second phase difference detection circuit 21
．． 22&;, an input signal R and a first local oscillation output L+, an input signal R and a second local oscillation output using a transistor.

A circuit configuration that performs on-off switching operation according to the first. First local oscillation output LI, LQ and input signal R
This can be easily realized by a circuit configuration that low-pass filters the exclusive OR output with θ1, θ. are the first. The relationship between the phase difference detection output of the second phase difference detection circuits 21 and 22 and the actual phase difference θ holds true as shown in FIG. 2 (al).

31 and 32 are phase difference detection outputs θ1. θ. A differentiator inputs and differentiates this, and DI and Do are its differential outputs. 41 and 42 are the first. In the second level comparator, respectively θ1. θ. is input, the magnitude relationship is determined using each average value as a threshold, and a binary logical value (
H, L level). C1°CG is the respective comparison output.

Reference numeral 5 denotes a logic inverter (inverter) which receives the comparison output C6 and outputs a logic inverted output. 61 and 62 input the differential output, logical inversion output, differential output D0, and comparison output C1, respectively, and output the binary state D of q and CI, respectively.
This is a polarity switching circuit that switches and outputs the polarity of DI and D according to the H level and L level. DI, ,
D/, are respective polarity switching outputs.

Such a function has a configuration in which the output of a polarity inverting circuit using an operational amplifier and its input is switched by an analog switch, and the positive reference input of the operational amplifier is opened or grounded by an analog switch to enable inversion or non-inversion. This can be easily realized by a configuration that switches operations.

7 is the first. Phase difference detection outputs θ1 and θ of the second phase difference detection circuits 21 and 22. , in this example θ. Input the value (+Vt) between the maximum input value (+V) and the average value (0), and the minimum input value (-V) and the average value (
This level judgment circuit has a function of making a binary judgment as to whether or not the input level falls between two threshold values (-Vt), which is an intermediate value (-Vt) between 0 and 0). This level determination circuit 7 can be easily constructed using two level comparison circuits whose thresholds are +Vt and -VT, and an OR circuit or an AND circuit. C is the level judgment output.

FIG. 2 (bl shows an example of the output characteristics of the level determination circuit 7.

8 is a switching circuit which inputs the polarity switching output DI, , n'Q and switches and outputs one of [, , Dj, according to the polarity of the level judgment output C, and can be realized by an analog switch. D is its switching output.

9 is a low-pass filter that inputs the switching output, extracts the baseband signal component contained in this output, and removes the noise component mixed in from the transmission line, and S consists of the extracted baseband signal. This is the frequency detection output.

The operation of the embodiment of the present invention in the above configuration will be explained.

FIG. 2 fal and (bl are diagrams showing an example of the phase difference detection characteristics of the first and second phase difference detection circuits 21 and 22 and an example of the output characteristics of the level determination circuit 7 in FIG. 1, respectively, and the vertical axis is The levels of the phase difference detection outputs θ1 and θ. and the binary state of the level determination output C are shown, respectively, and the horizontal axes each show the phase difference θ (radians).

The characteristics shown by the solid line in FIG. It exhibits a periodic characteristic in which one period is a V-shaped polygonal line characteristic that reaches the minimum value -V when in phase (θ = 0) and reaches the maximum value +V when it is out of phase (θ = ±π). ing.

At this time, the second local oscillation is output. is the first local oscillation output L
Since there is a phase delay of π/2 radians with respect to I, the phase difference detection output θ. The characteristic is a characteristic obtained by shifting the characteristic of θ1 by π/2 radian, as shown by the broken line, with respect to the phase difference θ between LI and R.

The characteristics of the level judgment output C in FIG. 2(b) are as follows.
) of θ. The level of is two thresholds +Va and -V.

An example is shown in which the binary states of +1 L II and "H" correspond to the case where the voltage is in the middle of , and the case where the voltage is above +v7 or below -Va, respectively.

In addition, when the human power of the level judgment circuit 7 is set to 01, if this circuit 7 is configured to obtain a binary state output of "H" and "L" in response to the input, which is opposite to the above, the characteristics will be completely unchanged. It is clear from FIG. 2(a) that they are equivalent.

Based on the example characteristics shown in FIG. 2, the principle of the frequency detection operation according to the configuration example shown in FIG. 1 will be specifically explained using mathematical expressions.

Now, each signal θ1, θo, DI, in FIG.
Do.

The time waveforms of D', , D', , D, and θ in Fig. 2 are respectively θI (t) + θo+t+ +
Dzt+ + DO(L) + D'+ +t
++ D'a+v+ +D(t) +θft+
In addition, the binary states of Co and C1 “H” and “L”
Let cO(t)+C11° be the time waveform in which `` is replaced with a rectangular wave of +1 and -1, respectively.At this time, the following relational expressions can be derived from FIGS. 1 and 2.

D'+ (L) -〇r (L) ・Go +t+
−−−−(5) D', +t+ −Do +t+・
CI (tl ・・・・・・・・・・・・(6) Here, (Co+t+) 2-(Czt+) 2= 1, so (1), +3+, (from formula 51, n
l, (t) and D'CLft) are given as follows from equations (2), (4), and +61, respectively.

π dt π　　　　　d.

+7+ , (From formula 81, D'l (tl and D'(
1(t) is theoretically proportional to the angular frequency deviation Δω with respect to the central angular frequency of the dt signal R, so D'+ +t+ + D'c+t+
It can be easily understood that both of these results in the frequency detection output S.

However, in actual circuit operation, the time waveform of the differential output waveform D+(tl + D++t+ and the comparison output Co, the rectangular time waveform of CI, C,.)+CI(
tl is a slight difference in change time due to a difference in circuit operation delay, so thin pulses are generated alternately in time in the output waveforms D'+ +t+ + D'c+t+ of the polarity switching circuits 61 and 62. It is possible. The period of this pulse is C0°.

It is equal to the period of the rectangular changing point of C0°, and occurs once every time the phase difference θ changes by π radians.

The above frequency detection operation and D'+ +t+ + D'
A specific example of the pulse generation phenomenon on czt+ and an example of operation for eliminating its influence by the level determination circuit 7 and the switching circuit 8 will be described below with reference to FIG.

Figure 3 (al, (bl) is when the absolute value of the angular frequency deviation Δω of the input signal R with respect to the central angular frequency is relatively large (Δω-±Δω□) and small (Δω=±ΔωL), respectively. That is, it is a time chart showing an example of each time waveform of (Δω□>ΔωL). In the figure, the waveform indicated by a solid line is Δω−+Δω□.

In the case of +Δω1〉0, the waveform shown by the broken line is Δω
--ΔωH1−Δω1<0, respectively.

In FIG. 3 (al), the change in phase difference θ (phase rotation) is faster than in (bl), so the triangular wave-like change in (θ1(t)·θQ ft) is faster in (al than in (b)). Therefore, these time differential waveforms D+ LL, + Do (L
The amplitude of the rectangular wave in ) is larger in (al) than in (b).

This means that the maximum and minimum values of DI ft+ + Do +t+ are +ga and -vH in case (a), respectively.
1 width), if we set +VL + and -vt,
From equations (1) to (4), the relationship v vH−□Δω□ ・・・・・・・・・・・・・・・・・・
・・・・・・・・・(9) π v VL−□Δω, ・・・・・・・・・・・・・・・・・・
It is clear from the fact that . . . QO) π is obtained.

On the other hand, C, (t, and CI +t+ are not shown, but
θ respectively. (7, and θ1(t) are equal to the binary shaped wave to ± lebel, so -DI(tl and DQ +t
+ waveform, and from the relationship of equations (51 and (61), D'l (t) and D'q+t+ are respectively D++t
+ and Do +t+ have full-wave rectified waveforms. However, when Δω<O (broken line), θ with θI (t) as the reference is different from when Δω>0 (solid line). . , the phase of is π
Since the radians are different, D'+ +t+ , D',
+t+ are both full-wave rectified in the negative direction.

Δω〉0. In either case Δω〈O, the commutation points in full-wave rectification operation are −DI (t) and C0+1+, and. Since the changes in +1+ and CI(t) do not exactly match and there is a slight time difference, a thin reverse polarity pulse is generated as shown.

This pulse is generated at an angular frequency of 2Δω, so if Δω is small, the fundamental wave falls within the baseband signal band of the frequency detection output S and becomes a distortion component that cannot be removed by the low-pass filter 9, which affects transmission quality. give.

Here, if the binary logic waveform of the level judgment output C of the level judgment circuit 7 is set as C+t+, then C(,〉 is +V as explained in Fig. 2,〉θ.(t)>“L” at Vt, θ..)>+
Since V(t++θ..<-yT indicates a movement that becomes "H", the waveform will be as shown in the second row from the bottom of Figure 3 (al, (b). Therefore, in this case, the switching circuit If the operation logic of the switching circuit 8 is configured so that the switching output waveform D (tl) of the switching circuit 8 becomes D'
The alternate switching output that avoids the pulse generation points of I ft) and D'(1+t+ is designated as D (t),
As shown in the bottom row of FIG. 3, D(tl) becomes a frequency detection output signal without distortion within the baseband signal band.

Note that the above level determination circuit 7. Due to the effect of eliminating unnecessary pulses by the switching circuit 8, even in a configuration in which the cascade connection order of the differentiator 31 or 32 and the polarity switching circuit 61 or 62 in FIG. be able to.

That is, θ1 and θ. First, the polarity switching circuit 61, +6
2 are connected first, the equivalent phase difference detection characteristic seen from the inputs of the differentiators 31 and 32 that follow them is a sawtooth characteristic with a period of π radians (Fig. 2 (θ,
The input waveform of the differentiators 31 and 32 has an angular frequency of 2.
Since it is a sawtooth wave of Δω, its differential output, that is, the input to the switching circuit 8, is composed of a waveform level portion proportional to Δω and a large impulse train with an angular frequency of 2Δω.

Therefore, the output D (t) equivalent to the above can be obtained by the switching operation that avoids the impulse train by the switching circuit 8.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to theoretically obtain a frequency detection operation without distortion and without unnecessary harmonics. In addition, to achieve this, there is no need for analog computing units, and it can be constructed using existing linear ICs mainly consisting of operational amplifiers, level comparators, analog switches, etc., logic circuit technologies such as swissotide capacitor circuit technology, and CMO3. Since the circuit scale is small, it is suitable for IC implementation. Furthermore, in terms of applications, it has the advantage of being excellent in versatility, such as being applicable not only to super-hetero gain receivers but also to direct quadrature detection waveform receivers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the circuit of the present invention, and FIG.
Figures (al and Tbl are diagrams showing an example of the phase difference detection characteristics of the first and second phase difference detection circuits and an example of the output characteristics of the level determination circuit, respectively, in the present invention, and Figures 3 (a) and (bl)
are a time chart showing an example of each time waveform when the absolute value of the angular frequency deviation of the input signal is relatively large, and a time chart showing an example of each time waveform when the absolute value of the angular frequency deviation of the input signal is reciprocally small. This is a time chart. R...Input signal, L+, Lo...
...First. Second local oscillation output, ■...Local oscillation circuit, 21, 22...First and second phase difference detection circuits, θ1, θ. ...Phase difference detection output, 31
, 32...Differentiator, Dr, Do...
...Differential output, 41, 42...1st. Second level comparator, C1, co... Comparison output, 5
...Logic inverter, C...Logic inversion output, 61, 62...Polarity switching circuit, D'1゜D
'o...Polarity switching output, 7...Level judgment circuit, C...Level judgment output, 71, 7
2... 1st. Second cascade connection part, 8...
・Switching circuit, D...Switching output, 9...
Low-pass filter, S... Frequency detection output. Idol. (a) □t (@Seki) 9th (b) □4n1111--------------Taku = "'--= -14

Claims (1)

[Claims] It has the same frequency as the center frequency of the input signal R and is π/
First and second local oscillation outputs L_ with a phase difference of 2 radians
A local oscillation circuit 1 that generates I, L_Q, a phase difference between the input signal R and the first local oscillation output L_I, and a phase difference between the input signal R and the second local oscillation output L_I.
First and second phase difference detection circuits 21 and 22 each having a phase difference detection output characteristic that repeats a linear rise and fall every π radian with a cycle of 2π radians with respect to the phase difference of the local oscillation output L_Q; First and second level comparators 41 and 42 that shape the outputs θ_I and θ_Q of the second phase difference detection circuits 21 and 22 into binary logical values, respectively, and a logic that logically inverts the output C_Q of the second level comparator 42 Inverter 5 and the first
, the output of either one of the second phase difference detection circuits 21 and 22 is input, and the input level is sandwiched between two threshold values located between the maximum value and the average value, and between the minimum value and the average value. It is connected to a level judgment circuit 7 that makes a binary judgment as to whether or not the signal is present, and to the first and second phase difference detection circuits 21 and 22. The first and second cascade connection parts 71 and 72 consist of a combination with polarity switching circuits 61 and 62 that
and a switching circuit 8 which switches and outputs either one of the outputs D'_I and D'_Q of the first and second cascade connection parts 71 and 72 according to the output C of the level determination circuit 7, and from the output D of the switching circuit 8. The output @C_Q@ of the logic inverter 5 is connected to the polarity switching input of the polarity switching circuit 61 of the first cascade connection portion 71, and the output @C_Q@ of the logic inverter 5 is connected to the polarity switching input of the polarity switching circuit 61 of the first cascade connection portion 71. The output C_I of the first level comparator 41 is connected to the polarity switching input of the polarity switching circuit 62 of the portion 72,
As for the switching operation of the switching circuit 8, the first phase difference detection circuit 21
When the output level of D'_I is sandwiched between two threshold values in the level determination circuit 7,
When the output level of the second phase difference detection circuit 22 is sandwiched between two threshold values in the level determination circuit 7, the output D'_Q of the second cascade connection part 72 is switched and outputted. A frequency detection circuit configured to obtain a frequency detection output S from a low-pass filter 9 that eliminates the influence of differential discontinuities in the phase difference detection characteristics of the second phase difference detection circuits 21 and 22.