RU2264630C1 - Method for determining phase shift between two sinusoidal signals - Google Patents

Abstract

FIELD: electric engineering.

SUBSTANCE: method can be used to determine phase angle between sinusoidal signals of same frequency in one-phase circuit of alternating current during diagnostics of workability of electronic and electro-mechanical systems and devices. Signals are digitized for same time moments. Sum of current and previous counts of first signal and difference of current and previous counts of second signal are used to determine reactive quasi-power in time range, equal to signals period. Actual values of signals are determined. Phase angle between signals is determined from relation of reactive quasi-power to result of multiplication of actual values of signals.

EFFECT: no need for filtering constant component of signals and shifting signals for 90 degrees angle, also it is possible to achieve average error of phase shift calculation equal to 0,77%.

3 dwg, 2 tbl

Description

The invention relates to the field of information processing systems and measuring equipment and can be used to determine the phase shift between sinusoidal signals of the same frequency in a single-phase AC circuit for diagnosing the health of electrotechnical and electromechanical systems and devices.

In the measuring technique, various methods are known for determining the phase shift between sinusoidal signals of the same frequency.

которые выбирают на интервале полуволны другого сигнала, принятого за опорный, а значение разности фаз определяют по формуле F₀=m(g+πn).A known method for determining the phase shift of two sinusoidal signals [RF Patent No. 2039360, IPC 6 G 01 R 25/00, publ. 1995.07.09], which consists in the fact that the measured instantaneous values are filtered out from the constant component of the signals X (t) and Y (t) having an oscillation period T, two instantaneous values of one of the signals taken as measuring are measured at time instants

which are selected on the half-wave interval of another signal taken as the reference, and the value of the phase difference is determined by the formula F ₀ = m (g + πn).

The disadvantage of this method is the multi-stage and the complexity of its implementation.

в сторону опережения без изменения амплитуды, а разность фаз определяют по формуле

A known method for determining the phase difference of two sinusoidal signals [A.S. No. 1503025, IPC 4 G 01 R 25/00, publ. 1987.04.27], selected as a prototype, which consists in the fact that the instantaneous values of the sinusoidal signals are measured, the sinusoidal signals are filtered from the DC component, each of them is phase-shifted by an angle

in the direction of advancing without changing the amplitude, and the phase difference is determined by the formula

сигналов, измеренных в один момент времени;where U ₁₁ , U ₁₂ - instantaneous values, respectively, of the first and shifted relative to it by an angle

signals measured at one moment in time;

сигналов, измеренных одновременно со значениями U₁₁ и U₁₂.U ₂₁ , U ₂₂ - instantaneous values, respectively, of the second and shifted relative to it by an angle

signals measured simultaneously with the values of U ₁₁ and U ₁₂ .

.The disadvantage of this method is its complexity and the need for additional operations to filter signals from the DC component and to shift the signals in phase by angle

.

The objective of the invention is to develop a simple and accurate method for determining the phase shift in a single-phase alternating current circuit between any two sinusoidal signals represented by digital samples of instantaneous values for the same points in time.

This is achieved by the fact that in the method for determining the phase shift between two sinusoidal signals, including, as in the prototype, measuring the instantaneous values of these signals, according to the invention, two sinusoidal signals a (t _j ), b (t _j ) are digitized, for the same same points in time

t _j = t ₁ , t ₂ , ..., t _N ,

where N is the number of partitions on the period T,

, затем определяют действующие значения А и В сигналов и определяют сдвиг фаз между сигналами a(t_j), b(t_j) по формулеsave each digital readout as the current and previous, then determine the difference and the sum of each pair of the current and previous values, multiply the difference and the sum, then sum the products, then determine the reactive quasi-power

, then determine the effective values of A and B signals and determine the phase shift between signals a (t _j ), b (t _j ) by the formula

After this, vector diagrams are constructed that give a visual representation of the mutual arrangement of various vectors and make it possible to qualitatively control analytical calculations.

The well-known Tallenge theorem on quasi-power between any two sinusoidal signals that do not necessarily exist at the same time in a circuit and are not necessarily connected by one zone of a circuit [P. Penfield et al. Energy theory of electric circuits / P. Penfield, R. Spence, S. Duinker . - M .: Energy, 1974. - 152 p.] It is also known that reactive power can be determined in two ways:

1) according to the well-known formula

2) according to the method of O.A. Maevsky [Mayevsky O.A. Energy performance of valve converters. - M .: Energy, 1978. - 320 p.]

where F _BAX is the area of the current – voltage characteristic for the studied signals, found in this case by the formula for determining the area of the polygon given by the coordinates of the ends of the segments [Bronstein I.N., Semendyaev K.A. Handbook of mathematics for engineers and students of technical colleges. - M .: Nauka, 1980. - 976 p.]

Substituting formula (4) into formula (3) we obtain a formula for calculating reactive quasi-power

, тогда, приравняв правые части формул (2) и (5), можно найти sinφ_ab It was experimentally established that expressions (2) and (5) are quite valid for calculating reactive quasi-power

, then, having equalized the right-hand sides of formulas (2) and (5), we can find sinφ _ab

The described method for determining the phase shift has several advantages, in particular there is no need to filter the signals from the DC component and shift the signals in phase by an angle of 90 °. The relative error in determining the phase shift is on average 0.77%.

Figure 1 shows the hardware diagram of a device that implements the considered method of determining the phase shift.

Figure 2 shows a diagram for which the instantaneous values of the signals a (t _j ) = i ₁ (t _j ), b (t _j ) = i ₂ (t _j ) are measured.

Figure 3 shows a vector diagram for illustratively checking the phase shift between the signals.

Table 1 shows the digital samples of the instantaneous values of the signals a (t _j ) = i ₁ (t _j ), b (t _j ) = i ₂ (t _j ).

Table 2 shows the results of checking the health of the proposed method for determining the phase shift.

The method can be implemented using the device (figure 1). It includes a first fetch-storage device 1 (UVX 1), a second fetch-storage device 2 (UVX 2), a third fetch-storage device 3 (UVX 3), a fourth fetch-storage device 4 (UVX 4), an inverter 5 (Inverter), first adder 6 (Adder 1), second adder 7 (Adder 2), multiplier 8 (Multiplier), integrator 9 (Integrator), multiplier-divider 10 (Multiplier-divider), clock 11 (TG), first rectifier 12 (Rectifier 1), the second rectifier 13 (Rectifier 2), the first low-pass filter 14 (low-pass filter 1), the second low-pass filter stot 15 (low-pass filter 2).

The input buses of the device are connected to the inputs of the retrieval-storage devices: the first 1 (UVX 1) and second 2 (UVX 2), the outputs of which are to the inputs of the third 3 (UVX 3), fourth 4 (UVX 4) of the storage-sampling devices. The first sampling-storage device 1 (UVX 1) is connected to the inputs of the first adder 6 (Adder 1). The second sampling-storage device 2 (UVX 2) is connected to the input of the second adder 7 (Adder 2). The input of the third sampling-storage device 3 (UVX 3) is connected to the input of the inverter 5 (Inverter), the output of which is connected to the input of the first adder 6 (Adder 1). The output of the fourth sampling-storage device 4 (UVX 4) is connected to the input of the second adder 7 (Adder 2). The outputs of the first 6 (Adder 1) and second 7 (Adder 2) of the adders are connected to the inputs of the multiplier 8 (Multiplier), the output of which is connected to the input of the integrator 9 (Integrator). The output of the integrator 9 (Integrator) is connected to the input of the multiplier divider 10 (Multiplier divider). The outputs of the clock generator 11 (TG) are connected to the control inputs of the first 1 (UVX 1), second 2 (UVX 2), third 3 (UVX 3) and fourth 4 (UVX 4) sampling-storage devices. The inputs of the first 12 (Rectifier 1) and second 13 (Rectifier 2) rectifiers are connected to the input buses, and their outputs are connected to the inputs of the first 14 (LPF 1) and second 15 (LPF 2) low-pass filters. The outputs of the first 14 (low-pass filter 1) and second 15 (low-pass filter 2) low-pass filters are connected to the multiplier inputs of the multiplier-divider 10 (multiplier-divider). The output of the multiplier divider 10 (Multiplier divider) is connected to the input of the segment indicator to output the phase shift value.

The first 1 (UVX 1), the second 2 (UVX 2), the third 3 (UVX 3) and the fourth 4 (UVX 4) of the sampling-storage device can be implemented on chips 1100SK2. Inverter 5 (Inverter) can be implemented on a 140UD17A chip. The first 6 (Adder 1) the second 7 (Adder 2), the adders can be implemented on operational amplifiers 140UD17A. As a multiplier 8 (Multiplier) and a multiplier divider 10 (Multiplier divider), a 525PS3 chip can be used. Integrator 9 (Integrator) can be implemented on an operational amplifier 140UD17A. The clock generator 11 (TG) can be implemented on the AT80C2051 microcontroller. Rectifiers 12 (Rectifier 1) and 13 (Rectifier 2), as well as low-pass filters 14 (LPF 1) and 15 (LPF 2) can be performed by operational amplifiers 140UD17A.

For the study, the circuit shown in Fig. 2 was chosen, which has two circuits, the first of them is active-inductive, and the second is active-capacitive.

A signal proportional to the first single-frequency sinusoidal signal, for example, a (t _j ) = i ₁ (t _j ) = 10.9329sin (ωt _j -30 °), is supplied to the input of the first sampling-storage device 1 (UVX 1), and to the input of the second sampling-storage device 2 (UVX 2) a signal proportional to the second single-frequency sinusoidal signal, for example, b (t _j ) = i ₂ (t _j ) = 9.1926sin (ωt _j + 40 °),

Where

t _j = t ₁ , t ₂ , ..., t _N ,

- число разбиений на периоде Т,

- the number of partitions on the period T,

Δt = 1 · 10 ^-4 - discreteness of arrays of signal values,

. В данном случае

(формула 5). С выхода интегратора 9 (Интегратор) значение реактивной квазимощности поступает на вход перемножителя-делителя 10 (Перемножитель-делитель). Параллельно с вышеописанным процессом сигналы i₁(t_j) и i₂(t_j) поступают на входы выпрямителей 12 (Выпрямитель 1) и 13 (Выпрямитель 2) соответственно. С выходов выпрямителей выпрямленные сигналы

и

подаются на входы фильтров низких частот 14 (ФНЧ 1) и 15 (ФНЧ 2). С помощью фильтра низких частот 14 (ФНЧ 1) определяют действующее значение сигнала

. В данном случае I₁=7,7404. С помощью фильтра низких частот 15 (ФНЧ 2) определяют действующее значение сигнала

. В данном случае I₂=6,5136. С выходов фильтров низких частот 14 (ФНЧ 1) и 15 (ФНЧ 2) действующие значения сигналов поступают на входы перемножителя-делителя 10 (Перемножитель-делитель),с помощью которого определяют сдвиг фазы между сигналами

(формула 6). В данном случае

Arrays of signal values are presented in table 1. The values of the signals are recorded in the blocks sampling-storage 1 (UVX 1) and 2 (UVX 2) and stored there as current, then from the output of the device sampling-storage 1 (UVX 1), the signal i ₁ (t _j ) goes to the sampling device- storage 3 (UVX 3) and becomes the previous value, and from the output of the fetch-storage device 2 (UVX 2), the value of the signal i ₂ (t _j ) enters the fetch-storage device 4 (UVX 4) and becomes the previous value. From the output of the sampling-storage device 3 (UVX 3), the previous value of the signal i ₁ (t _j ) enters the inverter 5 (Inverter). Using the inverter 5 (Inverter), the negative value of the previous signal i ₁ (t _j ) is converted to positive. From the output of the inverter 5 (Inverter), the value of the signal i ₁ (t _j ) is fed to the input of the adder 6 (Adder 1). At the same time, from the output of the sampling-storage device 1 (UVX 1), the current value of the signal i ₁ (t _j ) is input to the adder 6 (Adder 1). Using the adder 6 (Adder 1) determine the difference between the current and previous values of the signal i ₁ (t _j ). Simultaneously with the process described above, from the output of the fetch-storage device 4 (UVX 4), the previous value of the signal i ₂ (t _j ) is fed to the input of the adder 7 (Adder 2), and from the output of the fetch-storage device 2 (UVX 2), the current the signal value i ₂ (t _j ) is fed to the input of the adder 7 (Adder 2). Using the adder 7 (Adder 2) determine the sum of the current and previous values of the signal i ₂ (t _j ). From the output of adder 6 (Adder 1), the difference between the current and previous values of the signal i ₁ (t _j ) is input to the multiplier 8 (Multiplier), and from the output of adder 7 (Adder 2) the sum of the current and previous values of the signal i ₂ (t _j ) arrives at the input of the multiplier 8 (Multiplier). Using the multiplier 8 (Multiplier), the values of the difference and the sum of the signals are multiplied and fed to the input of the integrator 9 (Integrator). Using the integrator 9 (Integrator) sum the products of the difference and the sum of the signals and determine the value of reactive quasi-power

. In this case

(formula 5). From the output of the integrator 9 (Integrator), the value of reactive quasi-power is fed to the input of the multiplier-divider 10 (Multiplier-divider). In parallel with the above process, the signals i ₁ (t _j ) and i ₂ (t _j ) are fed to the inputs of rectifiers 12 (Rectifier 1) and 13 (Rectifier 2), respectively. Rectified signals from rectifier outputs

and

fed to the inputs of low-pass filters 14 (low-pass filter 1) and 15 (low-pass filter 2). Using a low-pass filter 14 (low-pass filter 1) determine the effective value of the signal

. In this case, I ₁ = 7.7404. Using a low-pass filter 15 (low-pass filter 2) determine the effective value of the signal

. In this case, I ₂ = 6.5136. From the outputs of the low-pass filters 14 (low-pass filter 1) and 15 (low-pass filter 2), the effective values of the signals are fed to the inputs of the multiplier-divider 10 (multiplier-divider), with which the phase shift between the signals is determined

(formula 6). In this case

, то

If

then

For clarity, the checks used the vector diagram shown in figure 3 and the formula

является близким по значению к реальному сдвигу фаз между тестовыми сигналами

Относительную погрешность ε вычисляли по формуле [Бронштейн И.Н., Семендяев К.А. Справочник по математике для инженеров и учащихся Втузов. - М.: Наука, 1980. - 976 с.]The results of the above calculations are summarized in table 2. The results show that the phase shift between two sinusoidal signals obtained using the proposed method

is close in value to the real phase shift between test signals

The relative error ε was calculated by the formula [Bronstein I.N., Semendyaev K.A. Handbook of mathematics for engineers and students of technical colleges. - M .: Nauka, 1980. - 976 p.]

Where

является приближенным значением числа

is the approximate value of the number

Thus, a simple and accurate method for determining the phase shift in a single-phase alternating current circuit between two sinusoidal signals is obtained.

Table 1 Time t, s a (t _j ) = i ₁ (t _j ), A b (t _j ) = i ₂ (t _j ), A 1 2 3 0 -5.46645 5.908889 0.0001 -5.16635 6,127166 0,0002 -4.86115 6,339397 0,0003 -4.55116 6,545371 0,0004 -4.23667 6.744885 0,0005 -3.918 6.937743 0,0006 -3.59547 7,123755 0,0007 -3,26938 7.302736 0,0008 -2.94007 7.47451 0,0009 -2,60786 7,638908 0.001 -2.27308 7,795767 0.0011 -1.93605 7,944933 0.0012 -1.59711 8,086257 0.0013 -1.2566 8,219602 0.0014 -0.91484 8.344835 0.0015 -0.57218 8.461833 0.0016 -0.22896 8.57048 0.0017 0.114487 8,670669 0.0018 0.457822 8.762301 0.0019 0,800706 8,845285 0.002 1,142799 8,91954 0.0021 1.483765 8,984993 0.0022 1.823266 9.041579 0.0023 2,160968 9,089242 0.0024 2,496537 9,127935 0.0025 2,829643 9.157619 0.0026 3,159956 9,178267 0.0027 3,48715 9,189856 0.0028 3,810903 9.192376 0.0029 4,130896 9,185824 0.003 4.446811 9,170207 0.0031 4,758338 9,14554 0.0032 5,065169 9,111848 0.0033 5,367002 9,069163 0.0034 5.663537 9,017528 0.0035 5,954484 8,956994 0.0036 6,239554 8.887621 0.0037 6,518467 8,809476 0.0038 6,790947 8,722638 0.0039 7.056724 8,627191

Continuation of the table. 1 2 3 0.004 7,315538 8.52323 0.0041 7,567132 8,410858 0.0042 7.811258 8.290186 0.0043 8,047676 8.161332 0.0044 8,276151 8,024423 0.0045 8,496459 7.879596 0.0046 8,708382 7,726993 0.0047 8,911711 7,566763 0.0048 9,106245 7,399067 0.0049 9.291792 7.224068 0.005 9,468169 7.04194 0.0051 9,635203 6.852863 0.0052 9.792727 6.657022 0.0053 9,940587 6,454612 0.0054 10,07864 6,245832 0.0055 10,20674 6,030888 0.0056 10,32477 5,809993 0.0057 10,43261 5.583363 0.0058 10,53016 5.351224 0.0059 10,61731 5,113803 0.006 10,69399 4.871336 0.0061 10.76011 4.624061 0.0062 10,81562 4.372223 0.0063 10,86045 4.11607 0.0064 10.89456 3,855855 0.0065 10,91792 3,591835 0.0066 10.9305 3,32427 0.0067 10.9323 3.053424 0.0068 10.92331 2.779565 0.0069 10.90354 2,502963 0.007 10,87301 2,223891 0.0071 10,83175 1.942624 0.0072 10,7798 1,65944 0.0073 10,71721 1.374619 0.0074 10.64404 1,08844 0.0075 10,56037 0,801188 0.0076 10,46628 0.513145 0.0077 10.36186 0.224595 0.0078 10,24721 -0.06418 0.0079 10.12245 -0.35288 0.008 9.987701 -0.64124 0.0081 9.843095 -0.92897

Continuation of the table. 1 1 2 3 0.0082 9,688775 -1,21578 0.0083 9,524893 -1,50139 0.0084 9.351612 -1.78552 0.0085 9,169101 -2.06789 0.0086 8.977542 -2.34821 0.0087 8,777123 -2.62622 0.0088 8.568042 -2.90164 0.0089 8,350506 -3.17419 0.009 8.124728 -3.44361 0.0091 7,890932 -3,70963 0.0092 7,649349 -3.97199 0.0093 7,400217 -4,23043 0.0094 7,143782 -4.4847 0.0095 6,880297 -4.73334 0.0096 6.610022 -4.97971 0.0097 6.333223 -5.21996 0.0098 6.050174 -5.45506 0.0099 5.761155 -5.68478 0.01 5,46645 -5.90889 0.0101 5,16635 -6.12717 0.0102 4.861152 -6.3394 0.0103 4,551156 -6.54537 0.0104 4.236669 -6.74489 0.0105 3,918001 -6.93774 0,0106 3,595466 -7.12375 0.0107 3,269383 -7.30274 0.0108 2,940073 -7.47451 0,0109 2.607862 -7.63891 0.011 2.273078 -7,79577 0.0111 1.93605 -7.94493 0.0112 1,597111 -8,08626 0.0113 1.256596 -8.2196 0.0114 0.914841 -8.34484 0.0115 0.572184 -8.46183 0.0116 0.228961 -8,57048 0.0117 -0.11449 -8.67067 0.0118 -0.45782 -8.7623 0.0119 -0,80071 -8.84529 0.012 -1.1428 -8.91954 0.0121 -1.48376 -8.98499 0.0122 -1.82327 -9.04158 0.0123 -2,16097 -9,08924 0.0124 -2.49654 -9.12793 0.0125 -2.82964 -9.15762

Continuation of table 1 1 2 3 0.0126 -3.15996 -9.17827 0.0127 -3.48715 -9.18986 0.0128 -3.8109 -9.19238 0.0129 -4,1309 -9.18582 0.013 -4.44681 -9.17021 0.0131 -4.75834 -9.14554 0.0132 -5.06517 -9.11185 0.0133 -5,367 -9,06916 0.0134 -5.66354 -9.01753 0.0135 -5.95448 -8.95699 0.0136 -6,23955 -8.88762 0.0137 -6.51847 -8,80948 0.0138 -6,79095 -8.72264 0.0139 -7.05672 -8.62719 0.014 -7.31554 -8.52323 0.0141 -7.56713 -8,41086 0.0142 -7.81126 -8.29019 0.0143 -8,04768 -8.16133 0.0144 -8.27615 -8,02442 0.0145 -8.49646 -7.8796 0.0146 -8,70838 -7,72699 0.0147 -8.91171 -7.56676 0.0148 -9.10624 -7,39907 0.0149 -9.29179 -7.22407 0.015 9,46817 -7.04194 0.0151 -9.6352 -6.85286 0.0152 -9.79273 -6.65702 0.0153 -9.94059 -6.45461 0.0154 -10.0786 -6,24583 0.0155 -10,2067 -6,03089 0.0156 -10.3248 -5.80999 0.0157 -10.4326 -5.58336 0.0158 -10.5302 -5.35122 0.0159 -10.6173 -5.1138 0.016 -10,694 -4.87134 0.0161 -10.7601 -4.62406 0.0162 -10.8156 -4.37222 0.0163 -10.8604 -4.111607 0.0164 -10.8946 -3.85586 0.0165 -10.9179 -2.59183 0.0166 -10.9305 -3,32427 0.0167 -10.9323 -3.05342 0.0168 -10.9233 -2.77957 0.0169 -10.9035 -2,50296

The end of the table. 1 2 3 0.017 -10,873 -2,22389 0.0171 -10.8317 -1.94262 0.0172 -10.7798 -1.65944 0.0173 -10.7172 -1.37462 0.0174 -10.644 -1.08844 0.0175 -10.5604 -0.80119 0.0176 -10.4663 -0.51314 0.0177 -10.3619 -0.2246 0.0178 -10.2472 0,064176 0.0179 -10.1225 0.352884 0.018 -9.9877 0.641243 0.0181 -9.8431 0.92897 0.0182 -9.68878 1,21578 0.0183 -9.52489 1,50139 0.0184 -9.35161 1.785519 0.0185 -9.1691 2,067885 0.0186 -8.97754 2,348211 0.0187 -8,77712 2,626219 0.0188 -8.56804 2,901635 0.0189 -8,35051 3,174188 0.019 -8,12473 3,443609 0.0191 -7.89093 3,70963 0.0192 -7.64935 3,971991 0.0193 -7,40022 4,230433 0.0194 -7.14378 4,484699 0.0195 -6.8803 4.734539 0.0196 -6.61002 4,979707 0.0197 -6.33322 5.21996 0.0198 -6.05017 5,455062 0.0199 -5.76116 5.684781 0.02 -5.46645 5.908889

Table 2 Signals The product of the actual values of I ₁ I ₂

Quasi-power

Angle, hail,

Check angle, deg Error,% a (t _j ) = i ₁ (t _j ) = 10.9329sin (ωt _j -30 °); 50.4177 47.2126 69,461 70 0.77 b (t _j ) = i ₂ (t _j ) = 9.1926sin (ωt _j + 40 °)

Claims (1)

A method for determining the phase shift between two sinusoidal signals, including measuring the instantaneous values of these signals, characterized in that the two sinusoidal signals a (t _j ), b (t _j ) are digitized for the same points in time t _j = t ₁ , t ₂ , ..., t _N , where N is the number of partitions on the period T, save each digital readout as the current and previous, then determine the difference and the sum of each pair of the current and previous values, multiply the difference and the sum, then sum the products, then determine the reactive quasi-power

then determine the effective values of A and B signals and determine the phase shift between signals a (t _j ), b (t _j ) according to the formula

Further, vector diagrams are constructed that give a visual representation of the mutual arrangement of various vectors and make it possible to qualitatively control analytical calculations.

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