JPH01152845A - Fsk detecting circuit - Google Patents

Abstract

PURPOSE:To reduce remarkably the lower limit of an FSK modulation index to be applicable by using four D flip-flops so as to reduce quantity of jitter. CONSTITUTION:Phase comparators 21, 22 receive R, LI and R, LQ respectively and output binary shaped outputs I, Q having a phase difference of the both and inverted logic outputs I and Q, respectively. D flip-flops 31, 32, 33, 34 receive the said outputs I, Q, inverse of I, inverse of Q as sampling data inputs and output sampling outputs A, B, C, D using sequentially the inverse of Q, I, Q, inverse of I as sampling clock inputs. A synthesis circuit 4 output the sum of four input levels as a synthesized output E. Thus, the quantity of jitter in the detected waveform is compressed to >=1/4, then the lower limit of the FSK modulation index is reduced considerably.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention is applicable to the case where a carrier wave modulated by binary frequency shift keying (FSX) is received and the original binary data sequence is detected. FSX of quadrature detection waveform used
This paper relates to improvements in detection circuits.

(Prior art and its problems) The FSK signal is based on a modulation method that makes two types of frequencies (marks and spaces) correspond to a binary data series, and its detection circuits have conventionally used ceramic discriminators and quadratures. Various frequency discrimination circuits such as detection circuits used for demodulating FM modulated waves of analog baseband signals are widely used.

However, these require devices that are not suitable for IC implementation, such as ceramic elements and phase-shifting inductance elements, so there is a limit to miniaturization, and the frequency of the carrier wave to be processed is 10.7 MHz.

Since it is limited to general-purpose intermediate frequencies such as 455 kHz, its application is limited to heterogain type receivers that convert the received wave to an intermediate frequency; for example, it is directly converted to a baseband signal and processed like a direct conversion type receiver. There was a limit to its general application as it could not be applied to FSX detection.

Against this background, in recent years, two mutually orthogonal local oscillation waves having the same frequency as the received wave or intermediate frequency that is the input signal are used, and by frequency mixing with the input signal, two basebands that are orthogonal to each other are generated. By extracting signal components, binary-shaping them, and sampling one of the binary-shaped signals using one D-type flip-flop, the input signal vector is equivalently converted relative to the center frequency. The so-called orthogonal detection waveform that performs FSK detection by sampling the rotational direction, that is, determining whether the input frequency is large or small with respect to the center frequency, has been attracting attention.

This method has the advantage that the circuit is simple, suitable for IC implementation, and can be applied even when no intermediate frequency is used, contributing to miniaturization. However, on the other hand, the jitter of the FSK detection output is
It has the property of being inversely proportional to the modulation index m (twice the frequency deviation/transmission speed), and generally when the transmission speed is large, the modulation index m needs to be set small due to the limited occupied bandwidth. As a result, the jitter becomes extremely large, making it unsuitable for use.

(Object of the Invention) The object of the present invention is to significantly reduce the lower limit of the applicable FSK modulation index, which was limited in the conventional circuit, and to achieve this, the scale of the added part is small. The object of the present invention is to provide an FSX detection circuit suitable for IC implementation.

(Configuration of the Invention) FIG. 1 shows an example of the configuration of an FSX detection circuit according to the present invention. In the figure, R is an input signal subjected to FSK modulation with a frequency deviation Δf (Hz), which corresponds to a received wave or intermediate frequency that has passed through a predetermined band-limiting filter.

1 is a local oscillator, which has the same frequency as the center frequency of the input signal and has two local oscillation waves orthogonal to each other,
L, is generated. Of these, Lo is 9 for Ll.
It has a phase delay of 0''. 21 and 22 are phase comparators, which input the above-mentioned R and R, respectively, and output the binary shaped outputs I and Q of the phase difference between the two and their logic. Inverted output T (logic inversion of I) and Q (logic inversion of Q)
Output each. The phase comparators 21 and 22 having such functions can be easily realized with a cascaded configuration of a two-signal mixer circuit, a low-pass filter, and a level comparator.
If the inputs R, L+, and Lo are all given as binary logic values, each can be configured with one D-type flip-flop. 31.32.33゜34 is a D-type flip-flop, and the above-mentioned I, Q, r,
Q is the sampling data input (D terminal input), and Q, I, Q, ■ are the sampling clock inputs (CK terminal input) in this order, and the sampling output A
, B, C, and D, respectively.

4 inputs all of the above A, B, C, and D, and performs a level sum calculation operation, or changes A, B, C, and D together in a common polarity direction over time (positive → negative).

This is a synthesis circuit that performs a binary change operation that always follows the latest or last change when changing (from negative to positive), and E is its synthesis output. 5 is a low-pass filter (LPF) having appropriate high-frequency cutoff characteristics for removing harmonics outside the baseband signal band, jitter components, and noise components mixed in from the transmission line included in the composite output E. F is its low-pass filter output, and 6 is a level comparator, which determines the level polarity of F using the DC average value of F when an unmodulated carrier is input to the system as a threshold, and outputs a detected output G. .

Here, an example of the configuration of the synthesis circuit 4 having the above-mentioned functions is shown in FIG.

(I) in FIG. 2 is a case where the simplest level sum calculation operation is used as the function of the synthesis circuit 4, and 41 indicates A, B,
This is an analog adder that outputs the level sum of four inputs C and D as a composite output E, and can be easily configured using an operational amplifier or the like. (II) is A.

When obtaining a binary output that follows the last change among changes in the common polarity direction of B, C, and D, 42 is (I)
Input the level sum from the same analog adder 41 as
The sum of levels when all A, B, C, and D are "H" (high level) and when any three are °H and the other one is "'L" (low level) The intermediate threshold VH1 and the value of the sum of levels when all three are "L" and when any three are "L II" and the other one is "H" This is a level comparator with hysteresis that has two thresholds as the threshold value ■.With the above configuration, the output E of the level comparator with hysteresis 42 is A,
Only when the polarity values of B, C, and D all become "H" does it change to "H", and conversely, all become "L".

It changes to L” only when it becomes, so it is always A, B,
It can be easily understood that the output follows the last change in C and D. (II[) is A, B, C, contrary to (U)
, D, when obtaining a binary output that follows the latest change in the common polarity direction, 43.44 is a level comparator, and the output from the analog adder 41, which is the same as (-■), is obtained. The level sum is input to the positive input and the negative input, respectively, and the threshold values V, , VH explained in the above (n) are input to the other negative input and positive input, respectively. 45 and 46 input the binary outputs of the level comparators 43 and 44, respectively;
This is a pulse generator using a monostable multivibrator that generates a pulse output that is much shorter than the minimum duration of the binary state of the input in synchronization with the rising edge change of the input from negative to positive. 47 is an R3 (set/reset) type flip-flop, which inputs the pulse outputs of pulse generators 45 and 46 to the set input terminal (S) and reset input terminal (R), respectively, and outputs the flip-flop (Q terminal output). is the composite output E.

With the above configuration, the input A of the analog level adder 41
, B, C, and D change from the "L" state to any one of them to the "H" state, the output of the level comparator 43 rises, and the output is output via the pulse generator 45. By applying the pulse output to the set input terminal of the RS flip-flop 47, E of the RS flip-flop 47 is set to the "'H" state.

When the polarity values of C and D all change from the state of "H+1" to the state of "L II", the level comparator 44
The output of 4 rises and the pulse output is given to the reset input terminal of 47 via the pulse generator 46.
E of 7 is reset to the "L" degree state.

By the above operation, the composite output E in this case is always A,
It is clear that the output follows the latest change in polarity among B, C, and D.

Note that the circuit having the same function as (III) is A.

Each of the polarity changes of B, C, and D is made into a one-shot pulse,
The input (A, B) that produced that pulse.

This can also be easily realized by configuring a logic circuit that selectively outputs either C or D) until the next other pulse is generated.

Next, based on the configuration example of the FSK detection circuit of the present invention shown in FIGS. 1 and 2, the detection operation and effects thereof will be explained in detail with reference to FIGS. 3 and 4.

FIG. 3 shows the relative phase movement of the FSK-modulated input signal R with the center frequency of the unmodulated input signal as a reference, and the outputs I of the phase comparators 21 and 22 of FIG.
Q's movement locus and the respective outputs A, B, C, and D type flip-flops 31, 32, 33, and 34 in
(A), (B), (C), and (D) are D-type flip-flops 31, 32, and 33 degrees, respectively.
It corresponds to 4.

The horizontal and vertical axes of each figure take the values of ■ and Q, respectively, with ■ (horizontal axis) pointing toward the right side, and Q (vertical axis) pointing toward the bottom, respectively, toward the positive pole (or ° "H" state). , respectively, with the left side and upper side facing the negative pole (or "L11 state").Therefore, the logic inversion outputs I and Q of I and Q are the opposite of the above.Based on the above coordinate expression method, first, the input signal R The relative phase movement as an FSK signal is expressed by the cosine component (in-phase baseband component of R) and sine component (orthogonal baseband component of R) of I and Q before binary shaping, respectively, on the horizontal and vertical axes. When the mark signal corresponds to the level of , a circular locus is drawn as shown by the broken lines in each figure in Figure 3, and on this locus, in the case of a mark signal with a center frequency of −Δf (Hz), and in the case of a mark signal with a center frequency of +Δf (Hz). In the case of a space signal of
f (Hz). Therefore, the movements of I and Q, which are the binary shaping of the cosine and sine components corresponding to the movement of the relative phase of R, become square trajectories shown by solid lines in each figure, and the binary values of ■ and Q Condition 1. T and Q, 4 by Q
The state points IQ, IQ, TQ, and TQ of the set correspond to the corner points of the square marked with *.

Furthermore, the D type flip-flop 31°32 of FIG.
, 33. Among the phase points of sampling for polarity determination of each output A, B, C, D in 34, positive polarity (or "H" state)
The phase points when the output is determined and when the negative polarity (or “L” state) output is determined are indicated by O marks and × marks, respectively.

- As an example, consider the case of the D type flip-flop 31 of FIG. 1 shown in FIG. 3(A).

As mentioned above, the sampling data and sampling clock of 31 are I and G, respectively, and this rising edge (
In other words, at the falling edge of Q), the polarity of I is extracted and appears as output A, but in Fig. 3 (A), a transition occurs in the direction indicated by the arrow at the phase points marked O and X. The time when this occurs corresponds to this rise (change from L11 to "H11"), and the rotation direction at the O mark and the ) and right turn (that is, corresponding to the mark signal), and the values of ■ at the O mark and the The output A of is "H""H"""L when the input signal R is an FSK space signal (center frequency +Δf) and a mark signal (center frequency -Δf), respectively.
”, it can be seen that FSK detection is performed correctly on a regular basis.

Similarly, for FIGS. 3(B), (C), and (D), the positions of the O marks and X marks are determined based on the input relationship of each D type flip-flop in FIG. , D is qualitatively the same as A, and it is easy to see that the only difference is that the positions of the O mark and the × mark are relatively different by 90''.Furthermore, this Therefore, the configuration in which all the arrows in Fig. 3 (A) to (D) are reversed, that is, instead of Q, I, Q, 1, Q,
1. Even in the case of the configuration in which Q and I are used as sampling clocks, all outputs of A, B, C, and D are only inverted, so it can be seen that it is effective as FSK detection.

If we take a closer look at the roughness of sampling per D-type flip-flop mentioned above, the maximum sampling period of each D-type flip-flop clock is 1/Δf (seconds), and the FSX modulation signal is generally There is no integer ratio relationship between the data transmission rate and its frequency deviation Δf (as asynchronous is allowed, so the sampling timing is , - There is no constant delay relationship, and a sampling delay variation of 0 to 1/Δf seconds occurs, which appears as sampling jitter at the output of each D-type flip-flop.

Therefore, the maximum jitter duty (time ratio) is
This becomes d and o(.

However, m: Modulation index = 2ΔfT T: 1-bit time length of data From equation (1), the FSK detection output by only one D type flip-flop is set to a smaller modulation index m as the data transmission speed becomes faster. Therefore, it can be understood that there is a characteristic that the jitter duty d becomes large.

Next, four D type flip-flops 31, 32.3 in the configuration example of the present invention according to FIGS. 1 and 2 CI)
An example of the operation and effect of combining 3.34 and these outputs A, B, C, and D by the combining circuit 4 will be explained with reference to FIG.

FIG. 4 is a time chart showing some operation examples of the various signals shown in FIG. 1, with time on the horizontal axis and level on the vertical axis, with corresponding signal names on the left side of the diagram and shows an example of its operation. In addition, “HII” attached to the right side of the figure
, ml L'''' indicates the state (polarity) when the corresponding signal is binary.

Also, i-1, t, i+1. i+2 is an algebraic representation of the sequence number of the modulation section (bit section) of FSK modulation, and is indicated in parentheses at the bottom (-Δf
) and (+Δf) represent the polarity mark and space of the frequency shift in the section of the corresponding series, respectively.

Now, sequence numbers i-1, t, i+1. +Δf in the order of i+2
Assume that an FSX signal in which (spaces) and -Δf (marks) alternate is given as an input signal R. At this time, the following characteristics can be mentioned from FIG. First, before and after the division of each modulation section shown by the vertical dashed line in FIG.
The binary shaped outputs Q and I of the phase difference have line symmetry before and after this as a time waveform. That is, the waveform of the section after the modulation section is a waveform that temporally traces the waveform of the previous section in reverse. Furthermore, within each section, Q maintains a relative phase lead and lag of 90° with respect to I in the case of space signals and mark signals, respectively, and the time periods of both Q and I are 1/ Δf. In addition, as mentioned above, the timing of the separation of the modulation section is 1 of Q and I.
There is no synchronization relationship with the periodic movement of /Δf, and it is independent of the timing of these changes.

Assuming the above characteristics, looking at the introduction to the modulation section of sequence number i in FIG.
In the example of FIG. 4, among the outputs A, B, C, and D of ~34, the falling edge of Q (
(rising edge of G) occurs, ■ at this time is sampled by the D type flip-flop 31, and its output A becomes “Ho”.
It will change from “LI” to “LI”.

Thereafter, the rising of ■, the rising of Q, and the falling of ■ (rising of I) occur in order at the timing of ■, ■, ■, and Q, I,
H is a D type flip-flop 32.33.3
4, so these outputs B,,C
, D sequentially change to ° "L" with the same polarity as A. At the time of transition from the 0th interval i to i+1, in the example of Fig. 4, the rising of I, the falling of Q (rising of G), the rising of Falling (rising of I).

In the order of rising of Q, Q, 1. By sampling Q and I, B, A, D, and C become “
Changes to HII. Through the above operations, each output of A, B, C, and D changes within the maximum delay time 1/Δf, but the earliest change occurs within a delay of 1/(4Δf), Less than>/(4Δf
), it can be seen that one of the outputs continues to change.

Therefore, the combined output E of A, B, C, and D when the configuration (I) in FIG. 2 is used as the combining circuit 4 in FIG. As shown, the number of “L” (or “H゛°)” states of A, B, , C, and D is equal to the time 1/(4Δ
f) increases or decreases by one at each time, resulting in a stepwise waveform exhibiting changes in five steps. Note that the thin solid line waveform F superimposed on the above is the output F of the low-pass filter 5 in FIG. 1, and is the waveform smoothed by removing harmonic jitter components contained in E. ing.

The output G of the level comparator 6 in FIG. 1 shown in the bottom row of FIG. It can be seen that the waveform is binarized using a threshold value (level corresponding to the center value of

Note that (II) or (I) in FIG. 2 is used as the synthesis circuit 4.
Although the waveform of the composite output E when using the configuration [I) is not shown, it is given as a binary change waveform that follows the last change or the first change among the changes in E in FIG. 4, respectively. In either case, the variation jitter can be suppressed within 1/(4Δf), so the detection output G in this case is also (
It is clear that this configuration has the same effect as configuration I).

(Effects of the Invention) As explained in detail above, according to the present invention, it is possible to compress each jitter of the detected waveform seen in a conventional quadrature detection waveform FSX detector to 174 or less, thereby greatly increasing the lower limit of the FSX modulation index. This circuit can be reduced to 100% and can support data transmission speeds higher than that of conventional circuits, and can be applied not only to heterodyne receivers but also to direct conversion type receivers, making it a versatile device for applications. Highly sexual.

Further, if a part of the configuration except for the synthesis circuit according to the present invention is installed in duplicate, and the phase of one oscillator and the phase of the other oscillator are configured to have a relative phase difference of 45 degrees, Equivalently, detection can be performed by phase comparison in 8 phases,
This has great effects in terms of advanced applications, such as the ability to obtain a circuit that can compress the amount of jitter to 178 or less.

Furthermore, in realizing the present invention, the conventionally added circuit parts are small in scale and are all suitable for IC implementation, so miniaturization and
It is extremely advantageous for economicization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of the FSK detection circuit according to the present invention, and FIG. 2 (I) (II) (I[I) is a block diagram showing an example of the configuration of the combining circuit used in FIG. , FIG. 3 shows the logical value I used in the present invention. Q's movement trajectory and sampling outputs A, B, and C. A diagram showing the phase points of polarity determination of D, FIG. 4 is FIG. 1. 2 is a time chart showing an example of the operation in the configuration example of the present invention according to FIG. 2(I). 1... Local oscillator, 21.22... Phase comparator, 3
1, 32.33.34...D type flip-flop, 4...Synthesizing circuit, 5...Low pass filter, 6...Level comparator, R...Signal input, L+, Lo . . . Local oscillation waves orthogonal to each other, I, Q . . . Phase comparator 21.
22 binary outputs, I, Q...I, Q logical inversion outputs,
A, B, C, D... D type flip-flop 31゜32, 33.34 sampling output, E... composite output, F... low-pass filter output, G... detection output, 41・
...Analog adder, 42...Level comparator with hysteresis, 43, 44...Level ratio M unit, 45.46.
...Pulse generator, 47...RS type flip-flop. Patent applicant Kokusai Electric Co., Ltd. 5

Claims (1)

[Claims] A local oscillator that generates two local oscillation waves that are orthogonal to each other, an input signal subjected to binary FSK modulation, and one of the two local oscillation waves, and a phase difference between them. Binary shaped outputs (I and Q) and their logic inverted outputs (@I@ and @
Two phase comparators (outputs I, @I@ and Q, @Q@) output (output I, @I@ and Q, @Q@), respectively, and input sampling data of I, Q, @I@, @Q@, respectively. Toshi @Q@, I, Q, @I@ (or Q, @I@
, @Q@, I) are input as sampling clock inputs, and all the sampling data outputs of the four D-type flip-flops are input, and the level sum output or these outputs in the same polar direction are input. a synthesis circuit that obtains a binary change output that follows the latest or last change among the changes; a low-pass filter that inputs the synthesis output of the synthesis circuit; and a low-pass filter that inputs the output of the low-pass filter and and a level comparator that performs level judgment using the DC average value as a threshold and outputs the binarized output to the outside as a detection output, and the low-pass filter is configured to filter the four D-type flip-flops by the synthesis circuit. The high-frequency cutoff characteristic removes harmonic jitter components outside the baseband signal band and noise components mixed in from the transmission line, which are included in the composite output that suppresses the change jitter of the four outputs obtained from the filter to 1/4 or less. An FSK detection circuit characterized by being provided with.