JP2009055097A - Fsk demodulation circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily demodulate a multi-valued FSK (Frequency Shift Keying) signal and a broadband FSK signal with a configuration simpler as compared with the conventional technology. <P>SOLUTION: A digital controlled oscillator having a plurality of oscillation frequencies which respectively coincide with respective instantaneous frequencies of FSK signals is controlled so as to sequentially repeat and intermittently oscillate oscillation frequencies of the respective oscillation frequencies by using a plurality of control signals respectively corresponding to the respective oscillation frequencies. The FSK signals are inputted to the digital controlled oscillator to thereby operate the digital controlled oscillator as a super-regenerative AM wave detector 10. An AM demodulation signal outputted from the digital controlled oscillator is used as a data sampling control signal to perform sample hold of the plurality of control signals and perform binary digit conversion of the control signals, thereby obtaining an FSK demodulation signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an FSK demodulating circuit and method for demodulating an FSK (Frequency Shift Keying) signal.

  An FSK signal receiving circuit that has already been put into practical use is configured to include a low noise amplifier (LNA), an FV conversion circuit, and an A / D conversion circuit. As another approach, there is a slope detection method of an FSK signal using the steep frequency selectivity of a super regenerative detection circuit (for example, see Non-Patent Document 1-3) that is a demodulation circuit of an AM signal. Is limited to narrowband FSK signals.

JP-A-9-214386 (FIGS. 19 and 20). N. Buchanan et al., "A 7.5-GHz superregenerative detector", IEEE Transactions on Microwave Theory and Technology, Vol. 50, No. 9, pp. 2198-2202, September 2002. C. Dehollainm et al., "A global survey on short range low power wireless data transmission architecture for ISM application", Proceedings of International Semiconductor Conference, Vol. 1, pp. 117-126, October 2001. E. Armstrong, "Some recent developments of regenerative circuits", Proceedings of IRE, Vol. 10, pp. 244-260, August 1922. B. Giebel et al., "Digitally Controlled Oscillator", IEEE Journal of Solid-State Circuits, Vol.24, No.6, pp. 640-645, June 1989. R. Staszewski et al., "Just-In-Time Gain Estimation of an RF Digitally Controlled Oscillator for Digital Direct Frequency Modulation", IEEE Transactions on Circuits and Systems, Vol.50, No.11, pp. 887-892, November 2003. R. Staszewsky et al., "A Digitally Controlled Oscillator in a 90nm Digital CMOS Process for Mobile Phones", IEEE Journal of Solid-State Circuits, Vol.40, No.11, pp. 2203-2211, November 2005.

  As described above, the FSK signal receiving circuit according to the related art is configured to include the low noise amplifier (LNA), the F-V conversion circuit, and the A / D conversion circuit, so that the configuration becomes complicated. There are problems in that the manufacturing cost is increased and that a multilevel FSK signal and a wideband FSK signal cannot be easily demodulated.

  19 and 20 of Patent Document 1 disclose an ASK signal demodulating circuit (the operation of which is shown in FIG. 8) that demodulates the ASK signal by a super regenerative detection circuit using a quenching signal. However, there is a problem that the FSK signal cannot be demodulated.

  The object of the present invention is to provide an FSK demodulating circuit and method that solve the above-described problems, have a simpler configuration than the prior art, and can easily demodulate a multilevel FSK signal or a wideband FSK signal. There is.

  There have already been reported examples of a digitally controlled oscillator (DCO (Digitally Controlled Oscillator); hereinafter referred to as DCO) that performs discrete switching of the oscillation frequency of the oscillation circuit using an electronic switch such as an FET (see, for example, Non-Patent Documents 4-6). It is already known that an oscillation circuit capable of switching the frequency by a binary signal can be realized. The inventors pay attention to this and are characterized in that an FSK demodulating circuit is configured by combining a DCO and a super regenerative detection circuit.

According to a first aspect of the present invention, there is provided an FSK demodulating circuit using a digitally controlled oscillator having a plurality of oscillation frequencies respectively corresponding to the respective instantaneous frequencies of the FSK signal as a plurality of control signals respectively corresponding to the respective oscillation frequencies. Control the oscillation frequency of the frequency to repeat repeatedly and intermittently,
By inputting the FSK signal to the digitally controlled oscillator, the digitally controlled oscillator is operated as a super regenerative AM detector,
The FSK demodulated signal is obtained by sampling and holding the plurality of control signals using the AM demodulated signal output from the digitally controlled oscillator as a data sampling control signal and performing binary conversion.

The FSK demodulating method according to the second invention uses a digitally controlled oscillator having a plurality of oscillation frequencies corresponding to the respective instantaneous frequencies of the FSK signal as a plurality of control signals respectively corresponding to the oscillation frequencies. Control the oscillation frequency of the frequency to repeat repeatedly and intermittently,
By inputting the FSK signal to the digitally controlled oscillator, the digitally controlled oscillator is operated as a super regenerative AM detector,
The FSK demodulated signal is obtained by sampling and holding the plurality of control signals using the AM demodulated signal output from the digitally controlled oscillator as a data sampling control signal and performing binary conversion.

  Therefore, according to the FSK demodulating circuit and method according to the present invention, the circuit scale can be reduced as compared with the conventional approach, and the power consumption can be reduced. Furthermore, even when the operating frequency is high and the yield of active elements is low, the number of necessary active elements that operate at the target frequency (carrier frequency) can be reduced. Further, an A / D converter that is indispensable in the conventional FSK demodulating circuit is unnecessary, and an FSK demodulating circuit with low power consumption can be formed with a simple configuration. The basic demodulation capability is based on the sensitivity characteristics of super reproduction, and the addition of a low noise amplifier (LNA) may not be necessary.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing a configuration of a 2FSK signal receiving circuit according to the first embodiment of the present invention. The 2FSK signal receiving circuit of FIG. 1 includes a dual frequency scanning super regenerative AM detection circuit 10 using a DCO, a DCO control signal generator 20, a comparator 12, a sample hold circuit 30, and a binary decoder 40. Composed.

  In FIG. 1, the DCO control signal generator 20 converts the DCO control signals V1 and V2 into (V1, V2) = (1, 0) and (0, 1) (where 1 is high level, 0 Are switched at a predetermined period T1 (T1 is sufficiently shorter than the switching period of the 2FSK signal) so as to change alternately, and each field effect transistor for switching (hereinafter referred to as field effect) is generated. The transistor is referred to as FET.) It is applied to the gates of Q1 and Q2, and is output to the sample and hold circuit 30.

In the super regenerative AM detection circuit 10, the gate of the oscillation FET Q11 is connected to the drains of the frequency switching FETs Q1 and Q2 via the transmission line L10, the source of the FET Q1 is grounded via the transmission line L1, and the source of the FET Q2 is Grounded via the transmission line L2 (<L1). The drain of the oscillation FET Q11 is grounded via the transmission line L12, and the source thereof is grounded via the output load transmission line L11. The source of the oscillation FET Q11 is connected to the low-pass filter (LPF) 11 via the terminal T3. Further, the drain of the oscillation FET Q11 is connected to the power supply voltage V _DD via the source and drain of the quenching intermittent oscillation switching FET Q5, and the switching FET Q5 is frequency-switched of the 2FSK signal input via the terminal T4. On / off control is performed by a sine wave (or rectangular pulse) quenching signal having a quenching frequency sufficiently higher than the frequency. A 2FSK signal having an instantaneous frequency or channel frequencies f1 and f2 is applied to the drain of the oscillation FET Q11 via the terminal T1 and the coupling capacitor C1.

In the circuit including the oscillation FET Q11 configured as described above, when the DCO control signal (V1, V2) = (1, 0) is applied, the switching FET Q1 is turned on while the switching FET Q2 is turned off. It becomes. At this time, a signal from the drain of the oscillation FET Q11 is fed back to the oscillation FET Q11 via the transmission line L12, the transmission line L1, the switching FET Q1, and the transmission line L10 to form a positive feedback circuit, and depends on the transmission line L1. Oscillation is performed at a frequency determined by a positive feedback circuit having an electrical length determined as described above. Here, the frequency is set to f1. In the circuit including the oscillation FET Q11, when the DCO control signal (V1, V2) = (0, 1) is applied, the switching FET Q1 is turned off while the switching FET Q2 is turned on. At this time, the signal from the drain of the oscillation FET Q11 is fed back to the oscillation FET Q11 via the transmission line L12, the transmission line L2, the switching FET Q2, and the transmission line L10 to form a positive feedback circuit, and depends on the transmission line L2. Oscillation is performed at a frequency determined by a positive feedback circuit having an electrical length determined in this manner. Here, the frequency is set to f2. The DCO control signal generator 20 outputs control signals V1 and V2 so that the oscillator sequentially oscillates in the order of the oscillation frequencies f1 and f2. Furthermore, since the switching FET Q5 is repeatedly turned on and off according to the quenching signal, the supply of the power supply voltage V _DD is turned on and off, so that the oscillator oscillates intermittently and the oscillator operates as a super regenerative detection circuit It will be.

  The 2FSK signal is applied to the oscillation FET Q11 via the terminal T1 and the coupling capacitor C1, and at this time, the oscillator oscillates by alternately scanning at the oscillation frequencies f1 and f2 based on the control signals V1 and V2. Only when the instantaneous frequency f1 or f2 of the 2FSK signal matches the oscillation frequency f1 or f2 of the oscillator, the AM demodulated signal is output from the source of the oscillation FET Q11, and the AM demodulated signal passes through the low-pass filter (LPF) 11. Through the non-inverting input terminal of the comparator 12. A threshold voltage Vth is applied to the inverting input terminal of the comparator 12, and the comparator 12 generates a high level data sampling control signal only when the input AM demodulated signal is equal to or higher than the threshold voltage Vth, and performs sample hold. Output to the circuit 30. The sample hold circuit 30 samples and holds the DCO control signals V1 and V2 output from the DCO control signal generator 20 when the data sampling control signal is at a high level, and then outputs the DCO control signals V1 and V2 to the binary decoder 40. In response to this, the binary decoder 40 performs binary conversion on the input signal and performs binary decoding to generate a 1-bit 2FSK demodulated signal and output it via the terminal T2.

  FIG. 2 is a circuit diagram showing detailed configurations of the low-pass filter (LPF) 11, the comparator 12, the sample hold circuit 30, and the binary decoder 40 of FIG. 1. In FIG. 2, the low-pass filter (LPF) 11 is composed of two operational amplifiers OP1 and OP2, the comparator 12 is composed of one comparator ICCP1, and the sample and hold circuit 30 is composed of two sample and hold ICSH1 and SH2. Composed. The binary decoder 40 includes an inverter I1 and an AND gate A1.

  FIG. 3 is a timing chart of each signal for illustrating the operation of the 2FSK signal receiving circuit of FIG. As is apparent from FIG. 3, the oscillator oscillates by alternately scanning at the oscillation frequencies f1 and f2, but only when the instantaneous frequency f1 or f2 of the 2FSK signal matches the oscillation frequency f1 or f2 of the oscillator. It can be seen that an AM demodulated signal is output from the source of the FET Q11, and the control signals V1 and V2 sampled and held by the sample and hold circuit 30 based on the AM demodulated signal are demodulated signals of the input FSK signal. That is, when the input FSK signal exists, the rise of the oscillation of the oscillator is accelerated, and as a result, PWM is applied. By taking out the envelope of this oscillation waveform and passing it through the low-pass filter 11, the AM component can be demodulated. In this embodiment, the circuit design is performed so that the oscillation frequency of the DCO matches the channel frequency of the FSK signal, and the oscillation frequency is switched by scanning sequentially. Further, the oscillation circuit is operated intermittently to operate as a super regenerative detection circuit, and the DCO control signal is sampled and held based on the AM demodulated signal obtained when the instantaneous frequency of the FSK signal matches the reception frequency of the super regenerative detection circuit. As a result, the control signal at this time becomes an FSK demodulated signal.

  As described above, according to the present embodiment, the digitally controlled oscillator having a plurality of oscillation frequencies respectively corresponding to the respective instantaneous frequencies of the FSK signal is used for the plurality of control signals respectively corresponding to the respective oscillation frequencies. The oscillation frequency of each oscillation frequency is controlled so as to sequentially repeat and intermittently oscillate, and the FSK signal is input to the digitally controlled oscillator to operate the digitally controlled oscillator as a super regenerative AM detector. Using the output AM demodulated signal as a data sampling control signal, the plurality of control signals are sampled and held, and binary conversion is performed to obtain an FSK demodulated signal. Thereby, the circuit scale can be reduced as compared with the conventional approach, and the power consumption can be reduced. Furthermore, even when the operating frequency is high and the yield of active elements is low, the number of FSK signal channels can be reduced to the number of necessary active elements operating at the target frequency (carrier frequency). Further, an A / D converter that is indispensable in the conventional FSK demodulating circuit is unnecessary, and an FSK demodulating circuit with low power consumption can be formed with a simple configuration. The basic demodulation capability is based on the sensitivity characteristics of super reproduction, and the addition of a low noise amplifier (LNA) may not be necessary.

Second embodiment.
FIG. 4 is a block diagram showing a configuration of a 4FSK signal receiving circuit according to the second embodiment of the present invention. The second embodiment is different from the first embodiment of FIG. 1 in that the 4FSK signal input via the terminal T1 is demodulated as follows.
(1) A 4-frequency scanning super regenerative AM detection circuit 10A using a DCO that oscillates intermittently at four oscillation frequencies is provided in place of the 2-frequency scanning super regenerative AM detection circuit 10 using a DCO.
(2) A DCO control signal generator 20A for generating four control signals V1-V4 is provided instead of the DCO control signal generator 20 for generating two control signals V1, V2.
(3) A sample and hold circuit 30A for sampling and holding the four control signals V1 to V4 is provided.
(4) In place of the binary decoder 40, the binary decoder 40A is provided which obtains a 2-bit 4FSK demodulated signal by binary-decoding the four sampled and held control signals V1-V4 by binary conversion.
Hereinafter, the difference will be described in detail.

  4 further includes switching FETs Q3 and Q4 and transmission lines L3 and L4 connected between their respective sources and the ground as compared with the circuit of FIG. The control signals V1-V4 from the DCO control signal generator 20A are applied to the gates of the switching FETs Q1-Q4, respectively. The drains of the switching FETs Q3 and Q4 are connected to the gate of the oscillation FET Q11 via the transmission line L10.

  When the DCO control signal generator 20A outputs the high level control signal V1 and the other low level control signals V2-V4, only the switching FET Q1 of the switching FETs Q1-Q4 is turned on, and the oscillation FET Q11 Is configured to oscillate at a predetermined oscillation frequency f1. Further, when the DCO control signal generator 20A outputs the high level control signal V2 and the other low level control signals V1, V3-V4, only the switching FET Q2 of the switching FETs Q1-Q4 is turned on. The oscillator including the oscillation FET Q11 is configured to oscillate at a predetermined oscillation frequency f2. Further, when the DCO control signal generator 20A outputs the high level control signal V3 and the other low level control signals V1, V2, and V4, only the switching FET Q3 of the switching FETs Q1-Q4 is turned on. The oscillator including the oscillation FET Q11 is configured to oscillate at a predetermined oscillation frequency f3. Furthermore, when the DCO control signal generator 20A outputs the high level control signal V4 and the other low level control signals V1-V3, only the switching FET Q4 among the switching FETs Q1-Q4 is turned on. The oscillator including the oscillation FET Q11 is configured to oscillate at a predetermined oscillation frequency f4. Here, the oscillation frequencies f1 to f4 are different from each other and correspond to the four instantaneous frequencies of the input 4FSK signal. Here, the DCO control signal generator 20A outputs the control signals V1-V4 so that the oscillator sequentially oscillates in the order of the oscillation frequencies f1, f2, f3, f4.

  When the data sampling control signal is at a high level, the sample hold circuit 30A samples and holds the DCO control signals V1 and V2 output from the DCO control signal generator 20A, and then outputs them to the binary decoder 40A. In response to this, the binary decoder 40A generates a 2-bit 4FSK demodulated signal by subjecting the input signal to binary conversion and binary decoding, and outputs it through terminals T11 and T12.

  FIG. 5 is a circuit diagram showing a detailed configuration of the low-pass filter (LPF) 11, the comparator 12, the sample hold circuit 30A, and the binary decoder 40A of FIG. In FIG. 5, the low-pass filter (LPF) 11 is composed of two operational amplifiers OP1 and OP2, the comparator 12 is composed of one comparator ICCP1, and the sample and hold circuit 30A is composed of four sample and hold ICSH1 to SH4. Composed. The binary decoder 40A includes a NAND gate N1 and an AND gate A1.

  FIG. 6 is a timing chart of each signal for illustrating the operation of the FSK signal receiving circuit of FIG. As is apparent from FIG. 6, the oscillator sequentially oscillates at the oscillation frequency f1-f4, but only the instantaneous frequency f1-f4 of the 4FSK signal coincides with the frequency f1-f4 of the oscillator. It can be seen that an AM demodulated signal is output from the source, and the control signals V1-V4 sampled and held by the sample hold circuit 30A based on the AM demodulated signal are demodulated signals of the input FSK signal. That is, when the input FSK signal exists, the rise of the oscillation of the oscillator is accelerated, and as a result, PWM is applied. By taking out the envelope of this oscillation waveform and passing it through the low-pass filter 11, the AM component can be demodulated. In this embodiment, the circuit design is performed so that the oscillation frequency of the DCO matches the channel frequency of the FSK signal, and the oscillation frequency is switched by scanning sequentially. Further, the oscillation circuit is operated intermittently to operate as a super regenerative detection circuit, and the DCO control signal is sampled and held based on the AM demodulated signal obtained when the instantaneous frequency of the FSK signal matches the reception frequency of the super regenerative detection circuit. As a result, the control signal at this time becomes an FSK demodulated signal.

  Therefore, according to the present embodiment, the same effects as those of the first embodiment can be obtained, and in particular, a 4FSK signal can be demodulated.

Modified example.
In the above embodiment, the demodulation circuit for the 2FSK signal and the 4FSK signal has been described. However, the present invention is not limited to this, and the number of DCO oscillation frequencies and the corresponding DCO control signal are increased to increase the 3FSK signal or 5 values or more. The FSK signal demodulating circuit may be configured. Since the instantaneous frequency (or channel frequency) of the FSK signal is determined by the oscillation frequency of the DCO, a desired FSK signal demodulation circuit can be easily configured by setting the oscillation frequency of the DCO.

  The inventors prototyped a 2FSK signal receiving circuit. The experimental results of this prototype circuit are shown below. FIG. 7 is a diagram illustrating an example of the 2FSK signal receiving circuit of FIG. 1 and showing the oscillation spectrum of the DCO during the super reproduction operation. The inventors made a prototype by designing on ADS (Advanced Design System) using the device parameters of NE3210S01. As is apparent from FIG. 7, when a 2FSK signal corresponding to the peak of the oscillation spectrum was input to this circuit, it was confirmed that the FSK signal could actually be demodulated.

  As described above in detail, according to the FSK demodulating circuit and method according to the present invention, the circuit scale can be reduced as compared with the conventional approach, and the power consumption can be reduced. Furthermore, even when the operating frequency is high and the yield of active elements is low, the number of necessary active elements that operate at the target frequency (carrier frequency) can be reduced. Further, an A / D converter that is indispensable in the conventional FSK demodulating circuit is unnecessary, and an FSK demodulating circuit with low power consumption can be formed with a simple configuration. The basic demodulation capability is based on the sensitivity characteristics of super reproduction, and the addition of a low noise amplifier (LNA) may not be necessary.

  Therefore, since a low-cost FSK signal receiving circuit can be configured, it can be used for applications requiring disposable such as RF tags. Furthermore, it can be used as a practical method for constructing an FSK signal receiving circuit in the THz region where a satisfactory yield cannot be obtained.

It is a block diagram which shows the structure of the 2FSK signal receiving circuit which concerns on the 1st Embodiment of this invention. 2 is a circuit diagram showing a detailed configuration of a low-pass filter (LPF) 11, a comparator 12, a sample hold circuit 30 and a binary decoder 40 in FIG. 3 is a timing chart of each signal for illustrating the operation of the FSK signal receiving circuit of FIG. 1. It is a block diagram which shows the structure of the 4FSK signal receiving circuit which concerns on the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram illustrating detailed configurations of a low-pass filter (LPF) 11, a comparator 12, a sample hold circuit 30A, and a binary decoder 40A in FIG. 5 is a timing chart of each signal for illustrating the operation of the FSK signal receiving circuit of FIG. 4. FIG. 2 is a diagram illustrating an oscillation spectrum of a DCO during super reproduction operation, which is an example of the FSK signal receiving circuit of FIG. 1. It is a timing chart of each signal for showing operation of an ASK signal demodulating circuit of a conventional example which demodulates an ASK signal by a super reproduction detection circuit using a quenching signal.

Explanation of symbols

10: Dual frequency scanning super regenerative AM detection circuit using DCO,
10A ... 4 frequency scanning super regenerative AM detection circuit using DCO,
11 ... Low-pass filter (LPF),
12 ... Comparator,
13 ... Voltage source,
20, 20A ... DCO control signal generator,
30, 30A ... Sample and hold circuit,
40, 30A Binary decoder,
C1 ... coupling capacitor,
L1 to L12 ... transmission line,
Q1 to Q5 ... switching field effect transistors (FETs),
Q11: Oscillating field effect transistor (FET).

Claims (2)

A digitally controlled oscillator having a plurality of oscillation frequencies respectively corresponding to the respective instantaneous frequencies of the FSK signal is used as a plurality of control signals respectively corresponding to the respective oscillation frequencies, and the oscillation frequencies of the respective oscillation frequencies are sequentially repeated and intermittently oscillated. Control and
By inputting the FSK signal to the digitally controlled oscillator, the digitally controlled oscillator is operated as a super regenerative AM detector,
An FSK demodulating circuit characterized in that an AM demodulated signal output from the digitally controlled oscillator is used as a data sampling control signal to sample and hold the plurality of control signals and to perform binary conversion to obtain an FSK demodulated signal. A digitally controlled oscillator having a plurality of oscillation frequencies respectively corresponding to the respective instantaneous frequencies of the FSK signal is used as a plurality of control signals respectively corresponding to the respective oscillation frequencies, and the oscillation frequencies of the respective oscillation frequencies are sequentially repeated and intermittently oscillated. To control and
By inputting the FSK signal to the digitally controlled oscillator, the digitally controlled oscillator is operated as a super regenerative AM detector,
An FSK demodulating method characterized in that an AM demodulated signal output from the digitally controlled oscillator is used as a data sampling control signal to sample and hold the plurality of control signals and perform binary conversion to obtain an FSK demodulated signal.

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