JP4230688B2 - Frequency demodulation circuit by digital signal processing - Google Patents

Frequency demodulation circuit by digital signal processing Download PDF

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JP4230688B2
JP4230688B2 JP2001303597A JP2001303597A JP4230688B2 JP 4230688 B2 JP4230688 B2 JP 4230688B2 JP 2001303597 A JP2001303597 A JP 2001303597A JP 2001303597 A JP2001303597 A JP 2001303597A JP 4230688 B2 JP4230688 B2 JP 4230688B2
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signal
circuit
multiplier
output
frequency
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JP2003110365A (en
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洋雄 阿良田
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Japan Broadcasting Corp
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Japan Broadcasting Corp
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Description

【０００１】
本発明は周波数変調波を復調する周波数復調回路、特にデジタル信号処理を用いた周波数復調回路に関するものである。
【産業上の利用分野】
【０００２】
本発明のデジタル信号処理を用いた周波数復調回路は、広く放送・通信の分野に応用することが可能である。
【０００３】
【従来の技術】
従来，デジタル信号処理を用いた周波数復調の手法としては，例えば，クロスプロダクト型の周波数復調回路が知られており、デジタル通信のA F C回路等で広く使われている。以下、従来の技術を詳細に説明する。
【０００４】
連続信号クロスプロダクト型周波数復調の原理
まず従来のクロスプロダクト型FM復調器の数式を導出する。一般的な変調信号g(t)は搬送波ωcを用いて次式（１）で表現することができる。ここに，ωc＝2πfcとし、また，I(t)，Q(t)を変調信号g(t)の同相成分および直交成分とする。
【数１】

Figure 0004230688
式（1）を変形して，式（２）を得る。
【数２】
Figure 0004230688
ここで瞬時位相θは式（2）の余弦関数の位相であり，これを次式（3）で定義する。
【数３】
Figure 0004230688
瞬時周波数fmは位相θ(t)を微分することにより次式で表わすことができる。
【数４】
Figure 0004230688
従って，式（４）を計算して次式（５）を得る。
【数５】
Figure 0004230688
逆正接関数の微分と分数の微分の公式を用いて式（５）を計算すると次式（６）が得られる。
【数６】
Figure 0004230688
式（６）によって同相成分と直交成分から復調瞬時周波数が得られる。すなわち，まず式（６）の第2項を計算しfcを加算すれば、瞬時周波数fmを得ることができる。ここにI’(t), Q’(t)は同相成分と直交成分の時間微分とする。
【０００５】
離散化クロスプロダクト型 FM 復調
つぎに，デジタル信号処理により計算を行なうために，同相成分と直交成分を離散化する。離散化した信号をそれぞれIn, In-1, Qn, Qn-1とする。微分は差分により近似すると、同相成分Inおよび直交成分Qnの微分In′およびQn′は次式（７）および（８）に示すようになる。
【数７】
Figure 0004230688
したがって同相成分と直交成分から求められる瞬時周波数fnは、次式（９）に示すようになる。
【数８】
Figure 0004230688
1タップの遅延時間をδtとする。δt は次式（10）に示すように、クロック周波数fclkの逆数である。
【数９】
Figure 0004230688
この式（10）を式（9）に代入して得た式（11）が，離散化クロスプロダクト型の周波数復調器の瞬時周波数となる。
【数１０】
Figure 0004230688
【０００６】
以上は、公知の事実であり、本発明はこの離散化クロスプロダクト型周波数復調器の欠点を改善しようとするものである。
【０００７】
【発明が解決しようとする課題】
前記離散化クロスプロダクト型周波数復調器では，離散的な数値を扱うため誤差が生じる。以下、かかる誤差を定量的に導出する。
離散化クロスプロダクト型周波数復調の欠点
誤差を求めるために、離散化クロスプロダクト型周波数復調法による式（11）に次式（12）で示される信号を入力した場合の出力を計算する。この信号の周波数はf0であるから，周波数復調した信号も本来はf0にならなければならない。
【数１１】
Figure 0004230688
入力信号がf0の単一正弦波を入力した場合のfcで同期検波した同相成分と直交成分は次式で示すようになる。
【数１２】
Figure 0004230688
式（11）に、式（13）〜式（16）を代入して整理すると次式（17）が得られる。
【数１３】
Figure 0004230688
式（17）が離散化クロスプロダクト型で復調した単一正弦波の周波数復調周波数を表す。この際、復調した単一正弦波の復調周波数は、定義からf0でなければならないが、式（17）で、f0ではなくSin関数の中にあり、従って誤差を含んでいる。
【０００８】
本発明の目的は原理的に誤差の無い周波数復調を得るようにせんとするものである。
【０００９】
【課題を解決するための手段】
本発明デジタル信号処理による周波数復調回路は変調信号の同相成分Ｉ ｎ 及び直交成分Ｑ ｎ の信号をそれぞれ入力する２つの入力端子にそれぞれ接続され、各同相成分Ｉ ｎ 及び直交成分Ｑ ｎ の信号をクロック周波数ｆ ｃｌｋ の逆数の遅延時間だけ遅延させて、それぞれ遅延させた同相成分Ｉ ｎ−１ 及び直交成分Ｑ ｎ−１ の信号を生成する２つの遅延回路と、前記２つの遅延回路の各々に接続される２つの乗算回路であって、遅延させた同相成分Ｉ ｎ−１ の信号と遅延させる前の直交成分Ｑ ｎ の信号とを乗算する第１乗算回路、及び遅延させた直交成分Ｑ ｎ−１ の信号と遅延させる前の同相成分Ｉ ｎ の信号とを乗算する第２乗算回路とからなる２つの乗算回路と、該２つの乗算回路の各出力信号を減算する減算器と、前記２つの入力端子にそれぞれ接続され、遅延させる前の同相成分Ｉ ｎ 及び直交成分Ｑ ｎ の信号をそれぞれ二乗した信号を生成する２つの二乗型乗算回路と、該２つの二乗型乗算回路から出力される各信号を加算する加算器と、前記減算器からの出力信号を前記加算器からの出力信号で除算する割算回路と、前記割算回路から出力される信号を逆正弦処理してその主値の信号を送出する逆正弦回路と、前記逆正弦回路から出力される信号を係数ｆ ｃｌｋ ／２πで乗算する乗算器とを具え、
前記乗算器が、
Figure 0004230688
からなる復調周波数ｆ ０ の信号を発生するようにしたことを特徴とする。
【００１０】
【作用】
以下，この誤差が零である周波数復調法を導出する。
離散化クロスプロダクト型周波数復調の特性改善と本方式の原理式
式（17）は真のf0について解ける。
【数１４】
Figure 0004230688
式（11）を代入して，
【数１５】
Figure 0004230688
式（19）が、原理的に誤算の無い周波数復調による復調周波数f0を得る本発明の原理式である。
【００１１】
【発明実施の形態】
本発明によるデジタル信号処理による周波数復調回路の原理系統図を図１に実施例として示す。即ち、図1を参照して，本発明デジタル信号処理周波数復調回路を説明する。
【００１２】
本例デジタル信号処理による周波数復調回路は図１に示すように、入力信号Inをデジタル信号処理周波数復調回路の一方の入力端子１に供給し、入力信号Qnをデジタル信号処理周波数復調回路の他方の入力端子２に供給する。この入力端子１は遅延回路３を経て乗算器５に接続するとともに他の乗算器６および二乗型乗算回路８にも直接接続する。
【００１３】
また、入力端子２は遅延回路４を経て乗算器６の入力端子へ接続するとともに前記乗算器５および二乗型乗算回路９にも直接接続する。
【００１４】
乗算器５および６を減算器７に接続し、この減算器７を割算回路11の一方の入力端子に接続する。二乗型乗算回路８および９は加算器10に接続し、その出力側を割算回路11の他方の入力端子に接続する。
【００１５】
割算回路11の出力端子を逆正弦回路12の入力端子に接続し、その出力端子を乗算器13の一方の入力端子に接続し、この乗算器13の他方の入力端子には係数fclk/2πを乗算する乗算回路14に接続する。乗算器13の出力端子を周波数復調回路の出力端子とする。
【００１６】
この様に構成された周波数復調回路の入力端子1に入力信号Inを入力するとともに入力端子2に入力信号Qnを入力する。ここに、入力信号Inおよび入力信号Qnは高周波信号の同相成分および直交成分を離散化した信号とする。
【００１７】
高周波信号の同相成分Inを遅延回路3で遅延時間δtだけ遅延し、信号In-1を得る。また、高周波信号の直交成分Qnの信号Qnを遅延回路4で遅延時間δtだけ遅延し、信号Qn-1を得る。遅延回路3および4の出力信号In-1およびQn-1をそれぞれ乗算器5および６の一方の入力端子に供給し、乗算器5および６の他方の入力端子に供給される入力信号QnおよびInと，時間δtだけ遅延した信号In-1およびQn-1を乗算し、信号In-1QnおよびInQn-1をそれぞれ得る。これら乗算器5および６の出力側の信号In-1QnおよびInQn-1を減算器７の被減算端子および減算端子にそれぞれ供給し、減算器7で，乗算器5の出力信号から，乗算器6の出力信号を減算する。
【００１８】
次に，高周波信号の同相成分Inを有する信号Inを二乗型乗算回路8で二乗し，信号In 2を形成する。同様に，高周波信号の直交成分Qnを有する信号Qnを二乗型乗算回路9で二乗し，信号Qn 2を形成する。これら二乗型乗算回路8および９の出力信号In 2およびQn 2を加算器10で加算する。
【００１９】
減算器７の出力信号および加算器10の出力信号を割算回路11で除算してその出力信号を逆正弦回路12に供給してここで振幅補正する。ここに，逆正弦回路は主値を取ることとする。この逆正弦回路12の出力信号を乗算器13に供給してここで係数発生回路14で発生するfclk/2πを乗算して、所望の周波数復調信号を出力15に得るようにする。
【００２０】
【発明の効果】
上述したように、本発明によれば従来の方法と比較して、式（17）で示される周波数誤差を含まず、正確な周波数を復調でき、従来と比較して飛躍的に性能を向上させることができる。
【図面の簡単な説明】
【図１】 図1は本発明周波数復調回路の実施例を示す回路図である。
【符号の説明】
1 入力端子
2 入力端子
3 遅延回路
4 遅延回路
5 乗算器
6 乗算器
7 減算器
8 二乗型乗算回路
9 二乗型乗算回路
10 加算器
11 割算回路
12 逆正弦回路
13 乗算器
14 係数発生回路
15 出力端子[0001]
The present invention relates to a frequency demodulation circuit that demodulates a frequency-modulated wave, and more particularly to a frequency demodulation circuit that uses digital signal processing.
[Industrial application fields]
[0002]
The frequency demodulation circuit using digital signal processing according to the present invention can be widely applied to the fields of broadcasting and communication.
[0003]
[Prior art]
Conventionally, as a method of frequency demodulation using digital signal processing, for example, a cross-product type frequency demodulation circuit is known and widely used in AFC circuits for digital communication. Hereinafter, the conventional technique will be described in detail.
[0004]
Principle of continuous signal cross product type frequency demodulation First, a mathematical expression of a conventional cross product type FM demodulator is derived. A general modulation signal g (t) can be expressed by the following equation (1) using a carrier wave ω c . Here, a ω c = 2πf c, also in-phase and quadrature components of I (t), Q (t ) of the modulated signal g (t).
[Expression 1]
Figure 0004230688
Equation (1) is transformed to obtain equation (2).
[Expression 2]
Figure 0004230688
Here, the instantaneous phase θ is the phase of the cosine function in equation (2), which is defined by the following equation (3).
[Equation 3]
Figure 0004230688
The instantaneous frequency f m can be expressed by the following equation by differentiating the phase θ (t).
[Expression 4]
Figure 0004230688
Therefore, the following formula (5) is obtained by calculating the formula (4).
[Equation 5]
Figure 0004230688
When equation (5) is calculated using the formula of the inverse tangent function and the fractional differentiation, the following equation (6) is obtained.
[Formula 6]
Figure 0004230688
The demodulated instantaneous frequency is obtained from the in-phase component and the quadrature component according to Equation (6). That is, first when adding the calculated f c the second term of Equation (6) can be obtained the instantaneous frequency f m. Here, I ′ (t) and Q ′ (t) are time derivatives of the in-phase component and the quadrature component.
[0005]
Discretized cross product type FM demodulation Next, in-phase components and quadrature components are discretized in order to perform calculation by digital signal processing. Let the discretized signals be I n , I n−1 , Q n , and Q n−1 , respectively. Differentiation is approximated by the difference, the differential I n 'and Q n' of the in-phase component I n and the quadrature component Q n are as shown in the following equation (7) and (8).
[Expression 7]
Figure 0004230688
Therefore, the instantaneous frequency f n obtained from the in-phase component and the quadrature component is expressed by the following equation (9).
[Equation 8]
Figure 0004230688
A delay time of one tap and [delta] t. The [delta] t as shown in the following equation (10) is the reciprocal of the clock frequency f clk.
[Equation 9]
Figure 0004230688
Equation (11) obtained by substituting Equation (10) into Equation (9) is the instantaneous frequency of the discretized cross product type frequency demodulator.
[Expression 10]
Figure 0004230688
[0006]
The above is a known fact, and the present invention aims to remedy the disadvantages of this discretized cross product type frequency demodulator.
[0007]
[Problems to be solved by the invention]
In the discretized cross product type frequency demodulator, an error occurs because discrete values are handled. Hereinafter, this error is derived quantitatively.
Disadvantages of discretized cross-product type frequency demodulation <br/> To obtain the error, calculate the output when the signal shown in the following equation (12) is input to equation (11) by the discretized cross-product type frequency demodulation method To do. Since the frequency of this signal is f 0 , the frequency demodulated signal must also be f 0 .
[Expression 11]
Figure 0004230688
Quadrature component and synchronous detection in-phase component at f c of entering a single sine wave input signal f 0 is as shown by the following equation.
[Expression 12]
Figure 0004230688
Substituting equations (13) to (16) into equation (11) and rearranging results in the following equation (17).
[Formula 13]
Figure 0004230688
Equation (17) represents the frequency demodulation frequency of a single sine wave demodulated by the discretized cross product type. At this time, the demodulated frequency of the demodulated single sine wave must be f 0 from the definition, but in equation (17), it is in the Sin function, not f 0 , and thus contains an error.
[0008]
The object of the present invention is in principle to obtain frequency demodulation without error.
[0009]
[Means for Solving the Problems]
Frequency demodulation circuit according to the present invention the digital signal processing are respectively connected to the two input terminal for inputting a signal in-phase component I n and a quadrature component Q n of the modulated signal, respectively, the signals of the in-phase component I n and a quadrature component Q n and delayed by the delay time of the reciprocal of the clock frequency f clk, and two delay circuit generating an in-phase component I n-1 and the quadrature component Q n-1 of the signals respectively delayed, to each of the two delay circuits a two multiplication circuits that will be connected, the quadrature component Q n that the first multiplication circuit for multiplying the signal of the quadrature component Q n before delaying the signal in-phase component I n-1 delayed, and delayed two multiplier circuit and a second multiplying circuit for multiplying the signal before the phase component I n delaying -1 signal, a subtractor for subtracting the output signals of the two multiplier circuits, wherein 2 One of the input end The respectively connected, and two square type multiplier circuit for generating a respective squared signal before phase component I n and the signal of the quadrature component Q n to delay, the signals output from the two square-type multiplier circuit an adder for adding a division circuit for dividing the output signal from the subtracter by the output signal from the adder, a signal of the main values of the signal output from the dividing circuit and arcsine treated and arc sine circuit for transmitting, and a multiplier for multiplying a signal output from the inverse sine circuit by a factor f clk / 2 [pi comprising,
The multiplier is
Figure 0004230688
Characterized by being adapted to generate signals for demodulating the frequency f 0 consisting of.
[0010]
[Action]
In the following, a frequency demodulation method in which this error is zero is derived.
Principle type <br/> type discretization cross-product type frequency demodulation of the characteristic improvement and the present method (17) is solved for the true f 0.
[Expression 14]
Figure 0004230688
Substituting equation (11),
[Expression 15]
Figure 0004230688
Equation (19) is the principle equation of the present invention for obtaining the demodulated frequency f 0 by frequency demodulation without error in principle.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
A principle system diagram of a frequency demodulating circuit by digital signal processing according to the present invention is shown in FIG. 1 as an embodiment. That is, the digital signal processing frequency demodulation circuit of the present invention will be described with reference to FIG.
[0012]
Frequency demodulation circuit according to the present embodiment digital signal processing, as shown in FIG. 1, and supplies the input signal I n to one input terminal 1 of the digital signal processing frequency demodulation circuit, an input signal Q n of the digital signal processing frequency demodulation circuit The other input terminal 2 is supplied. The input terminal 1 is connected to the multiplier 5 through the delay circuit 3 and also directly connected to the other multiplier 6 and the square type multiplier circuit 8.
[0013]
The input terminal 2 is connected to the input terminal of the multiplier 6 through the delay circuit 4 and also directly connected to the multiplier 5 and the square type multiplier circuit 9.
[0014]
Multipliers 5 and 6 are connected to a subtracter 7, and this subtracter 7 is connected to one input terminal of a division circuit 11. The square multiplier circuits 8 and 9 are connected to the adder 10 and the output side thereof is connected to the other input terminal of the divider circuit 11.
[0015]
The output terminal of the divider circuit 11 is connected to the input terminal of the inverse sine circuit 12, the output terminal is connected to one input terminal of the multiplier 13, and the other input terminal of the multiplier 13 has a coefficient f clk / Connected to a multiplier circuit 14 for multiplying by 2π. The output terminal of the multiplier 13 is used as the output terminal of the frequency demodulation circuit.
[0016]
Inputting an input signal Q n to input terminal 2 inputs the input signal I n to the input terminal 1 of the configured frequency demodulation circuit in this way. Here, an input signal I n, and input signal Q n is a discretized signal phase and quadrature components of the RF signal.
[0017]
Phase component I n of the high-frequency signal is delayed by a delay time δt in the delay circuit 3 to obtain a signal I n-1. Further, only the quadrature component Q n delay the signal Q n by the delay circuit 4 of the high-frequency signal δt delayed to obtain a signal Q n-1. Input signal Q supplied delay circuit 3 and 4 of the output signal I n-1 and Q n-1 respectively supplied to one input terminal of the multiplier 5 and 6, to the other input terminal of the multiplier 5 and 6 obtain a n and I n, the time δt only multiplies the signal I n-1 and Q n-1 the delayed signal I n-1 Q n and I n Q n-1, respectively. The signals I n−1 Q n and I n Q n−1 on the output side of the multipliers 5 and 6 are supplied to the subtracted terminal and the subtracting terminal of the subtractor 7, respectively, and the subtractor 7 outputs the output of the multiplier 5. The output signal of the multiplier 6 is subtracted from the signal.
[0018]
Subsequently, a signal I n having an in-phase component I n of the high-frequency signal squared by the square-type multiplying circuit 8 to form a signal I n 2. Similarly, a signal Q n having a quadrature component Q n of a high-frequency signal is squared by a square multiplier 9 to form a signal Q n 2 . The output signals I n 2 and Q n 2 of these square multiplication circuits 8 and 9 are added by an adder 10.
[0019]
The output signal of the subtractor 7 and the output signal of the adder 10 are divided by the division circuit 11, and the output signal is supplied to the inverse sine circuit 12, where the amplitude is corrected. Here, the inverse sine circuit takes a main value. The output signal of the inverse sine circuit 12 is supplied to the multiplier 13 where it is multiplied by f clk / 2π generated by the coefficient generation circuit 14 to obtain a desired frequency demodulated signal at the output 15.
[0020]
【The invention's effect】
As described above, according to the present invention, compared to the conventional method, the frequency error represented by the equation (17) is not included and an accurate frequency can be demodulated, and the performance is dramatically improved as compared with the conventional method. be able to.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a frequency demodulation circuit according to the present invention.
[Explanation of symbols]
1 Input terminal
2 Input terminal
3 Delay circuit
4 Delay circuit
5 multiplier
6 multiplier
7 Subtractor
8 Square type multiplication circuit
9 Square type multiplication circuit
10 Adder
11 Division circuit
12 Inverse sine circuit
13 multiplier
14 Coefficient generator circuit
15 Output terminal

Claims (1)

変調信号の同相成分Ｉ ｎ 及び直交成分Ｑ ｎ の信号をそれぞれ入力する２つの入力端子にそれぞれ接続され、各同相成分Ｉ ｎ 及び直交成分Ｑ ｎ の信号をクロック周波数ｆ ｃｌｋ の逆数の遅延時間だけ遅延させて、それぞれ遅延させた同相成分Ｉ ｎ−１ 及び直交成分Ｑ ｎ−１ の信号を生成する２つの遅延回路と、前記２つの遅延回路の各々に接続される２つの乗算回路であって、遅延させた同相成分Ｉ ｎ−１ の信号と遅延させる前の直交成分Ｑ ｎ の信号とを乗算する第１乗算回路、及び遅延させた直交成分Ｑ ｎ−１ の信号と遅延させる前の同相成分Ｉ ｎ の信号とを乗算する第２乗算回路とからなる２つの乗算回路と、該２つの乗算回路の各出力信号を減算する減算器と、前記２つの入力端子にそれぞれ接続され、遅延させる前の同相成分Ｉ ｎ 及び直交成分Ｑ ｎ の信号をそれぞれ二乗した信号を生成する２つの二乗型乗算回路と、該２つの二乗型乗算回路から出力される各信号を加算する加算器と、前記減算器からの出力信号を前記加算器からの出力信号で除算する割算回路と、前記割算回路から出力される信号を逆正弦処理してその主値の信号を送出する逆正弦回路と、前記逆正弦回路から出力される信号を係数ｆ ｃｌｋ ／２πで乗算する乗算器とを具え、
前記乗算器が、
Figure 0004230688
からなる復調周波数ｆ ０ の信号を発生するようにしたことを特徴とするデジタル信号処理による周波数復調回路。Are respectively connected to signal in-phase component I n and a quadrature component Q n of the modulated signal to the two input terminals for inputting respectively, the signals of the in-phase component I n and a quadrature component Q n by the delay time of the reciprocal of the clock frequency f clk delaying, and two delay circuit generating an in-phase component I n-1 and the quadrature component Q n-1 of the signals respectively delayed, a two multiplication circuits that will be connected to each of the two delay circuits A first multiplication circuit that multiplies the delayed in - phase component I n-1 signal by the quadrature component Q n signal before being delayed, and the in-phase before delaying the delayed quadrature component Q n-1 signal. a second multiplier circuit and two multiplier circuits consisting for multiplying the signal component I n, a subtracter for subtracting the output signals of the two multiplication circuits, respectively connected to the two input terminals, delays Previous in-phase component and two square type multiplier circuit for generating a n and a quadrature component Q n each squared signal a signal, an adder for adding the signals output from the two square-type multiplier circuit, the output from the subtracter a division circuit for dividing the signal at the output signal from said adder, and arc sine circuit for sending a signal of the main values of the signal output from said dividing circuit by arcsine process, from the arcsine circuit A multiplier for multiplying the output signal by a coefficient f clk / 2π ,
The multiplier is
Figure 0004230688
Frequency demodulation circuit according to the digital signal processing, characterized in that the the generates a signal of the demodulation frequency f 0 consisting of.
JP2001303597A 2001-09-28 2001-09-28 Frequency demodulation circuit by digital signal processing Expired - Fee Related JP4230688B2 (en)

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