JP3065509B2 - Surface mount type light emitting diode - Google Patents
Surface mount type light emitting diodeInfo
- Publication number
- JP3065509B2 JP3065509B2 JP7158810A JP15881095A JP3065509B2 JP 3065509 B2 JP3065509 B2 JP 3065509B2 JP 7158810 A JP7158810 A JP 7158810A JP 15881095 A JP15881095 A JP 15881095A JP 3065509 B2 JP3065509 B2 JP 3065509B2
- Authority
- JP
- Japan
- Prior art keywords
- emitting diode
- resist film
- solder resist
- substrate
- light emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
Landscapes
- Led Device Packages (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は発光ダイオードの構成に
関するものであり、詳細にはプリント回路基板などに取
付用の孔を設けることなく、直接に表面への実装を可能
とした表面実装型の発光ダイオードの構成に係るもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a light emitting diode, and more particularly, to a surface mount type light emitting diode which can be directly mounted on a surface without providing a mounting hole in a printed circuit board or the like. It relates to a configuration of a light emitting diode.
【０００２】[0002]
【従来の技術】従来のこの種の表面実装型発光ダイオー
ド９０の構成の例を示すものが図６および図７であり、
例えばガラスエポキシプリント回路板を利用して形成さ
れた基板９１上には導電パターン９２が設けられるもの
であり、この導電パターン９２は長方形とされた基板９
１の短辺側の二辺に設けられる端子部９２ａと、一方の
前記端子部９２ａに接続し前記基板９１の中央に向かい
延設されるパット部９２ｂと、他の一方の端子部９２ａ
に接続し前記基板９１の中央に向かい延設される配線部
９２ｃとで構成されている。2. Description of the Related Art FIGS. 6 and 7 show examples of the structure of a conventional surface mount type light emitting diode 90 of this type.
For example, a conductive pattern 92 is provided on a substrate 91 formed using a glass epoxy printed circuit board, and the conductive pattern 92 is a rectangular substrate 9.
1, a terminal portion 92a provided on two short sides, a pad portion 92b connected to one terminal portion 92a and extending toward the center of the substrate 91, and another terminal portion 92a.
And a wiring portion 92c extending toward the center of the substrate 91.
【０００３】そして、前記導電パターン９２は、通常に
は金メッキが施されて前記マウント部９２ａにＬＥＤチ
ップ９３がマウントされ、金ワイヤ９４で配線部９２ｃ
との配線が行われ、その後に透明エポキシ樹脂などで前
記ＬＥＤチップ９３と金ワイヤ９４とを覆う略直方体状
のモールド部９５が形成されて表面実装型発光ダイオー
ド９０とされるものである。The conductive pattern 92 is usually plated with gold, and an LED chip 93 is mounted on the mount 92a.
Thereafter, a substantially rectangular parallelepiped mold portion 95 covering the LED chip 93 and the gold wire 94 is formed with a transparent epoxy resin or the like, thereby forming a surface-mounted light emitting diode 90.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、前記し
た従来の構成の表面実装型発光ダイオード９０において
は、第一に、前記モールド部９５を形成するためのモー
ルド工程で、図８に示すように基板９１が金型８１、８
２で挟まれるものとなるので、このときの圧力で基板９
１が圧縮されて変形し、導電パターン９２の端子部９２
ａなどに割れ、剥がれなどを生じて導通不良となるなど
の問題点を生じている。However, in the surface mount type light emitting diode 90 having the above-described conventional structure, first, in the molding step for forming the mold portion 95, the substrate is not provided as shown in FIG. 91 is the mold 81,8
2, the substrate 9 is pressed by the pressure at this time.
1 is compressed and deformed, and the terminal portion 92 of the conductive pattern 92 is
a, etc., cause problems such as cracking and peeling, resulting in poor conduction.
【０００５】また、第二には、前記導電パターン９２と
モールド部９５とが熱膨張係数の差が大きいものである
ので、例えばプリント回路板に取付けるためのハンダリ
フロー時など高温となる雰囲気に曝された場合に、導電
パターン９２とモールド部９５とに剥離を生じ、この剥
離部分からハンダ、フラックスなどの不純物、あるいは
湿度が侵入するなどして表面実装型発光ダイオード９０
の寿命を短縮する問題点も生じ、これらの点の解決が課
題とされていた。Second, since the conductive pattern 92 and the mold portion 95 have a large difference in thermal expansion coefficient, the conductive pattern 92 and the mold portion 95 are exposed to a high-temperature atmosphere such as at the time of solder reflow for mounting on a printed circuit board. In this case, the conductive pattern 92 and the mold portion 95 are separated from each other, and impurities such as solder and flux or moisture enter the separated portion, and the surface-mounted light emitting diode 90 is removed.
There has also been a problem of shortening the service life of these devices, and solving these problems has been an issue.
【０００６】[0006]
【課題を解決するための手段】本発明は前記した従来の
課題を解決するための具体的な手段として、短辺側の二
辺には端子部が形成され上面には前記端子部と夫々が接
続するマウント部と配線部とが導電パターンで形成され
た長方形の基板の上面中央部に略直方体状としたモール
ド部を設けて成る表面実装型発光ダイオードにおいて、
前記基板の上面であり、且つ、少なくとも前記モールド
部の前記端子部と平行する二辺が基板と接する接合線を
含む部分はハンダレジスト膜で覆われていることを特徴
とする表面実装型発光ダイオードを提供することで、端
子部の割れ、モールド部の剥離を共に生じないものとし
て課題を解決するものである。According to the present invention, as a specific means for solving the above-mentioned conventional problems, terminal portions are formed on two short sides and the terminal portions are formed on the upper surface. In a surface-mounted light-emitting diode, a mounting portion and a wiring portion to be connected are provided with a substantially rectangular parallelepiped mold portion at the center of the upper surface of a rectangular substrate formed of a conductive pattern.
A surface-mounted light-emitting diode, wherein a portion including an upper surface of the substrate and including a joining line at least two sides of the mold portion parallel to the terminal portion are in contact with the substrate is covered with a solder resist film. By solving the problem, it is possible to prevent cracking of the terminal portion and peeling of the mold portion.
【０００７】[0007]
【実施例】つぎに、本発明を図に示す一実施例に基づい
て詳細に説明する。図１および図２に符号１で示すもの
は本発明に係る表面実装型発光ダイオード（以下に発光
ダイオード１と略称する）であり、この発光ダイオード
１は、端子部３ａ、マウント部３ｂ、配線部３ｃで成る
導電パターン３が形成された基板２にＬＥＤチップ４が
マウントされ、金ワイヤ５で配線が行われた後に透明樹
脂によるモールド部６が形成されるものである点は従来
例のものと同様である。Next, the present invention will be described in detail based on an embodiment shown in the drawings. 1 and 2 is a surface-mounted light-emitting diode (hereinafter abbreviated as light-emitting diode 1) according to the present invention. The light-emitting diode 1 includes a terminal portion 3a, a mount portion 3b, and a wiring portion. An LED chip 4 is mounted on a substrate 2 on which a conductive pattern 3 made of 3c is formed, and a wiring portion is formed by a gold wire 5, and then a molded portion 6 made of a transparent resin is formed. The same is true.
【０００８】ここで、本発明では前記基板２の上面２ａ
にハンダレジスト膜７を設けるものであり、上記ハンダ
レジスト膜７が設けられる位置は、端子部３ａが設けら
れている基板２の短辺２ｂに平行するモールド部６の二
辺が基板２と接する接合線６ａを少なくとも含むものと
されている。Here, in the present invention, the upper surface 2a of the substrate 2
The solder resist film 7 is provided at the position where the solder resist film 7 is provided, and two sides of the mold portion 6 parallel to the short side 2b of the substrate 2 provided with the terminal portions 3a are in contact with the substrate 2. It includes at least the joining line 6a.
【０００９】即ち、前記基板２は前記接合線６ａを境界
として、一方では基板２の上面２ａが前記端子部３ａ若
しくはマウント部３ｂ、配線部３ｃを含み露出し、他方
では基板２の上面２ａが前記端子部３ａ若しくはマウン
ト部３ｂ、配線部３ｃを含みモールド部６に覆われるも
のとなっているが、前記ハンダレジスト膜７は露出側と
覆われる側との双方にわたるようにして基板２の上面２
ａに設けられるのである。That is, the upper surface 2a of the substrate 2 is exposed including the terminal portion 3a or the mounting portion 3b and the wiring portion 3c at the bonding line 6a as a boundary, and the upper surface 2a of the substrate 2 is exposed at the other end. The solder resist film 7 includes the terminal portion 3a or the mount portion 3b and the wiring portion 3c and is covered with the mold portion 6. The solder resist film 7 extends over both the exposed side and the covered side. 2
a.
【００１０】尚、実際の発光ダイオード１の製造工程に
おいては、前記基板２を作成する際の導電パターン３が
エッチングなど適宜な手段で形成が行われた後の時点
で、例えばスクリーン印刷などにより所定位置にハンダ
レジスト膜７を予めに印刷しておけば良いものである。In the actual manufacturing process of the light emitting diode 1, after the conductive pattern 3 for forming the substrate 2 is formed by a suitable means such as etching, the predetermined pattern is formed by, for example, screen printing. What is necessary is to print the solder resist film 7 at the position in advance.
【００１１】次いで、上記の構成とした本発明の発光ダ
イオード１の作用および効果について説明を行う。先
ず、上記の構成としたことで、図３に示すようにモール
ド部６を形成するために基板２を金型１１、１２で挾ん
だ場合にも前記導電パターン３の端子部３ａに生じる割
れ、剥がれの発生は皆無となった。Next, the operation and effect of the light emitting diode 1 of the present invention having the above-described configuration will be described. First, due to the above configuration, even when the substrate 2 is sandwiched between the molds 11 and 12 to form the mold portion 6 as shown in FIG. No peeling occurred.
【００１２】これは、前記ハンダレジスト膜７が前記基
板２および導電パターン３が形成された部材に比較して
軟質であるので、上記のように金型１１、１２に挟まれ
て圧縮されたときには、このハンダレジスト膜７の部分
のみで変形を生じるものとなり、基板２に変形を生じる
ことがなく、従って、割れ、剥がれは発生しなく成るの
である。Since the solder resist film 7 is softer than the member on which the substrate 2 and the conductive pattern 3 are formed, the solder resist film 7 is compressed between the molds 11 and 12 as described above. Thus, deformation occurs only in the solder resist film 7, and no deformation occurs in the substrate 2, so that cracking and peeling do not occur.
【００１３】また、図４は環境温度の変化に対する基板
２とモールド部６との剥離発生の度合いを従来例（図６
および図７を参照）との比較で示すものであり、図中に
符号Ｔで示す曲線は本発明に係る発光ダイオード１の剥
離の発生頻度曲線であり、同じ図中に符号Ｃで示す曲線
は従来例の発光ダイオードの剥離の発生頻度曲線であ
る。FIG. 4 shows a conventional example (FIG. 6) showing the degree of occurrence of separation between the substrate 2 and the mold portion 6 with respect to a change in environmental temperature.
And FIG. 7), a curve indicated by a symbol T in the figure is a frequency curve of occurrence of peeling of the light emitting diode 1 according to the present invention, and a curve indicated by a symbol C in the same figure is It is an occurrence frequency curve of the peeling of the light emitting diode of the conventional example.
【００１４】このときの条件は、回路基板などに発光ダ
イオード１を取付けるときのリフロー炉の温度条件であ
る、前加熱（１５０℃、２分）と本加熱（２４０℃、５
秒）との組合せを１サイクルとして５サイクルを印加
し、各サイクルの終了時毎に剥離の発生を観察してい
る。The conditions at this time are preheating (150 ° C., 2 minutes) and main heating (240 ° C., 5 minutes), which are the temperature conditions of the reflow furnace when the light emitting diode 1 is mounted on a circuit board or the like.
And 5 seconds are applied with one cycle as a combination with (second), and the occurrence of peeling is observed at the end of each cycle.
【００１５】上記試験の結果では、従来例の発光ダイオ
ードは発生頻度曲線Ｃで示すように、最初の１サイクル
で１０％強のものに剥離を生じ、２サイクルでは６０％
強、３サイクルでは８２％、４サイクルでは９０％弱と
サイクルを重ねるごとに剥離の発生の度合いは進行し、
５サイクル終了時点では９５％とほぼ全てのものに剥離
を発生するものとなっている。According to the results of the above test, as shown by the frequency curve C, the light emitting diode of the conventional example peeled off in a little more than 10% in the first cycle and 60% in the second cycle.
Strong, 82% in 3 cycles, slightly less than 90% in 4 cycles, the degree of peeling progresses with each cycle.
At the end of the five cycles, almost all of the materials, 95%, are peeled off.
【００１６】これに対して、本発明の構成とした発光ダ
イオード１では５サイクルの終了時点でも全くに剥離の
発生は認められず格段に耐久性に優れるものであり、こ
れは、前記導電パターン３を含む基板２とモールド部６
との間に介在する比較的に軟質なハンダレジスト膜７が
変形して、上記両者２、６の熱膨張係数の差により生じ
た寸法差を吸収するからである。On the other hand, in the light emitting diode 1 having the structure of the present invention, no peeling was observed at the end of the five cycles, and the durability was remarkably excellent. 2 and mold part 6 including
This is because the relatively soft solder resist film 7 interposed between the two is deformed to absorb the dimensional difference caused by the difference in the coefficient of thermal expansion between the two.
【００１７】また、前記金型１１、１２に挟まれると
き、および、環境温度が変化したときの緩衝材としてハ
ンダレジスト膜７を選択したのは、上記したようにリフ
ロー炉を通過させるときに万一に剥離を生じた場合、ハ
ンダおよびフラックスが導電パターン３上を流れてＬＥ
Ｄチップ４に達するのを防止するためである。The reason why the solder resist film 7 is selected as a buffer when sandwiched between the dies 11 and 12 and when the environmental temperature changes is that when the solder resist film 7 is passed through the reflow furnace as described above. If peeling occurs, solder and flux flow on the conductive pattern 3 to cause LE
This is to prevent reaching the D chip 4.
【００１８】尚、発明者によるこの発明を成すための実
験の結果では、前記モールド部６に側方からの力を加え
て基板２と離脱させるときには、従来例のものが略１．
７Kgであったのに対して、本発明の構成とした発光ダイ
オード１では略２Kgと略１８％向上したものとなり、前
記ハンダレジスト膜７を介在させることで接着強度も向
上することが確認されている。According to the results of experiments conducted by the inventor to carry out the present invention, when the mold portion 6 is separated from the substrate 2 by applying a force from the side to the mold portion 6, the conventional one is approximately 1.
Compared to 7 kg, the light emitting diode 1 according to the present invention has an improved of about 2 kg and an improvement of about 18%. It has been confirmed that the bonding strength can be improved by interposing the solder resist film 7. I have.
【００１９】加えて、この実施例においては端子部３ａ
寄りの２個所にハンダレジスト膜７が設けられるもので
あるので、例えば、ＬＥＤチップ４のアノードに接続さ
れる端子部３ａ側のハンダレジスト膜７と、ＬＥＤチッ
プ４のカソードに接続される端子部３ａ側のハンダレジ
スト膜７とを色彩を異なるものとすれば発光ダイオード
１の極性を表示することが可能となる、In addition, in this embodiment, the terminal 3a
Since the solder resist film 7 is provided at two closer positions, for example, the solder resist film 7 on the terminal portion 3a side connected to the anode of the LED chip 4 and the terminal portion connected to the cathode of the LED chip 4 If the color of the solder resist film 7 on the 3a side is different from that of the solder resist film 7, the polarity of the light emitting diode 1 can be displayed.
【００２０】ここで、前記基板２の寸法は０．８mm×
１．６mm程度と極めて小さいものであり、現実に回路基
板などに発光ダイオード１を組付けるとき、あるいは検
査をするときの極性の判断は、極めて困難な作業となっ
ている、従って、上記のように色彩など判断を容易とす
る手段が設けられることで、組立工程、検査工程におい
て格段の作業効率の向上が期待できるものとなる。Here, the size of the substrate 2 is 0.8 mm ×
It is extremely small, about 1.6 mm, and it is extremely difficult to determine the polarity when actually mounting the light emitting diode 1 on a circuit board or performing an inspection. By providing means for easily determining colors and the like, remarkable improvement in work efficiency in the assembling process and the inspection process can be expected.
【００２１】更には、前記ＬＥＤチップ４の発光色が赤
色である場合には、アノード側の端子部３ａ側のハンダ
レジスト膜７を赤色とし、発光色が緑色である場合には
アノード側のハンダレジスト膜７を緑色とするなどＬＥ
Ｄチップ４の発光色とアノード側のハンダレジスト膜７
の色彩を関連させ、カソード側のハンダレジスト膜７を
黒色などとすれば、上記の極性表示と共に発光色の表示
も可能となる。Further, when the emission color of the LED chip 4 is red, the solder resist film 7 on the anode side terminal portion 3a is red, and when the emission color is green, the solder on the anode side is red. LE such as making the resist film 7 green
Emitting color of D chip 4 and solder resist film 7 on anode side
If the solder resist film 7 on the cathode side is made black or the like, it is possible to display the emission color together with the polarity display.
【００２２】図５に示すものは本発明の別な実施例であ
り、前の実施例が二本の接合線６ａの近傍にハンダレジ
スト膜７を形成するものとしていたが、本発明はこれを
限定するものでなく、図示のように基板２のマウント部
３ｂと配線部３ｃとを除く上面２ａの全面にハンダレジ
スト膜８を形成しても良く、要は少なくとも前記接合線
６ａを含むようにハンダレジスト膜８が形成されれば良
いものである。FIG. 5 shows another embodiment of the present invention. In the previous embodiment, the solder resist film 7 was formed near the two joining lines 6a. The solder resist film 8 may be formed on the entire surface of the upper surface 2a except for the mount portion 3b and the wiring portion 3c of the substrate 2 as shown in the drawing, and it is essential that the solder resist film 8 includes at least the bonding line 6a. What is necessary is that the solder resist film 8 is formed.
【００２３】このように形成したことでハンダレジスト
膜８はマウント部３ｂにマウントされるＬＥＤチップ４
の全周を取囲むものとなり、このときに前記ハンダレジ
スト膜８を白色として形成しておくことで反射膜を兼ね
るものとすることができ、点灯を行った際の発光ダイオ
ード１の明るさを、より一層に向上させることが可能と
なる。The solder resist film 8 formed in this manner allows the LED chip 4 mounted on the mounting portion 3b to be mounted.
At this time, the solder resist film 8 is formed in white at this time so that it can also serve as a reflection film, and the brightness of the light emitting diode 1 when lighting is performed is reduced. , Can be further improved.
【００２４】また、この実施例においても前記ハンダレ
ジスト膜８をＬＥＤチップ４の発光色と同一のものとし
ておけば、非点灯時に発光ダイオード１の発光色を表示
可能とするものとなることは、前の実施例と同様であ
る。尚、上記した以外の作用、効果については前の実施
例と全くに同様であるので、ここでの詳細な説明は省略
する。Also in this embodiment, if the solder resist film 8 is made to have the same color as the light emitted from the LED chip 4, it is possible to display the light emitted from the light emitting diode 1 when not lit. It is similar to the previous embodiment. Since the operation and effects other than those described above are completely the same as those of the previous embodiment, detailed description thereof will be omitted.
【００２５】[0025]
【発明の効果】以上に説明したように本発明により、基
板の上面であり、且つ、少なくともモールド部の端子部
と平行する二辺が基板と接する接合線を含む部分はハン
ダレジスト膜で覆われている表面実装型発光ダイオード
としたことで、第一には、モールド部を形成するための
金型による挟み込み時にも、基板の上面に設けたハンダ
レジスト膜がその柔軟性で圧力を吸収して基板の変形に
よる端子部の割れ、剥がれを防止し、導通不良を生じな
いものとして、この種の表面実装型発光ダイオードの信
頼性の向上に極めて優れた効果を奏するものである。As described above, according to the present invention, the solder resist film covers at least the portion of the upper surface of the substrate, which includes the joint line where at least two sides parallel to the terminals of the mold portion are in contact with the substrate. First, by adopting a surface mount type light emitting diode, the solder resist film provided on the upper surface of the substrate absorbs pressure due to its flexibility even when sandwiched by a mold to form a mold part. This prevents the terminal portion from being cracked or peeled off due to the deformation of the substrate and does not cause conduction failure, which is extremely effective in improving the reliability of this type of surface mount type light emitting diode.
【００２６】また、第二には、導電パターンを含む基板
の面とモールド部との間にハンダレジスト膜を介在させ
たことで、リフロー炉の通過時など環境温度が変化した
場合においても、基板とモールド部との熱膨張係数の差
により生じる寸法差を前記ハンダレジスト膜の柔軟性で
吸収するものとし、両者間に剥離を生じることをなくし
て不純物、湿度のＬＥＤチップへの侵入を防止し、劣化
を生じないものとして、この点においても表面実装型発
光ダイオードの信頼性の向上に極めて優れた効果を奏す
るものである。Second, since a solder resist film is interposed between the mold surface and the surface of the substrate including the conductive pattern, even when the ambient temperature changes, for example, when passing through a reflow furnace, The dimensional difference caused by the difference in the coefficient of thermal expansion between the solder resist film and the mold portion is absorbed by the flexibility of the solder resist film, eliminating separation between the two to prevent impurities and humidity from entering the LED chip. In this respect, it is extremely effective in improving the reliability of the surface mount type light emitting diode.
【００２７】更に、ハンダレジスト膜を夫々の端子部側
で色彩の異なるものとすることで、この種の超小型で、
且つ、対称的な形状とされて極性あるいは発光色の判断
が困難な表面実装型発光ダイオードにおいても、それら
を容易に判定できる手段を提供し、組立、検査などの工
程の効率向上にも優れた効果を奏するものとなる。Further, by making the solder resist film different in color at each terminal portion side, this kind of ultra-compact,
In addition, even in a surface-mounted light-emitting diode having a symmetrical shape and it is difficult to determine the polarity or emission color, it provides a means for easily determining these, and is excellent in improving the efficiency of processes such as assembly and inspection. It will be effective.
【００２８】加えて、ハンダレジスト膜をマウント部と
配線部とを除く基板の上面の全面に設け、且つ、その色
彩を白色あるいはＬＥＤチップの発光色とすることで、
前記ハンダレジスト膜がＬＥＤチップに対して反射膜と
しても機能するものとして、この種の表面実装型発光ダ
イオードの明るさを向上させて、性能向上にも優れた効
果を奏するものとなる。In addition, a solder resist film is provided on the entire upper surface of the substrate except for the mount portion and the wiring portion, and the color is white or the emission color of the LED chip.
Assuming that the solder resist film also functions as a reflection film for the LED chip, the brightness of this type of surface mount type light emitting diode can be improved, and the effect of improving the performance can be obtained.
【図１】 本発明に係る表面実装型発光ダイオードの一
実施例を示す斜視図である。FIG. 1 is a perspective view showing one embodiment of a surface mount type light emitting diode according to the present invention.
【図２】 同じ実施例のハンダレジスト膜の敷設の状態
を示す説明図である。FIG. 2 is an explanatory diagram showing a state of laying a solder resist film of the same embodiment.
【図３】 同じ実施例のモールド部を形成するときの状
態を示す説明図である。FIG. 3 is an explanatory view showing a state when a mold part of the same embodiment is formed.
【図４】 同じ実施例の加熱試験の結果を従来例の加熱
試験の結果との比較で示すグラフである。FIG. 4 is a graph showing a result of a heating test of the same example in comparison with a result of a heating test of a conventional example.
【図５】 同じく本発明に係る表面実装型発光ダイオー
ドの別の実施例をハンダレジスト膜の敷設の状態で示す
説明図である。FIG. 5 is an explanatory view showing another embodiment of the surface-mounted light-emitting diode according to the present invention in a state where a solder resist film is laid.
【図６】 従来例を示す斜視図である。FIG. 6 is a perspective view showing a conventional example.
【図７】 従来例の導電パターンの敷設の状態を示す説
明図である。FIG. 7 is an explanatory diagram showing a state of laying a conductive pattern according to a conventional example.
【図８】 従来例のモールド部を形成するときの状態を
示す説明図である。FIG. 8 is an explanatory view showing a state when a mold section of a conventional example is formed.
１……表面実装型発光ダイオード ２……基板 ２ａ……上面 ２ｂ……短辺 ３……導電パターン ３ａ……端子部 ３ｂ……マウント部 ３ｃ……配線部 ４……ＬＥＤチップ ５……金ワイヤ ６……モールド部 ６ａ……接合線 ７、８……ハンダレジスト膜 １１、１２……金型 DESCRIPTION OF SYMBOLS 1 ... Surface mount type light emitting diode 2 ... Substrate 2a ... Top surface 2b ... Short side 3 ... Conductive pattern 3a ... Terminal part 3b ... Mount part 3c ... Wiring part 4 ... LED chip 5 ... Gold Wire 6 Mold part 6a Joining line 7, 8 Solder resist film 11, 12 Mold
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平５−211245（ＪＰ，Ａ) 特開 平５−67698（ＪＰ，Ａ) 特開 平６−5926（ＪＰ，Ａ) 特開 平７−202271（ＪＰ，Ａ) 実開 平４−102378（ＪＰ，Ｕ) 実開 平１−171055（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 33/00 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-211245 (JP, A) JP-A-5-67698 (JP, A) JP-A-6-5926 (JP, A) JP-A-7- 202271 (JP, A) JP-A 4-102378 (JP, U) JP-A 1-171055 (JP, U) (58) Fields surveyed (Int. Cl. 7 , DB name) H01L 33/00
Claims (3)
には前記端子部と夫々が接続するマウント部と配線部と
が導電パターンで形成された長方形の基板の上面中央部
に略直方体状としたモールド部を設けて成る表面実装型
発光ダイオードにおいて、前記基板の上面であり、且
つ、少なくとも前記モールド部の前記端子部と平行する
二辺が基板と接する接合線を含む部分はハンダレジスト
膜で覆われていることを特徴とする表面実装型発光ダイ
オード。A terminal portion is formed on two short sides, and a mount portion and a wiring portion connected to the terminal portion are respectively formed on the upper surface at the center of the upper surface of a rectangular substrate formed of a conductive pattern. In the surface mounting type light emitting diode provided with a substantially rectangular parallelepiped mold portion, a portion that is a top surface of the substrate and includes a bonding line at least two sides of the mold portion parallel to the terminal portion contact the substrate. A surface-mount type light-emitting diode covered with a solder resist film.
で色彩の異なるものとされていることを特徴とする請求
項１記載の表面実装型発光ダイオード。2. The surface-mounted light-emitting diode according to claim 1, wherein the solder resist film has different colors on respective terminal portions.
と配線部とを除く前記基板の上面の全面に設けられ、且
つ、その色彩を白色、若しくは、ＬＥＤチップの発光色
とされていることを特徴とする請求項１記載の表面実装
型発光ダイオード。3. The method according to claim 1, wherein the solder resist film is provided on the entire upper surface of the substrate except for the mount portion and the wiring portion, and has a color of white or a light emission color of an LED chip. The surface-mounted light emitting diode according to claim 1.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7158810A JP3065509B2 (en) | 1995-06-02 | 1995-06-02 | Surface mount type light emitting diode |
| CN96104882A CN1127152C (en) | 1995-06-02 | 1996-05-08 | Surface mounting type light emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7158810A JP3065509B2 (en) | 1995-06-02 | 1995-06-02 | Surface mount type light emitting diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08330637A JPH08330637A (en) | 1996-12-13 |
| JP3065509B2 true JP3065509B2 (en) | 2000-07-17 |
Family
ID=15679861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7158810A Expired - Fee Related JP3065509B2 (en) | 1995-06-02 | 1995-06-02 | Surface mount type light emitting diode |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3065509B2 (en) |
| CN (1) | CN1127152C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2827388B1 (en) * | 2013-07-19 | 2020-08-19 | Nichia Corporation | Light emitting device and method of manufacturing the same |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3900595B2 (en) * | 1997-06-23 | 2007-04-04 | 日亜化学工業株式会社 | Photoelectric device |
| JP3356069B2 (en) * | 1998-07-29 | 2002-12-09 | 松下電器産業株式会社 | Chip type light emitting device |
| JP3871820B2 (en) * | 1998-10-23 | 2007-01-24 | ローム株式会社 | Semiconductor light emitting device |
| JP3895086B2 (en) * | 1999-12-08 | 2007-03-22 | ローム株式会社 | Chip-type semiconductor light-emitting device |
| JP4024994B2 (en) * | 2000-06-30 | 2007-12-19 | 株式会社東芝 | Semiconductor light emitting device |
| JP4608810B2 (en) * | 2001-05-23 | 2011-01-12 | パナソニック株式会社 | Surface mount semiconductor device |
| JP4514413B2 (en) | 2003-04-14 | 2010-07-28 | 豊田合成株式会社 | LED lamp and manufacturing method thereof |
| JP4451214B2 (en) * | 2004-05-21 | 2010-04-14 | シャープ株式会社 | Semiconductor device |
| JP4989867B2 (en) * | 2005-08-26 | 2012-08-01 | スタンレー電気株式会社 | Surface mount type LED |
| CN102983242B (en) * | 2008-01-23 | 2017-04-26 | 晶元光电股份有限公司 | Light-emitting diode element |
| CN101494260B (en) * | 2008-01-23 | 2013-02-13 | 晶元光电股份有限公司 | LED element |
| JP5104385B2 (en) * | 2008-02-20 | 2012-12-19 | 豊田合成株式会社 | LED lamp module |
| JP2012186450A (en) * | 2011-02-16 | 2012-09-27 | Rohm Co Ltd | Led module |
| JP6262816B2 (en) * | 2011-02-16 | 2018-01-17 | ローム株式会社 | LED module |
| JP2011146735A (en) * | 2011-03-22 | 2011-07-28 | Rohm Co Ltd | Method for manufacturing semiconductor light emitting device |
| JP6553143B2 (en) * | 2012-05-09 | 2019-07-31 | ローム株式会社 | Semiconductor light emitting device |
| KR102123039B1 (en) | 2013-07-19 | 2020-06-15 | 니치아 카가쿠 고교 가부시키가이샤 | Light emitting device and method of manufacturing the same |
| JP7029223B2 (en) * | 2016-07-13 | 2022-03-03 | ローム株式会社 | Semiconductor light emitting device |
| JP2018014462A (en) * | 2016-07-22 | 2018-01-25 | キヤノン株式会社 | Optical sensor, scanner unit, and image forming apparatus |
| JP7022510B2 (en) * | 2017-02-17 | 2022-02-18 | ローム株式会社 | Manufacturing method of semiconductor light emitting device and semiconductor light emitting device |
| US10559723B2 (en) * | 2017-08-25 | 2020-02-11 | Rohm Co., Ltd. | Optical device |
| JP2018142708A (en) * | 2018-04-02 | 2018-09-13 | ローム株式会社 | Led module and packaging structure of the same |
| JP2020027824A (en) * | 2018-08-09 | 2020-02-20 | ローム株式会社 | Light-emitting device and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58122756A (en) * | 1982-01-14 | 1983-07-21 | Matsushita Electric Ind Co Ltd | Semiconductor element mounting apparatus |
| JPS63174379A (en) * | 1987-01-14 | 1988-07-18 | Toshiba Corp | Luminous display device |
-
1995
- 1995-06-02 JP JP7158810A patent/JP3065509B2/en not_active Expired - Fee Related
-
1996
- 1996-05-08 CN CN96104882A patent/CN1127152C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2827388B1 (en) * | 2013-07-19 | 2020-08-19 | Nichia Corporation | Light emitting device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1140904A (en) | 1997-01-22 |
| JPH08330637A (en) | 1996-12-13 |
| CN1127152C (en) | 2003-11-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3065509B2 (en) | Surface mount type light emitting diode | |
| US5882949A (en) | Method of making compact light-emitting device with sealing member | |
| US7282740B2 (en) | Semiconductor light emitting device | |
| KR20020018058A (en) | Semiconductor device | |
| JP2009524930A (en) | Light emitting diode package and manufacturing method thereof | |
| CN100499187C (en) | Light-emitting diode | |
| JP2009048915A (en) | Led lamp, and led lamp module | |
| JP2914097B2 (en) | Injection molded printed circuit board | |
| JPH07235624A (en) | Led lamp | |
| JPH1050734A (en) | Chip type semiconductor | |
| JPH09172104A (en) | Board for semiconductor device | |
| JPH11112036A (en) | Surface mounting semiconductor device | |
| JPH06291230A (en) | Manufacture of composite semiconductor device | |
| JP2004079619A (en) | Light emitting diode device | |
| CN218039260U (en) | Semiconductor device and packaging system | |
| CN111750339B (en) | Electronic device and method for manufacturing the same | |
| JP3188058B2 (en) | Light emitting diode | |
| JP2901955B1 (en) | Circuit board, board mounting method and circuit assembly | |
| JP4608810B2 (en) | Surface mount semiconductor device | |
| JPH087435Y2 (en) | Electronic keyboard instrument switch mounting structure | |
| JPH10199899A (en) | Manufacture of semiconductor device | |
| JP2001024237A (en) | Led and display device using the same | |
| JPH0778936A (en) | Multichip module | |
| JP2003133482A (en) | Tip part and its manufacturing method | |
| JPH0355898A (en) | Electronic circuit module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080512 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090512 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090512 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100512 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110512 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110512 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120512 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130512 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140512 Year of fee payment: 14 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |