JP2003133482A - Tip part and its manufacturing method - Google Patents
Tip part and its manufacturing methodInfo
- Publication number
- JP2003133482A JP2003133482A JP2001326707A JP2001326707A JP2003133482A JP 2003133482 A JP2003133482 A JP 2003133482A JP 2001326707 A JP2001326707 A JP 2001326707A JP 2001326707 A JP2001326707 A JP 2001326707A JP 2003133482 A JP2003133482 A JP 2003133482A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- substrate
- chip
- light emitting
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、チップ部品およびそ
の製造方法に関し、特にたとえば、基板の表面上に素子
チップを取り付け、基板の裏面両端に素子チップに接続
された２つの電極が配置された、チップ部品およびその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip component and a method of manufacturing the same, and more particularly, for example, an element chip is mounted on the front surface of a substrate, and two electrodes connected to the element chip are arranged at both ends of the back surface of the substrate. , A chip component and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】この種の従来のチップ部品の一例が平成
５年１０月８日付で出願公開された実開平５−７３９５
８号公報［Ｈ０１Ｌ ２３／２８，Ｈ０５ １／１８］
に開示されている。図９（Ａ）に示すように、この従来
技術の電子部品装置１は、樹脂ケース２の両端に外部端
子３ａおよび外部端子３ｂが設けられる。図示は省略す
るが、この外部端子３ａおよび外部端子３ｂのそれぞれ
に連結される内部端子に、半導体素子やコンデンサ等の
電子部品が接続される。ケース２の裏面（図９（Ａ）に
おいては、上面）側の中央には、凹部４が形成され、そ
の凹部４から外部端子３ａおよび外部端子３ｂの無いケ
ース２側面に開放された溝５が設けられる。図９（Ｂ）
に示すように、この電子機器装置１を回路基板６に実装
する場合には、回路基板６に設けられた２つのソルダリ
ングパット７の間に接着剤８が塗布される。このとき、
過剰な接着剤８は、溝５から外部端子３ａおよび外部端
子３ｂの無いケース２側面に流出されるため、接着剤８
がソルダリングパット７に付着することがなく、半田付
け不良の無い表面実装が可能であった。2. Description of the Related Art An example of a conventional chip component of this type was filed and published on October 8, 1993, in Japanese Utility Model Publication No. 5-7395.
No. 8 [H01L 23/28, H05 1/18]
Is disclosed in. As shown in FIG. 9 (A), in the electronic component device 1 of the related art, an external terminal 3 a and an external terminal 3 b are provided at both ends of a resin case 2. Although illustration is omitted, electronic parts such as a semiconductor element and a capacitor are connected to the internal terminals connected to the external terminal 3a and the external terminal 3b, respectively. A recess 4 is formed in the center of the back surface (upper surface in FIG. 9A) of the case 2, and a groove 5 is opened from the recess 4 to the side surface of the case 2 without the external terminals 3a and the external terminals 3b. It is provided. FIG. 9 (B)
As shown in FIG. 3, when the electronic device 1 is mounted on the circuit board 6, the adhesive 8 is applied between the two soldering pads 7 provided on the circuit board 6. At this time,
The excess adhesive 8 flows out from the groove 5 to the side surface of the case 2 where the external terminals 3a and 3b are not provided.
Did not adhere to the soldering pads 7, and surface mounting without defective soldering was possible.
【０００３】[0003]
【発明が解決しようとする課題】しかし、従来の電子部
品装置１では、図９（Ａ）に示したように、ケース２に
は、凹部４および溝５を形成するため、ケース２を形成
するための金型を製造するのが面倒であった。結果とし
て、電子部品装置１が高価になってしまうという問題が
あった。However, in the conventional electronic component device 1, as shown in FIG. 9A, the case 2 is formed because the recess 4 and the groove 5 are formed in the case 2. Was difficult to manufacture. As a result, there is a problem that the electronic component device 1 becomes expensive.
【０００４】それゆえに、この発明の主たる目的は、簡
単な構成で実装不良を防止できる、チップ部品を提供す
ることである。Therefore, a main object of the present invention is to provide a chip part which can prevent mounting defects with a simple structure.
【０００５】また、この発明の他の目的は、安価に製造
できる、チップ部品の製造方法を提供することである。Another object of the present invention is to provide a method of manufacturing a chip component which can be manufactured at low cost.
【０００６】[0006]
【課題を解決するための手段】第１の発明は、基板の表
面上に素子チップを取り付け、基板の裏面両端に素子チ
ップに接続された２つの電極が配置されたチップ部品に
おいて、レジスト印刷によって２つの電極の間に凸部を
設けたことを特徴とする、チップ部品である。According to a first aspect of the present invention, an element chip is mounted on a front surface of a substrate, and two electrodes connected to the element chip are arranged on both ends of a back surface of the substrate. The chip component is characterized in that a convex portion is provided between two electrodes.
【０００７】第２の発明は、基板の表面上に素子チップ
を取り付け、基板の裏面両端に素子チップに接続された
２つの電極が配置されたチップ部品において、電極と同
じ材料によって２つの電極の間に凸部を設けたことを特
徴とする、チップ部品である。According to a second aspect of the present invention, in a chip component in which an element chip is mounted on the front surface of a substrate and two electrodes connected to the element chip are arranged at both ends of the back surface of the substrate, the two electrodes are made of the same material as the electrodes. The chip component is characterized in that a convex portion is provided therebetween.
【０００８】第３の発明は、基板の表面上に素子チップ
を取り付け、基板の裏面両端に素子チップに接続された
２つの電極が配置されたチップ部品の製造方法であっ
て、基板の裏面両端に２つの電極を形成し、レジスト印
刷することにより２つの電極間に凸部を形成し、そして
素子チップを基板の表面上に取り付けた、チップ部品の
製造方法である。A third aspect of the present invention is a method of manufacturing a chip component in which an element chip is mounted on the front surface of a substrate, and two electrodes connected to the element chip are arranged on both ends of the back surface of the substrate. Is a method for manufacturing a chip component, in which two electrodes are formed on the substrate, resist printing is performed to form a convex portion between the two electrodes, and the element chip is attached on the surface of the substrate.
【０００９】第４の発明は、基板の表面上に素子チップ
を取り付け、基板の裏面両端に素子チップに接続された
２つの電極が配置されたチップ部品の製造方法であっ
て、表面に導電性の材料を貼り付けた基板を準備し、基
板にエッチング処理を施して、基板の裏面両端に２つの
電極を形成するとともに、２つの電極間に凸部を形成
し、そして素子チップを基板の表面上に取り付けた、チ
ップ部品の製造方法である。A fourth aspect of the present invention is a method of manufacturing a chip component in which an element chip is mounted on the front surface of a substrate, and two electrodes connected to the element chip are arranged on both ends of the back surface of the substrate, and the surface of the element is electrically conductive. The substrate on which the above material is attached is prepared, and the substrate is subjected to an etching treatment to form two electrodes on both ends of the back surface of the substrate, a convex portion is formed between the two electrodes, and the element chip is mounted on the front surface of the substrate. It is a method of manufacturing a chip component attached above.
【００１０】[0010]
【作用】第１の発明のチップ部品では、基板の表面上に
素子チップが取り付けられる。また、基板の裏面両端に
は、素子チップに接続された２つの電極が配置される。
この２つの電極の間には、レジスト印刷を施すことによ
り、凸部が設けられる。たとえば、このようなチップ部
品は、電子機器のプリント基板（回路基板）に実装され
る。チップ部品を回路基板に実装する際には、まず、チ
ップ部品に設けられた２つの電極に接続されるべき回路
基板上の２つの電極（パターン電極）の間に接着剤が塗
布される。次に、チップ部品の電極が当該パターン電極
に接合するように、チップ部品が回路基板上にマウント
される。このとき、チップ部品の自重等により、接着剤
は放射状に押し広げられるが、当該パターン電極（チッ
プ部品の電極）側への広がりは凸部によって阻止され
る。つまり、接着剤がチップ部品の電極とパターン電極
との接合部に侵入してしまうことがない。In the chip component of the first invention, the element chip is mounted on the surface of the substrate. Further, two electrodes connected to the element chip are arranged on both ends of the back surface of the substrate.
A convex portion is provided between the two electrodes by performing resist printing. For example, such a chip component is mounted on a printed circuit board (circuit board) of an electronic device. When mounting the chip component on the circuit board, first, an adhesive is applied between the two electrodes (pattern electrodes) on the circuit board to be connected to the two electrodes provided on the chip component. Next, the chip component is mounted on the circuit board so that the electrode of the chip component is bonded to the pattern electrode. At this time, the adhesive is radially spread by the weight of the chip component, etc., but the convex portion prevents the pattern electrode (electrode of the chip component) from spreading. That is, the adhesive does not enter the joint between the electrode of the chip component and the pattern electrode.
【００１１】第２の発明はのチップ部品では、基板の裏
面両端に配置される電極と同じ材料（たとえば、銅 (銅
箔））を用いて凸部を形成するようにした以外は第１の
発明と同じであるため、重複した説明は省略する。In the chip component of the second invention, the convex portion is formed by using the same material (for example, copper (copper foil)) as the electrodes arranged on both ends of the back surface of the substrate. Since it is the same as the invention, duplicate description is omitted.
【００１２】たとえば、第１の発明および第２の発明で
は、凸部は、基板裏面の２つの電極が設けられない側面
側に延びて形成される凸条である。つまり、凸部は、２
つの電極が対向する端縁に平行或いはほぼ平行に延びて
形成される。したがって、チップ部品を回路基板に実装
する際に、チップ部品の電極とパターン電極との接合部
に接着剤が侵入するのを防止することができる。For example, in the first invention and the second invention, the convex portion is a convex strip formed to extend to the side surface side where two electrodes are not provided on the back surface of the substrate. That is, the convex portion is 2
Two electrodes are formed so as to extend in parallel or substantially in parallel with the opposite edges. Therefore, when the chip component is mounted on the circuit board, it is possible to prevent the adhesive from entering the joint portion between the electrode of the chip component and the pattern electrode.
【００１３】また、凸部は、リング状に形成するように
してもよい。この場合には、リング状の凸部により、接
着剤が放射状に広がるのを防止できる。つまり、チップ
部品から接着剤がはみ出すのを防止できるため、隣接す
るチップ部品の実装不良の発生も防止（回避）すること
ができる。Further, the convex portion may be formed in a ring shape. In this case, the ring-shaped protrusion can prevent the adhesive from spreading radially. That is, since the adhesive can be prevented from protruding from the chip component, it is possible to prevent (avoid) the occurrence of mounting failure of the adjacent chip component.
【００１４】第３の発明は、第１の発明のチップ部品の
製造方法である。まず、基板の裏面両端に２つの電極が
形成される。次に、レジスト印刷処理を施すことによ
り、２つの電極間に凸部が形成され。そして、基板の表
面上に素子チップが接続される。このように、レジスト
印刷処理を施すだけなので、製造コストを抑えることが
できる。A third invention is a method for manufacturing a chip part of the first invention. First, two electrodes are formed on both ends of the back surface of the substrate. Next, a resist printing process is performed to form a convex portion between the two electrodes. Then, the element chip is connected to the surface of the substrate. Since the resist printing process is only performed in this way, the manufacturing cost can be suppressed.
【００１５】第４の発明は、第２の発明のチップ部品の
製造方法である。まず、表面に導電性の材料、たとえば
銅（箔）が貼り付けられた（ラミネートされた）基板が
準備さえる。次に、この基板に対して所定のパターンに
従ってエッチング処理を施すことにより、余分な導電性
の材料が食刻され、２つの電極が形成されるとともに、
その間に凸部が形成される。そして、基板の表面上に素
子チップが接続される。このように、同じ工程で、電極
と凸部とを同じ材料で形成するので、さらに製造コスト
を抑えることができる。A fourth invention is a method for manufacturing a chip part of the second invention. First, a substrate having a conductive material, for example, copper (foil) attached to its surface (laminated) is prepared. Next, by subjecting this substrate to an etching treatment in accordance with a predetermined pattern, the excess conductive material is etched to form two electrodes, and at the same time,
A convex portion is formed therebetween. Then, the element chip is connected to the surface of the substrate. In this way, since the electrodes and the protrusions are formed of the same material in the same process, the manufacturing cost can be further reduced.
【００１６】[0016]
【発明の効果】この発明によれば、凸部を設けるだけ
で、この凸部によってチップ部品および回路基板の電極
に接着剤が付着するのを防止できるので、簡単な構成で
実装不良を防止することができる。According to the present invention, it is possible to prevent the adhesive from adhering to the electrodes of the chip component and the circuit board by means of the protrusions only by providing the protrusions, so that the mounting failure can be prevented with a simple structure. be able to.
【００１７】また、レジスト印刷やエッチング処理を施
すだけなので、製造コストを抑えることができ、結果と
して、製品コストを低下させることができる。Further, since only resist printing or etching is performed, the manufacturing cost can be suppressed, and as a result, the product cost can be reduced.
【００１８】この発明の上述の目的，その他の目的，特
徴および利点は、図面を参照して行う以下の実施例の詳
細な説明から一層明らかとなろう。The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the detailed description of the following embodiments given with reference to the drawings.
【００１９】[0019]
【実施例】図１を参照して、この実施例のチップ部品と
しての半導体発光装置（以下、単に「発光装置」とい
う。）１０は、ガラスエポキシ或いはセラミック等の絶
縁性の材料で形成された基板１２を含む。基板１２の表
面には、２つのパターン電極（以下、単に「電極」とい
う。）１４ａおよび電極１４ｂが形成される。電極１４
および電極１６はたとえば銅（銅泊）で形成され、図１
のＩＩ−ＩＩ断面である図２から分かるように、基板１
２の上面から側面を介して下面まで伸びて形成されてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a semiconductor light emitting device (hereinafter, simply referred to as "light emitting device") 10 as a chip component of this embodiment is formed of an insulating material such as glass epoxy or ceramic. A substrate 12 is included. Two pattern electrodes (hereinafter, simply referred to as “electrodes”) 14 a and electrodes 14 b are formed on the surface of the substrate 12. Electrode 14
The electrodes 16 are made of, for example, copper (copper foil), and
2 which is a II-II cross section of FIG.
2 extends from the upper surface to the lower surface via the side surface.
【００２０】なお、図面においては、分かり易くするた
めに、電極１４ａおよび電極１４ｂに厚みを設けて示し
てあるが、実際には薄膜の厚さに形成される。In the drawings, the electrodes 14a and 14b are shown with a thickness for the sake of clarity, but they are actually formed with a thin film thickness.
【００２１】また、基板１２の裏面（下面）には、２つ
の電極（電極１４ａおよび電極１４ｂ）の間に、電極１
４ａおよび電極１４ｂが形成されていない基板１２側面
に向けて延びる凸条１６が形成される。つまり、発光装
置１０を裏面（下面）側から見た図３に示すように、凸
条１６は、電極１４ａと電極１４ｂとが対向する端縁と
平行或いはほぼ平行であり、電極１４ａおよび電極１４
ｂとは一定距離を隔てて設けられる。たとえば、この凸
条１６はレジストを塗布 (印刷）することにより形成さ
れ、電極１４ａおよび電極１４ｂと同様に、薄膜の厚さ
に形成される。On the back surface (lower surface) of the substrate 12, the electrode 1 is provided between the two electrodes (electrode 14a and electrode 14b).
A ridge 16 extending toward the side surface of the substrate 12 on which the electrode 4a and the electrode 14b are not formed is formed. That is, as shown in FIG. 3 when the light emitting device 10 is viewed from the back surface (lower surface) side, the ridges 16 are parallel or substantially parallel to the edges where the electrodes 14a and 14b face each other, and thus the electrodes 14a and 14b.
It is provided at a constant distance from b. For example, the ridge 16 is formed by applying (printing) a resist, and is formed to have a thin film thickness like the electrodes 14a and 14b.
【００２２】なお、図面においては、分かり易くするた
めに、電極１４ａおよび電極１４ｂと同様に厚みを設け
て示してある。In the drawings, for the sake of clarity, the electrodes 14a and 14b are shown to have the same thickness as the electrodes 14a and 14b.
【００２３】図１に戻って、発光装置１０はまた、半導
体発光素子チップ（以下、「ＬＥＤチップ」という。）
１８を含み、ＬＥＤチップ１８は基板１２の上面１２ａ
側であり、電極１４ａ上に銀ペーストのような導電性の
接着剤（図示せず）によってダイボンディング（接着）
される。また、ＬＥＤチップ１８と電極１４ｂとが、金
線或いは銅線のような金属細線（ワイヤ）２０によって
電気的に接続される。このようにして、ＬＥＤチップ１
８が電極１４ａおよび電極１４ｂにボンディングされ
る。さらに、ＬＥＤチップ１８およびワイヤ２０は、基
板１２、電極１４ａおよび電極１４ｂの上に形成される
エポキシ樹脂のような透光性樹脂２２によって封止され
る。Returning to FIG. 1, the light emitting device 10 also includes a semiconductor light emitting element chip (hereinafter referred to as "LED chip").
The LED chip 18 includes the LED chip 18 and the upper surface 12a of the substrate 12.
Side, and die bonding (adhesion) on the electrode 14a with a conductive adhesive (not shown) such as silver paste.
To be done. Further, the LED chip 18 and the electrode 14b are electrically connected by a thin metal wire (wire) 20 such as a gold wire or a copper wire. In this way, the LED chip 1
8 is bonded to the electrodes 14a and 14b. Further, the LED chip 18 and the wires 20 are sealed with a transparent resin 22 such as an epoxy resin formed on the substrate 12, the electrodes 14a and the electrodes 14b.
【００２４】この実施例の発光装置１０を製造する場合
には、図４（Ａ）および図４（Ｂ）に示すような複数の
基板１２（複数の電極１４ａおよび電極１４ｂを含
む。）が連続的に形成された連続体３０が準備される。
この連続体３０は、電極１４ａおよび電極１４ｂが形成
された基板１２を複数（図４（Ａ）および図４（Ｂ）の
例では５個）の発光装置１０に対応する数だけ連結した
大きさである。In manufacturing the light emitting device 10 of this embodiment, a plurality of substrates 12 (including a plurality of electrodes 14a and 14b) as shown in FIGS. 4A and 4B are continuous. The continuously formed continuous body 30 is prepared.
The continuous body 30 has a size in which the substrates 12 on which the electrodes 14a and 14b are formed are connected by the number corresponding to a plurality (five in the example of FIGS. 4A and 4B) of the light emitting devices 10. Is.
【００２５】図示は省略するが、このような連続体３０
を形成する場合には、まず、基板１２が連続的に形成さ
れた連続基板３２の表面に銅箔がラミネートされる。次
に、図４（Ａ）および図４（Ｂ）に示したような所定の
パターンに従ってエッチング処理が施され、つまり不要
な銅箔が食刻され、複数の発光装置１０に対応する電極
対（電極１４ａおよび電極１４ｂ）が連続基板３２の表
面に形成される。Although not shown, such a continuous body 30
In the case of forming, the copper foil is first laminated on the surface of the continuous substrate 32 on which the substrate 12 is continuously formed. Next, an etching process is performed according to a predetermined pattern as shown in FIGS. 4A and 4B, that is, unnecessary copper foil is etched, and electrode pairs (corresponding to a plurality of light emitting devices 10) are formed. Electrodes 14a and 14b) are formed on the surface of continuous substrate 32.
【００２６】なお、隣接する電極１４ａ同士は連続的に
形成され、同様に、隣接する電極１４ｂ同士は連続的に
形成される。The adjacent electrodes 14a are continuously formed, and similarly, the adjacent electrodes 14b are continuously formed.
【００２７】その後、レジスト印刷処理が施され、図４
（Ｂ）に示すように、複数の凸条１６が連続基板３２の
裏面側に連続的に形成される。具体的には、複数の電極
１４ａと複数の電極１４ｂとが対向する端縁と一定距離
を隔てて、その端縁と平行に延びるように、レジストが
塗布（印刷）される。After that, resist printing processing is performed, and FIG.
As shown in (B), a plurality of ridges 16 are continuously formed on the back surface side of the continuous substrate 32. Specifically, the resist is applied (printed) such that the plurality of electrodes 14a and the plurality of electrodes 14b are spaced apart from the facing edges by a certain distance and extend in parallel to the edges.
【００２８】このように形成された連続体３０を用い
て、複数の電極１４ａのそれぞれに導電性の接着剤（図
示せず）が塗布される。続いて、図５（Ａ）に示すよう
に、それぞれの電極１４ａ上にＬＥＤチップ１８がマウ
ントされる。したがって、ＬＥＤチップ１８がダイボン
ディングされる。Using the thus formed continuous body 30, a conductive adhesive (not shown) is applied to each of the plurality of electrodes 14a. Subsequently, as shown in FIG. 5A, the LED chips 18 are mounted on the respective electrodes 14a. Therefore, the LED chip 18 is die-bonded.
【００２９】次の工程では、図５（Ｂ）に示すように、
ＬＥＤチップ１８がワイヤ２０を用いてワイヤボンディ
ングされる。つまり、ＬＥＤチップ１８とそのＬＥＤチ
ップ１８がダイボンディングされた電極１４ａに対応す
る電極１４ｂとがワイヤ２０によって電気的に接続され
る。In the next step, as shown in FIG.
The LED chip 18 is wire-bonded using the wire 20. That is, the LED chip 18 and the electrode 14b corresponding to the electrode 14a die-bonded to the LED chip 18 are electrically connected by the wire 20.
【００３０】続いて、図６（Ａ）に示すように、ＬＥＤ
チップ１８がボンディングされた連続体３０が上型３４
ａと下型３４ｂとの間に配置される。そして、図６
（Ｂ）に示すように、上型３４ａと下型３４ｂとで形成
されたキャビネット３６内に透光性樹脂２２がモールド
される。透光性樹脂２２が硬化されると、図６（Ｃ）に
示すように、金型（上型３４ａおよび下型３４ｂ）が離
型され、発光装置１０の１つ分の大きさ毎にダイシング
（切断）される。このようにして、図１に示したような
発光装置１０が複数製造される。Then, as shown in FIG. 6A, the LED
The continuous body 30 to which the chip 18 is bonded is the upper mold 34.
It is arranged between a and the lower mold 34b. And FIG.
As shown in (B), the translucent resin 22 is molded in a cabinet 36 formed by an upper mold 34a and a lower mold 34b. When the translucent resin 22 is cured, the mold (upper mold 34a and lower mold 34b) is released from the mold as shown in FIG. 6C, and dicing is performed for each size of the light emitting device 10. (Cut). In this way, a plurality of light emitting devices 10 as shown in FIG. 1 are manufactured.
【００３１】また、この実施例の発光装置１０は、携帯
電話機のような電子機器に適用され、たとえば、テンキ
ー（ダイヤルキー）、通話キー或いは切断キーなどの各
種キースイッチを照明するようなバックライト方式の照
明装置として用いられる。具体的には、発光装置１０
は、図７（Ａ）に示すような態様で、電子機器（図示せ
ず）に設けられる回路基板４０に実装される。The light emitting device 10 of this embodiment is applied to an electronic device such as a mobile phone, and is a backlight for illuminating various key switches such as a ten-key (dial key), a call key or a disconnect key. It is used as a lighting device of the type. Specifically, the light emitting device 10
Is mounted on a circuit board 40 provided in an electronic device (not shown) in a mode as shown in FIG.
【００３２】このような回路基板４０に発光装置１０を
実装する場合には、まず、回路基板４０に形成されたパ
ターン電極４２ａとパターン電極４２ｂとの間に、たと
えば、ペースト状の接着剤４４が印刷（塗布）される。When mounting the light emitting device 10 on such a circuit board 40, first, for example, a paste adhesive 44 is provided between the pattern electrodes 42a and 42b formed on the circuit board 40. It is printed (applied).
【００３３】次に、パターン電極４２ａおよびパターン
電極４２ｂに、電極１４ａおよび電極１ｂが接触するよ
うに、発光装置１０が回路基板４０上に配置（マウン
ト）される。このとき、発光装置１０は、パターン電極
４２ａ、４２ｂ間に塗布された接着剤４４によって、回
路基板４０に固定（仮留め）される。Next, the light emitting device 10 is placed (mounted) on the circuit board 40 so that the electrode 14a and the electrode 1b are in contact with the pattern electrode 42a and the pattern electrode 42b. At this time, the light emitting device 10 is fixed (temporarily fixed) to the circuit board 40 by the adhesive 44 applied between the pattern electrodes 42a and 42b.
【００３４】このとき、接着剤４４は、発光装置１０の
自重等により、回路基板４０上を水平方向（放射状）に
広がろうとするが、パターン電極４２ａおよびパターン
電極４２ｂ（電極１４ａおよび電極１４ｂ）側への広が
りは凸条１６によって阻止される。このため、接着剤４
４が、電極１４ａとパターン電極４２ａとの接合部およ
び電極１４ｂとパターン電極４２ｂとの接合部に侵入す
るのを防止できる。したがって、各接合部での接合（接
続）不良が発生することはない。At this time, the adhesive 44 tries to spread in the horizontal direction (radially) on the circuit board 40 due to the weight of the light emitting device 10 or the like, but the pattern electrode 42a and the pattern electrode 42b (the electrodes 14a and 14b). The lateral extension is blocked by the ridge 16. Therefore, the adhesive 4
4 can be prevented from entering the joint between the electrode 14a and the pattern electrode 42a and the joint between the electrode 14b and the pattern electrode 42b. Therefore, no defective joint (connection) occurs at each joint.
【００３５】続いて、図７に示すように、電極１４ａお
よび電極１４ｂの側面側とパターン電極４２ａおよびパ
ターン電極４２ｂの上面側とを覆うように、半田ペース
ト４６が塗布される。この状態で、発光装置１０および
回路基板４０等がリフロ炉（図示せず）を通され、その
後、常温で冷却される。したがって、半田ペースト４６
が溶融および凝固して、電極１４ａとパターン電極４２
ａとが接合されるとともに、電極１４ｂとパターン電極
４２ｂとが接合される。つまり、発光装置１０が回路基
板４０に接合（実装）される。Then, as shown in FIG. 7, a solder paste 46 is applied so as to cover the side surfaces of the electrodes 14a and 14b and the upper surfaces of the pattern electrodes 42a and 42b. In this state, the light emitting device 10 and the circuit board 40 are passed through a reflow furnace (not shown), and then cooled at room temperature. Therefore, the solder paste 46
Melts and solidifies, and the electrode 14a and the pattern electrode 42
The electrode 14b and the pattern electrode 42b are joined together as well as a. That is, the light emitting device 10 is bonded (mounted) to the circuit board 40.
【００３６】なお、図７から分かるように、凸条１６と
回路基板４０との間には、パタン電極４２ａ、４２ｂの
厚みに相当する隙間が形成されるため、凸条１６を電極
１４ａ、１４ｂよりも少し厚く形成して、隙間をなくす
ようにすれば、接着剤４４の侵入を効果的に防止するこ
とができると考えられる。As can be seen from FIG. 7, since a gap corresponding to the thickness of the pattern electrodes 42a and 42b is formed between the ridge 16 and the circuit board 40, the ridge 16 is connected to the electrodes 14a and 14b. It is considered that the intrusion of the adhesive 44 can be effectively prevented by forming the adhesive 44 to be slightly thicker than that to eliminate the gap.
【００３７】ただし、この場合には、凸条１６の厚みを
大きくし過ぎると、電極１４ａ、１４ｂと電極４２ａ、
４２ｂとの間に隙間が形成されてしまう恐れがあるの
で、注意する必要がある。However, in this case, if the thickness of the ridge 16 is excessively increased, the electrodes 14a, 14b and the electrode 42a,
It is necessary to be careful because a gap may be formed between 42b and 42b.
【００３８】また、連続体３０を準備（形成）するとき
に、レジストを印刷して、複数の凸条１６を形成するよ
うにしたが、複数の凸条１６は、透光性樹脂２２を形成
した後に形成するようにしてもよい。Further, when the continuous body 30 is prepared (formed), the resist is printed to form the plurality of ridges 16. However, the plurality of ridges 16 form the transparent resin 22. It may be formed after that.
【００３９】この実施例によれば、発光装置の裏面電極
間に凸条のレジストを印刷するだけなので、簡単に製造
することができる。しかも、その凸条によって、接着剤
が発光装置の電極の表面や発光装置を実装する回路基板
のパターン電極に表面に侵入するのを防止できるので、
実装不良を防止することができる。すなわち、製品（電
子機器）の歩溜まりを向上させることができる。According to this embodiment, since only the resist having convex stripes is printed between the back electrodes of the light emitting device, it can be easily manufactured. Moreover, since the ridge can prevent the adhesive from invading the surface of the electrode of the light emitting device or the pattern electrode of the circuit board mounting the light emitting device on the surface,
Mounting failure can be prevented. That is, the yield of products (electronic devices) can be improved.
【００４０】なお、この実施例では、凸条１６をレジス
トで形成するようにしたが、凸条１６は電極１４ａ、１
４ｂと同じ材料（この実施例では、銅箔）で形成するよ
うにしてもよい。この場合には、発光装置１０の製造時
に、連続体３０の表面にラミネートされた銅箔に、複数
の凸条１６に対応するパターンを含む所定のパターンに
従ってエッチング処理を施し、複数の電極１４ａ、電極
１４ｂおよび凸条１６を同時に（同じ工程で）形成する
ようにすればよい。In this embodiment, the ridges 16 are made of resist, but the ridges 16 are formed by the electrodes 14a and 1a.
The same material as 4b (copper foil in this embodiment) may be used. In this case, at the time of manufacturing the light emitting device 10, the copper foil laminated on the surface of the continuous body 30 is subjected to an etching treatment according to a predetermined pattern including a pattern corresponding to the plurality of ridges 16, and a plurality of electrodes 14a, The electrode 14b and the ridge 16 may be formed simultaneously (in the same step).
【００４１】また、この実施例では、基板１２の裏面１
２ｃ側の電極１４ａおよび電極１４ｂの間に２つの凸条
１６を形成するようにしたが、発光装置１０を回路基板
４０に実装するときに、回路基板４０に塗布された接着
剤４４が電極の接合部に侵入するのを阻止できる形状で
あれば、他の形状のものを形成してもよい。In this embodiment, the back surface 1 of the substrate 12 is also used.
The two ridges 16 are formed between the electrode 14a and the electrode 14b on the 2c side. However, when the light emitting device 10 is mounted on the circuit board 40, the adhesive 44 applied to the circuit board 40 serves as an electrode. Other shapes may be formed as long as they can prevent entry into the joint.
【００４２】たとえば、図８に示すように、基板１２の
裏面１２ｃ側の電極１４ａおよび電極１４ｂの間に、リ
ング（環）状の凸部１６′を形成するようにしてもよ
い。この凸部１６′は、上述の実施例と同様に、レジス
トを塗布することにより形成することができる。ただ
し、凸部１６′は、電極１４ａおよび電極１４ｂと同じ
材料で形成するようにしてもよい。For example, as shown in FIG. 8, a ring-shaped convex portion 16 'may be formed between the electrode 14a and the electrode 14b on the rear surface 12c side of the substrate 12. This convex portion 16 'can be formed by applying a resist, as in the above-described embodiment. However, the convex portion 16 'may be formed of the same material as that of the electrodes 14a and 14b.
【００４３】この図８に示すような発光装置１０を、図
７に示したような回路基板４０に実装する場合には、パ
ターン電極４２ａとパターン電極４２ｂとの間であり、
回路基板４０の表面（上面）に塗布される接着剤４４
は、電極１４ａとパターン電極４２ａとの接合部および
電極１４ｂとパターン電極４２ｂとの接合部への広がり
が阻止されるだけでなく、それらの接合部以外への広が
りも防止される。つまり、接着剤４４が放射状に広がろ
うとするのを防止することができる。When the light emitting device 10 as shown in FIG. 8 is mounted on the circuit board 40 as shown in FIG. 7, it is between the pattern electrode 42a and the pattern electrode 42b.
Adhesive 44 applied to the surface (upper surface) of the circuit board 40
Not only prevents the spread to the joint between the electrode 14a and the pattern electrode 42a and the joint between the electrode 14b and the pattern electrode 42b, but also prevents the spread to other joints. That is, it is possible to prevent the adhesive 44 from spreading radially.
【００４４】したがって、このような発光装置１０等
（他の装置等）を、回路基板４０上に密集して実装する
場合には、隣接する他の装置等の電極および他の装置等
の電極が接合されるべき回路基板４０上のパターン電極
に接着剤４４が付着するのを防止することができる。Therefore, when the light emitting devices 10 and the like (other devices and the like) are densely mounted on the circuit board 40, the electrodes of the other devices and the adjacent electrodes and the electrodes of the other devices and the like are adjacent to each other. It is possible to prevent the adhesive 44 from adhering to the pattern electrode on the circuit board 40 to be joined.
【００４５】つまり、隣接する他の装置等の実装不良も
防止することができるので、上述の実施例よりも、さら
に電子機器（製品）の歩溜まりを向上させることができ
ると言える。In other words, since it is possible to prevent mounting defects of other adjacent devices, it can be said that the yield of electronic devices (products) can be further improved as compared with the above-mentioned embodiment.
【００４６】なお、上述の実施例では、チップ部品とし
て発光装置のみを示したが、基板上に素子チップが取り
付けられ、その素子チップに接続される電極が基板の裏
面（下面）両端に配置されるものであれば、この発明を
適用できることは言うまでもない。In the above-described embodiments, only the light emitting device is shown as the chip component, but the element chip is mounted on the substrate and the electrodes connected to the element chip are arranged on both ends of the back surface (lower surface) of the substrate. It goes without saying that the present invention can be applied to any one.
【図１】この発明の一実施例を示す図解図である。FIG. 1 is an illustrative view showing one embodiment of the present invention.
【図２】図１実施例に示す発光装置の断面図である。FIG. 2 is a cross-sectional view of the light emitting device shown in FIG. 1 embodiment.
【図３】図１実施例に示す発光装置を裏面側から見た図
解図である。3 is an illustrative view of the light emitting device shown in FIG. 1 as viewed from the back surface side. FIG.
【図４】図１実施例に示す発光装置の製造工程の一部を
説明するための図解図である。FIG. 4 is an illustrative view for explaining a part of the manufacturing process for the light-emitting device shown in FIG. 1 embodiment.
【図５】図１実施例に示す発光装置の製造工程の他の一
部を説明するための図解図である。5 is an illustrative view for explaining another part of the manufacturing process of the light-emitting device shown in FIG. 1 embodiment. FIG.
【図６】図１実施例に示す発光装置の製造工程のその他
の一部を説明するための図解図である。FIG. 6 is an illustrative view for explaining another part of the manufacturing process of the light-emitting device shown in FIG. 1 embodiment.
【図７】図１実施例に示す発光装置を回路基板へ実装し
た状態の一例を示す図解図である。FIG. 7 is an illustrative view showing one example of a state in which the light emitting device shown in FIG. 1 embodiment is mounted on a circuit board.
【図８】この発明の他の発光装置の一例を示す図解図で
ある。FIG. 8 is an illustrative view showing one example of another light emitting device of the present invention.
【図９】従来のチップ部品の一例およびそのチップ部品
を回路基板に実装した状態の一例を示す図解図である。FIG. 9 is an illustrative view showing an example of a conventional chip component and an example of a state in which the chip component is mounted on a circuit board.
１０ …半導体発光装置（発光装置） １２ …基板 １４ａ，１４ｂ …電極 １６ …半導体発光素子チップ（ＬＥＤチップ） １８ …凸部 ２０ …ワイヤ ２２ …透光性樹脂 ３０ …連続体 ３２ …連続基板 ４０ …回路基板 ４２ａ、４２ｂ …パターン電極 ４４ …接着剤 ４６ …半田ペースト 10 ... Semiconductor light emitting device (light emitting device) 12 ... Substrate 14a, 14b ... Electrodes 16 ... Semiconductor light emitting element chip (LED chip) 18 ... Projection 20 ... Wire 22 ... Translucent resin 30 ... Continuum 32 ... Continuous substrate 40 ... Circuit board 42a, 42b ... Pattern electrodes 44 ... Adhesive 46 ... Solder paste
Claims (7)
記基板の裏面両端に前記素子チップに接続された２つの
電極が配置されたチップ部品において、 レジスト印刷によって前記２つの電極の間に凸部を設け
たことを特徴とする、チップ部品。1. A chip component in which an element chip is mounted on the front surface of a substrate, and two electrodes connected to the element chip are arranged at both ends of the back surface of the substrate, and a protrusion is formed between the two electrodes by resist printing. A chip part, characterized by having a section.
記基板の裏面両端に前記素子チップに接続された２つの
電極が配置されたチップ部品において、 前記電極と同じ材料によって前記２つの電極の間に凸部
を設けたことを特徴とする、チップ部品。2. A chip component in which an element chip is mounted on a front surface of a substrate, and two electrodes connected to the element chip are arranged at both ends of the back surface of the substrate, wherein the two electrodes are made of the same material as the electrode. A chip component characterized by having a convex portion provided therebetween.
ップ部品。3. The chip component according to claim 2, wherein the material is copper foil.
向に延びる凸条を含む、請求項１ないし３のいずれかに
記載のチップ部品。4. The chip component according to claim 1, wherein the protrusion includes a protrusion extending in a direction in which the electrode is not arranged.
１ないし３のいずれかに記載のチップ部品。5. The chip component according to claim 1, wherein the convex portion is formed in a ring shape.
記基板の裏面両端に前記素子チップに接続された２つの
電極が配置されたチップ部品の製造方法であって、 前記基板の裏面両端に前記２つの電極を形成し、 レジスト印刷することにより前記２つの電極間に凸部を
形成し、そして前記素子チップを前記基板の表面上に取
り付けた、チップ部品の製造方法。6. A method of manufacturing a chip component, wherein an element chip is mounted on a front surface of a substrate, and two electrodes connected to the element chip are arranged on both ends of the back surface of the substrate, wherein both ends of the back surface of the substrate are attached. A method of manufacturing a chip component, wherein the two electrodes are formed, a convex portion is formed between the two electrodes by resist printing, and the element chip is attached on the surface of the substrate.
記基板の裏面両端に前記素子チップに接続された２つの
電極が配置されたチップ部品の製造方法であって、 表面に導電性の材料を貼り付けた基板を準備し、 前記基板にエッチング処理を施して、前記基板の裏面両
端に前記２つの電極を形成するとともに、前記２つの電
極間に凸部を形成し、そして前記素子チップを前記基板
の表面上に取り付けた、チップ部品の製造方法。7. A method of manufacturing a chip component, in which an element chip is mounted on a front surface of a substrate, and two electrodes connected to the element chip are arranged at both ends of a back surface of the substrate, wherein a conductive material is provided on the front surface. Is prepared, and the substrate is subjected to an etching treatment to form the two electrodes on both ends of the back surface of the substrate, and a convex portion is formed between the two electrodes, and the element chip is formed. A method for manufacturing a chip component mounted on the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001326707A JP3851541B2 (en) | 2001-10-24 | 2001-10-24 | Chip component and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001326707A JP3851541B2 (en) | 2001-10-24 | 2001-10-24 | Chip component and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003133482A true JP2003133482A (en) | 2003-05-09 |
| JP3851541B2 JP3851541B2 (en) | 2006-11-29 |
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ID=19143047
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|---|---|---|---|
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| Country | Link |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006011522A1 (en) * | 2004-07-28 | 2006-02-02 | Sharp Kabushiki Kaisha | Light emitting module and production method therefor |
| JP2008311506A (en) * | 2007-06-15 | 2008-12-25 | Harvatek Corp | Sealing method for light emitting diode chip having high-efficiency light emission effect, and sealing structure thereof |
| KR101145209B1 (en) | 2010-04-20 | 2012-05-24 | 우리이앤엘 주식회사 | Light emitting apparatus |
-
2001
- 2001-10-24 JP JP2001326707A patent/JP3851541B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006011522A1 (en) * | 2004-07-28 | 2006-02-02 | Sharp Kabushiki Kaisha | Light emitting module and production method therefor |
| JP2008311506A (en) * | 2007-06-15 | 2008-12-25 | Harvatek Corp | Sealing method for light emitting diode chip having high-efficiency light emission effect, and sealing structure thereof |
| KR101145209B1 (en) | 2010-04-20 | 2012-05-24 | 우리이앤엘 주식회사 | Light emitting apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3851541B2 (en) | 2006-11-29 |
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