JP3188058B2 - Light emitting diode - Google Patents

Light emitting diode

Info

Publication number
JP3188058B2
JP3188058B2 JP18475093A JP18475093A JP3188058B2 JP 3188058 B2 JP3188058 B2 JP 3188058B2 JP 18475093 A JP18475093 A JP 18475093A JP 18475093 A JP18475093 A JP 18475093A JP 3188058 B2 JP3188058 B2 JP 3188058B2
Authority
JP
Japan
Prior art keywords
light emitting
wire
emitting diode
lead terminal
led
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18475093A
Other languages
Japanese (ja)
Other versions
JPH0745868A (en
Inventor
富美夫 深瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP18475093A priority Critical patent/JP3188058B2/en
Publication of JPH0745868A publication Critical patent/JPH0745868A/en
Application granted granted Critical
Publication of JP3188058B2 publication Critical patent/JP3188058B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Led Device Packages (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、樹脂モールドタイプの
発光ダイオードに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin mold type light emitting diode.

【０００２】[0002]

【従来の技術】従来の技術について、図５を参照して説
明する。図５は従来例による樹脂モールドタイプの発光
ダイオード（ＬＥＤ）の断面図である。図５に示すよう
に、ＬＥＤチップ２０が導電性ペースト２１によってリ
ード端子２２上に載置され、ＡＵ線２３によって他のリ
ード端子２４に電気的に接続されている。ここで、２５
はＬＥＤチップ２０のＰＮ接合面、２６は樹脂レンズ部
である。2. Description of the Related Art A conventional technique will be described with reference to FIG. FIG. 5 is a cross-sectional view of a conventional resin mold type light emitting diode (LED). As shown in FIG. 5, the LED chip 20 is mounted on the lead terminal 22 by the conductive paste 21 and is electrically connected to another lead terminal 24 by the AU wire 23. Where 25
Denotes a PN junction surface of the LED chip 20, and 26 denotes a resin lens portion.

【０００３】[0003]

【発明が解決しようとする課題】ところで、図５に示す
発光ダイオードは２本のリード端子２２，２４を有し、
ＬＥＤチップ２０はＡＵ線２３で接続されているため、
以下のような問題点がある。The light emitting diode shown in FIG. 5 has two lead terminals 22 and 24,
Since the LED chip 20 is connected by the AU line 23,
There are the following problems.

【０００４】即ち、 １）生産設備としてワイヤーボンダーが必要で設備投資
が大きくなる。[0004] 1) A wire bonder is required as a production facility, which increases capital investment.

【０００５】２）ＡＵ線２３でワイヤーボンディングを
行うため、発光面に電極が必要となり、その電極面で光
の吸収が生じるためＬＥＤランプの光度が低下する。2) Since wire bonding is performed with the AU wire 23, an electrode is required on the light emitting surface, and light is absorbed on the electrode surface, so that the luminous intensity of the LED lamp decreases.

【０００６】３）ＡＵ線２３の短絡による不良が発生す
る。3) A defect occurs due to a short circuit of the AU line 23.

【０００７】４）ＬＥＤランプを基板に実装する際、半
田付けの熱で樹脂レンズ部２６がエポキシ樹脂のガラス
転移点温度（約１３０°Ｃ）以上になることによりＡＵ
線２３に応力が加わり断線が生じる。4) When mounting the LED lamp on the substrate, the heat of soldering causes the resin lens portion 26 to reach a temperature higher than the glass transition point temperature (about 130 ° C.) of the epoxy resin, resulting in AU
The stress is applied to the wire 23 and the wire is broken.

【０００８】５）ＡＵ線２３とエポキシ樹脂との線膨張
係数の違い（ＡＵ線〜１．４×１０- 5 ，エポキシ樹脂
〜７×１０- 5 ）による温度サイクル試験（−２５℃〜
＋１００℃）でのＡＵ線の断線、等の問題がある。[0008] 5) the difference in the linear expansion coefficient between the AU line 23 and the epoxy resin (AU line to 1.4 × 10 - 5, an epoxy resin to 7-× 10 - 5) Temperature cycle test according to (-25 ° C. ~
(+ 100 ° C.).

【０００９】そこで、本発明の目的は、ワイヤーボンデ
ィングによる上記問題点を解消できる高信頼性の発光ダ
イオードを提供することにある。An object of the present invention is to provide a highly reliable light emitting diode which can solve the above-mentioned problems caused by wire bonding.

【００１０】[0010]

【課題を解決するための手段】前記目的を達成するため
に本発明は、ＰＮ接合面と直角となる面が主発光面であ
るＬＥＤを備えた発光ダイオードにおいて、上下面に導
電層を被着した樹脂絶縁層を、帯状にプレス加工して得
たリード端子と、該リード端子の長さ方向端部に、ＰＮ
接合面の一方が接するよう配置されたＬＥＤチップと、
該チップの電極と、前記リード端子の導電層とを電気的
に接続する導電性ペーストと、を、少なくとも備えてる
ことを特徴とする。In order to achieve the above object, according to the present invention, a plane perpendicular to a PN junction plane is a main light emitting plane.
LED on the top and bottom surfaces
Pressing the resin insulation layer with the electrical layer into a belt shape
And a lead terminal, and a PN
An LED chip arranged such that one of the joining surfaces is in contact with the LED chip,
The electrodes of the chip and the conductive layers of the lead terminals are electrically connected.
And a conductive paste to be connected to, characterized by isosamples comprise at least.

【００１１】[0011]

【作用】ＬＥＤチップのＰ層、Ｎ層を直接、リード端子
の電気的に分離された導電層に各々接着しているので、
ボンディング用のワイヤーは使用せず、従ってワイヤー
ボンダーも不要となり、材料コスト及び設備投資コスト
の低減、生産性の向上を図れる。The P layer and the N layer of the LED chip are directly bonded to the electrically separated conductive layers of the lead terminals, respectively.
No wire for bonding is used, so that a wire bonder is not required, thereby reducing material costs and equipment investment costs and improving productivity.

【００１２】また、ワイヤーを使用しないことから、従
来のワイヤーを使用することによる問題点、即ちワイヤ
ーボンディング用の電極面で光の吸収が生じるためＬＥ
Ｄランプの光度が低下する、ワイヤーの短絡による不良
が発生する、ワイヤーに応力が加わり断線が生じる、等
の問題は解消でき、高輝度、高信頼性の発光ダイオード
を実現できる。Also, since no wire is used, there is a problem with using a conventional wire, that is, since light is absorbed on the electrode surface for wire bonding, LE
Problems such as a decrease in the luminous intensity of the D lamp, a failure due to a short circuit of the wire, and a breakage due to stress applied to the wire can be solved, and a light emitting diode with high luminance and high reliability can be realized.

【００１３】[0013]

【実施例】本発明の一実施例について、図１及び図２を
参照して説明する。図１は本発明の一実施例による発光
ダイオードの断面図、図２は同じく発光ダイオードの発
光チップ部の拡大断面図である。なお、従来例と同一機
能部分には同一記号を付している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a light emitting diode according to an embodiment of the present invention, and FIG. 2 is an enlarged sectional view of a light emitting chip portion of the light emitting diode. The same symbols are given to the same functional parts as in the conventional example.

【００１４】本実施例は、図１及び図２に示すように、
リード端子１は絶縁層２を導電層３，３’によって挟ん
でいる。そして、このリード端子１の端面部分に、ＰＮ
接合面が発光面に対して直角なＬＥＤチップ４を導電性
ペースト５，５’によって接着固定する。６，７はそれ
ぞれ、ＬＥＤチップのＮ層およびＰ層、８はＰＮ層であ
る。In this embodiment, as shown in FIGS. 1 and 2,
The lead terminal 1 sandwiches the insulating layer 2 between the conductive layers 3 and 3 '. PN is attached to the end face of the lead terminal 1.
The LED chip 4 whose bonding surface is perpendicular to the light-emitting surface is bonded and fixed with conductive pastes 5 and 5 '. Reference numerals 6 and 7 denote N and P layers of the LED chip, respectively, and 8 denotes a PN layer.

【００１５】上記構造によれば、従来の発光ダイオード
のようにボンディング用のワイヤーは使用しないので、
ワイヤーボンダーも不要となり、材料コスト及び設備投
資コストの低減、生産性の向上を図れる。According to the above structure, a wire for bonding is not used unlike a conventional light emitting diode.
The need for a wire bonder is also eliminated, reducing material costs and capital investment costs, and improving productivity.

【００１６】また、ワイヤーを使用しないことから、従
来のワイヤーを使用することによる問題点、即ちワイヤ
ーボンディング用の電極面で光の吸収が生じるためＬＥ
Ｄランプの光度が低下する、ワイヤーの短絡による不良
が発生する、ワイヤーに応力が加わり断線が生じる、等
の問題は解消でき、高輝度、高信頼性の発光ダイオード
を実現できる。Also, since no wire is used, there is a problem with using a conventional wire, that is, since light is absorbed on the electrode surface for wire bonding, LE
Problems such as a decrease in the luminous intensity of the D lamp, a failure due to a short circuit of the wire, and a breakage due to stress applied to the wire can be solved, and a light emitting diode with high luminance and high reliability can be realized.

【００１７】また、上記リード端子１の製造方法は、プ
ラスチック等の絶縁体の両側にＣｕまたはＦｅ等の金属
を圧接（または接着）により帯状にし、それをプレス加
工（打ち抜き加工）して得る。このように、従来と同様
の工程なので、大幅な工程変更なしに生産できる。In the method of manufacturing the lead terminal 1, a metal such as Cu or Fe is formed on both sides of an insulator such as a plastic by pressing (or bonding) and pressed (punched). As described above, since the process is the same as the conventional process, the production can be performed without a significant change in the process.

【００１８】図３は本発明の他の実施例による発光ダイ
オードの断面図である。本実施例の構造は図１及び図２
と同等であるが、２チップをリード端子に搭載した点の
みが異なっている。図３に示すように、リード端子９は
絶縁層１０，１１を導電層１２，１３，１４で挟んだ構
造である。この導電層１２，１３及び１３，１４それぞ
れに対してＬＥＤチップ１５，１６を導電性ペーストで
接続固定している。FIG. 3 is a sectional view of a light emitting diode according to another embodiment of the present invention. FIGS. 1 and 2 show the structure of this embodiment.
However, the only difference is that two chips are mounted on the lead terminals. As shown in FIG. 3, the lead terminal 9 has a structure in which insulating layers 10 and 11 are sandwiched between conductive layers 12, 13 and 14. The LED chips 15 and 16 are connected and fixed to the conductive layers 12 and 13 and 13 and 14 respectively with a conductive paste.

【００１９】本実施例によっても図１及び図２と同等の
効果を得ることができる。According to this embodiment, the same effects as those of FIGS. 1 and 2 can be obtained.

【００２０】図４は本発明のさらに他の実施例である。
本実施例は図１の実施例に、樹脂反射面１７を設けた点
が異なっている。上記構造をとることによって、ＰＮ接
合面と直角方向に出る光を上部（ＬＥＤランプ発光面）
に導くことにより、さらに高輝度化を図れる。なお、本
構造の樹脂反射面１７を図３の２チップタイプに応用で
きることは言うまでもない。FIG. 4 shows still another embodiment of the present invention.
This embodiment is different from the embodiment of FIG. 1 in that a resin reflecting surface 17 is provided. By taking the above structure, light emitted in the direction perpendicular to the PN junction surface is directed to the upper part (LED lamp light emitting surface).
, The luminance can be further increased. Needless to say, the resin reflection surface 17 of this structure can be applied to the two-chip type shown in FIG.

【００２１】[0021]

【発明の効果】以上説明したように、本発明の発光ダイ
オードは、ボンディング用のワイヤーは使用せず、従っ
てワイヤーボンダーも不要となり、材料コスト及び設備
投資コストの低減、生産性の向上を図れる。As described above, the light emitting diode of the present invention does not use a wire for bonding, and therefore does not require a wire bonder, thereby reducing material costs and equipment investment costs and improving productivity.

【００２２】また、ワイヤーを使用しないことから、従
来のワイヤーを使用することによる問題点、即ちワイヤ
ーボンディング用の電極面で光の吸収が生じるためＬＥ
Ｄランプの光度が低下する、ワイヤーの短絡による不良
が発生する、ワイヤーに応力が加わり断線が生じる、等
の問題は解消でき、高輝度、高信頼性の発光ダイオード
を実現できる。Also, since no wire is used, there is a problem with using a conventional wire, that is, since light is absorbed on the electrode surface for wire bonding, LE
Problems such as a decrease in the luminous intensity of the D lamp, a failure due to a short circuit of the wire, and a breakage due to stress applied to the wire can be solved, and a light emitting diode with high luminance and high reliability can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例による発光ダイオードの断面
図である。FIG. 1 is a sectional view of a light emitting diode according to an embodiment of the present invention.

【図２】本発明の一実施例によるＬＥＤチップの拡大断
面図である。FIG. 2 is an enlarged sectional view of an LED chip according to an embodiment of the present invention.

【図３】本発明の他の実施例による発光ダイオードの断
面図である。FIG. 3 is a cross-sectional view of a light emitting diode according to another embodiment of the present invention.

【図４】本発明の更に他の実施例による発光ダイオード
の断面図である。FIG. 4 is a sectional view of a light emitting diode according to another embodiment of the present invention.

【図５】従来例による発光ダイオードの断面図である。FIG. 5 is a sectional view of a light emitting diode according to a conventional example.

【符号の説明】[Explanation of symbols]

１ リード端子 ２ 絶縁層 ３，３’導電層 ４ ＬＥＤチップ ６ Ｎ層 ７ Ｐ層 DESCRIPTION OF SYMBOLS 1 Lead terminal 2 Insulating layer 3, 3 'conductive layer 4 LED chip 6 N layer 7 P layer

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 ＰＮ接合面と直角となる面が主発光面で
あるＬＥＤを備えた発光ダイオードにおいて、 上下面に導電層を被着した樹脂絶縁層を、帯状にプレス
加工して得たリード端子と、 該リード端子の長さ方向端部に、ＰＮ接合面の一方が接
するよう配置されたＬＥＤチップと、 該チップの電極と、前記リード端子の導電層とを電気的
に接続する導電性ペーストと、を、少なくとも備えて る
ことを特徴とする発光ダイオード。1. A main light emitting surface is a surface perpendicular to a PN junction surface.
In a light-emitting diode equipped with a certain LED, a resin insulating layer with conductive layers attached on the upper and lower surfaces is pressed in a belt shape.
One of the PN junction surfaces is in contact with the lead terminal obtained by processing and the longitudinal end of the lead terminal.
An LED chip, an electrode of the chip , and a conductive layer of the lead terminal.
And a conductive paste to be connected to, light emitting diodes, wherein isosamples comprise at least.
JP18475093A 1993-07-27 1993-07-27 Light emitting diode Expired - Fee Related JP3188058B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18475093A JP3188058B2 (en) 1993-07-27 1993-07-27 Light emitting diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18475093A JP3188058B2 (en) 1993-07-27 1993-07-27 Light emitting diode

Publications (2)

Publication Number Publication Date
JPH0745868A JPH0745868A (en) 1995-02-14
JP3188058B2 true JP3188058B2 (en) 2001-07-16

Family

ID=16158693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18475093A Expired - Fee Related JP3188058B2 (en) 1993-07-27 1993-07-27 Light emitting diode

Country Status (1)

Country Link
JP (1) JP3188058B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2007018098A1 (en) 2005-08-05 2009-02-19 オリンパスメディカルシステムズ株式会社 Light emitting unit
JP2007214472A (en) * 2006-02-13 2007-08-23 Matsushita Electric Ind Co Ltd Edgelight and method of manufacturing same

Also Published As

Publication number Publication date
JPH0745868A (en) 1995-02-14

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