JP3053316U - 集積回路が誤ってテストモードオペレーションに入ることを防ぐための集積回路内蔵装置 - Google Patents

集積回路が誤ってテストモードオペレーションに入ることを防ぐための集積回路内蔵装置

Info

Publication number
JP3053316U
JP3053316U JP1998003042U JP304298U JP3053316U JP 3053316 U JP3053316 U JP 3053316U JP 1998003042 U JP1998003042 U JP 1998003042U JP 304298 U JP304298 U JP 304298U JP 3053316 U JP3053316 U JP 3053316U
Authority
JP
Japan
Prior art keywords
signal
integrated circuit
test mode
test
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1998003042U
Other languages
English (en)
Japanese (ja)
Inventor
ジェイソン・チェン
バオ‐シァン・サン
ヘンリー・ファン
Original Assignee
ホルテック・マイクロエレクトロニクス・インク
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/843,786 external-priority patent/US6526536B1/en
Application filed by ホルテック・マイクロエレクトロニクス・インク filed Critical ホルテック・マイクロエレクトロニクス・インク
Application granted granted Critical
Publication of JP3053316U publication Critical patent/JP3053316U/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP1998003042U 1997-04-21 1998-04-17 集積回路が誤ってテストモードオペレーションに入ることを防ぐための集積回路内蔵装置 Expired - Lifetime JP3053316U (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/843,786 US6526536B1 (en) 1996-12-12 1997-04-21 Apparatus within an integrated circuit for preventing the integrated circuit from erroneously entering a test mode operation
US08/843,786 1997-04-21

Publications (1)

Publication Number Publication Date
JP3053316U true JP3053316U (ja) 1998-10-27

Family

ID=25291010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1998003042U Expired - Lifetime JP3053316U (ja) 1997-04-21 1998-04-17 集積回路が誤ってテストモードオペレーションに入ることを防ぐための集積回路内蔵装置

Country Status (5)

Country Link
JP (1) JP3053316U (zh)
KR (1) KR19980065071U (zh)
CN (1) CN1125346C (zh)
DE (1) DE29807139U1 (zh)
GB (1) GB2324613A (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001256711A (ja) 2000-03-14 2001-09-21 Alps Electric Co Ltd Ｆｄｄ装置用ｉｃのテストモード切換方法およびテストモード切換装置、ｆｄｄ装置
US7574638B2 (en) * 2005-02-03 2009-08-11 Samsung Electronics Co., Ltd. Semiconductor device tested using minimum pins and methods of testing the same
CN102455962A (zh) * 2010-10-29 2012-05-16 上海三旗通信科技股份有限公司 一种通过电流检测自动启动程序测试的方法
CN104678284B (zh) * 2013-12-03 2017-11-14 北京中电华大电子设计有限责任公司 一种提高芯片健壮性的新型测试控制电路和方法
CN105759190B (zh) * 2016-02-23 2018-09-28 工业和信息化部电子第五研究所 Mos管参数退化的检测电路
CN106918775A (zh) * 2017-04-21 2017-07-04 成都锐成芯微科技股份有限公司 芯片测试模式的进入方法
CN109406986A (zh) * 2018-10-11 2019-03-01 深圳忆联信息系统有限公司 测试模式复位控制方法、装置、计算机设备和存储介质
CN111175645B (zh) * 2020-03-12 2021-03-16 杭州芯耘光电科技有限公司 一种测试电路及其构成的集成电路和测试设定方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077738A (en) * 1988-12-30 1991-12-31 Intel Corporation Test mode enable scheme for memory
US5072138A (en) * 1990-08-17 1991-12-10 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequential clocked access codes for test mode entry
US5377200A (en) * 1992-08-27 1994-12-27 Advanced Micro Devices, Inc. Power saving feature for components having built-in testing logic

Also Published As

Publication number Publication date
DE29807139U1 (de) 1998-08-06
KR19980065071U (ko) 1998-11-25
CN1197213A (zh) 1998-10-28
GB2324613A (en) 1998-10-28
CN1125346C (zh) 2003-10-22
GB9807859D0 (en) 1998-06-10

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