JP2973958B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a gettering technique for removing impurities such as heavy metals and crystal defects that deteriorate device characteristics in an element region from the element region.

[0002]

2. Description of the Related Art In the manufacturing process of a semiconductor device, if impurities such as heavy metals such as Fe and Cu are present in a device operation region, device characteristics are deteriorated. Therefore, there is a gettering technique for removing these impurities. In particular, as a gettering method in which the distance between the device element region on the wafer surface and the gettering site is short and the gettering speed is increased, a silicon oxide film is formed by oxidation on a wafer exposed portion around the element to be patterned on the semiconductor wafer. There is a technique of performing gettering on this silicon oxide film (Japanese Patent Laid-Open No. 7-201976). In this technique, by selectively oxidizing a wafer exposed portion around a device element, a portion between an oxidized portion and a non-oxidized wafer region is removed.
That is, stress is applied between the regions of the silicon substrate, and the impurities which become gettering sites and degrade the device element can be removed from the device element area to the wafer exposed portion around the element.

[0003]

However, in this conventional technique, a silicon oxide film is formed by uniformly oxidizing a part or the whole of an exposed portion of a wafer around a device element. And the gettering ability is small.
This is because the strain field serving as a gettering site is particularly large at the edge of the silicon oxide film, but only partially or entirely oxidizing the exposed portion of the wafer around the device element, the end of the silicon oxide film is not easily obtained. Is insufficient.

An object of the present invention is to provide a method of manufacturing a semiconductor device having a large gettering ability by enlarging a region at an end portion of a silicon oxide film to increase a stress applied to a gettering region.

[0005]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming various elements on a semiconductor wafer to manufacture the semiconductor device; A plurality of stripe-shaped silicon oxide films arranged in parallel are formed. Alternatively, a plurality of island-shaped silicon oxide films separated from each other may be formed in a peripheral region of the element formation region of the semiconductor wafer. Here, the distance between the element formation region and the peripheral region of the element formation region is equal to or less than the thickness of the defect-free layer in the case of a wafer having a defect-free layer, and the thickness of the epitaxial layer in the case of an epitaxial wafer. Hereinafter, in the case of other wafers, the thickness is preferably equal to or less than the thickness of the wafer. Further, after forming the silicon oxide film in the peripheral region, it is preferable that the cooling rate of the heat treatment and the temperature of the pumping furnace be 3 ° C./min or less and 700 ° C. to 400 ° C., respectively. Further, the element isolation oxide film formed in the element formation region is preferably formed in a stripe shape so that two or more irregularities are present at the interface with the semiconductor wafer.

[0006]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of steps. First, as shown in FIG.
The surface of the silicon wafer 1 is thermally oxidized in an oxidizing atmosphere of water vapor and oxygen to form a silicon oxide film 2 having a thickness of 200 ° on the entire surface of the silicon wafer 1. Next, a 2000 nm thick silicon nitride film 3 is formed on the entire surface by chemical vapor deposition. In the following figures, 4 denotes an element forming region, 5 denotes an element non-forming region, and here, a scribe line region. Next, as shown in FIG. 1B, the silicon nitride film 3 is selectively etched using a photolithography technique, and an opening 6 is formed in the element forming region 4 and an opening 7 is formed in the scribe line region 5. Form each. At this time, in the scribe line region 5, as shown in FIG. 2, the openings 7 are formed in a plurality of narrow grooves (stripes) which are arranged in the width direction and surround the element forming region 4. Next, as shown in FIG. 1C, thermal silicon oxide films 8 and 9 each having a thickness of 3000.degree. Are formed in regions of the silicon oxide film 2 exposed in the openings 6 and 7, respectively. The silicon oxide films 8 and 9 are element isolation silicon oxide films 8 in the element formation region 4 and are formed as stripe-shaped silicon oxide films 9 in the scribe line region 5. Thermal oxidation for forming these thermally oxidized silicon films 8 and 9 is performed by atmospheric pressure oxidation at a temperature of 1000 ° C. in an oxidizing atmosphere of water vapor and oxygen. As a result, a strain field 10 due to stress is present at the interface between the silicon oxide films 8 and 9 and the silicon wafer 1 and serves as a gettering site.

Here, the size of the stripe of the silicon oxide film 9 in the scribe line region 5 will be described with reference to FIG. In the first embodiment, the size of the stripe of the silicon oxide film 9 is such that the width of the silicon oxide film 3 is 0.5 μm, the width of the space 11 between the silicon oxide films 3 is 0.9 μm, The width of one pitch consisting of the width of the silicon film 9 and the width of one space 11 was 1.4 μm. The direction of the stripe was parallel to the length direction of the scribe line. The element formation region 4 is 8 m long
m, 8 mm wide square area, and scribe line area 5
Is 1 mm both vertically and horizontally. There are 712 striped silicon oxide films 9 on one scribe line region 5, and the length (margin) from the element formation region to the silicon oxide film 9 on the nearest scribe line is 2.3 μm.

The operation of the semiconductor device of this embodiment will be described with reference to FIG.
This will be described in detail with reference to FIG. FIG. 3A is a cross-sectional view of the semiconductor device according to the embodiment of the present invention shown in FIGS. 1 and 2, and FIG. 3B is a cross-sectional view of a conventional semiconductor device. FIG. 3 (a)
At the interface between the silicon wafer 1 and the silicon oxide film 9 arranged in stripes in the scribe line region 5, a stress field 10 due to stress exists. The strain field 10 serves as a gettering site for gettering impurities M such as heavy metals in the element region 4. By the heat treatment performed in the element formation process, the impurities M such as heavy metals also diffuse to the gettering sites 10. If the strain field is a gettering site, its gettering ability depends on the magnitude of the strain field and the magnitude of the stress of the strain field. Then, the magnitude of the strain field becomes large at the end of the silicon oxide film. In the configuration of the present embodiment, the silicon oxide film 9
Are formed in a stripe shape, so that there are a large number of end portions of the silicon oxide film corresponding to the number of stripes.
Many large strain fields 10 will be present. On the other hand, in the case where the silicon oxide film 9 is formed on almost the entire surface of the region 5 other than the element region as shown in FIG.
Number is also reduced. Therefore, the structure of the present embodiment having a large number of large strain fields has a higher gettering ability than the conventional structure. Thus, in the present embodiment, it becomes easy to reduce heavy metal contamination in the device active region of the semiconductor wafer.

FIG. 4 is a plan view of a second embodiment of the present invention. Here, by forming the silicon nitride film 3 formed in the scribe line region into a stitch shape, the stripe shape of the silicon oxide film 9 formed thereby is separated into an island shape in the length direction. . For example, the size of the stripe to which the silicon oxide film 3 of each island of the scribe line region 5 is connected is such that the width of the island 9 of the silicon oxide film is 0.5 μm and the width of the space 11 between these islands is 0.9 μm. The width of one pitch consisting of the width of the island 9 of the silicon oxide film and the width of one space 11 was 1.4 μm. The island 9
Is 499 μm in the length direction, and the interval between the scribe line regions 5 other than the element region in the length direction of the island 9 is 1
μm, and the pitch in the length direction of the island 9 is 500 μm.
m. The length direction of the island 9 is parallel to the length direction of the scribe line region 5. The element forming area 4 is a square frame area of 8 mm in height and 8 mm in width, and the width of the scribe line area 5 is 1 mm in both length and width. Further, there are 712 stripes to which the silicon oxide film of the island 9 is connected on one scribe line region, and the length (margin) from the element formation region 4 to the silicon oxide film 9 in the closest scribe line region is 2 0.3 μm. When a stripe of the silicon oxide film is formed on the silicon wafer 1 by the island-shaped silicon nitride film, the end of the silicon oxide film is more sharp than in the first embodiment in which the silicon oxide film of the continuous stripe is formed. Are also generated in the length direction, and the distortion field is increased by the number of the end portions, so that the gettering ability is high.

Here, in the semiconductor device shown in FIG. 1 and FIG. 2, gettering of each wafer formed by changing the distance from the element region of the region where the silicon oxide film 9 arranged in stripes of the scribe line region 5 is formed. FIG. 5 shows the result of estimating the situation from the pn junction leakage current measurement. Semiconductor wafer IG (Intrinsic-Gettering), EG (Extr
In order to compare the distance from the element region of the gettering site of an insic-gettering or an epitaxial wafer with the distance from the element region of the region where the silicon oxide film arranged in stripes is formed, the distance from the element region is 30 μm in thickness. In the case of using a wafer having a defect-free layer of a thickness of 20 μm, using a wafer having an epitaxial layer of 20 μm in thickness, and measuring a pn junction leak current in the case of using a 675 μm-thick PBS (Poly-Back-Seal) wafer. went. The method of forming the silicon oxide films arranged in stripes is the same as in the first embodiment. Then, an n-diffusion layer having a cell size of 7 mm long and 7 mm wide is formed as a p-well over the entire surface of the wafer by implanting B ⁺ at a dose of 10 ¹³ cm ⁻² and an energy of 300 keV as shown in FIG. A region is formed by P ⁺ implantation at a dose of 10 ¹⁴ cm ^-2 and energy of 40 keV, and the contact portion in the region is implanted with P ⁺ implantation at a dose of 10 ¹⁴ cm ^-2 and an energy of 70 keV. The leakage current to the back side of the wafer at a bias voltage of 5 V was measured. The distance between the stripe-shaped silicon oxide films and the element formation region was the distance from the end of the n-diffusion layer to the silicon oxide film closest to the n-diffusion layer in the stripe-shaped silicon oxide film. The heat treatment for diffusing impurities in the wafer was equivalent to a DRAM manufacturing process.

FIG. 5A shows the result when a wafer having a defect-free layer is used, FIG. 5B shows the result when an epitaxial wafer is used, and FIG. 5C shows the result when a PBS wafer is used. ). As can be seen from FIG. 5, the distance between the silicon oxide film arranged in stripes and the element formation region is less than the thickness of the defect-free layer in FIG. 5A, less than the thickness of the epitaxial layer in FIG. In (c), the value of the pn junction leakage current was significantly reduced when the thickness was equal to or less than the thickness of the wafer. From this result, it is found that the distance between the silicon oxide film arranged in a stripe and the element formation region is equal to or less than the distance from the element formation region to the IG, EG, or the gettering site of the epitaxial wafer. It can be seen that gettering to the silicon oxide films arranged in stripes is effective. This is because the distance from the element formation area to the stripe-shaped silicon oxide film formation region is shorter than the distance from the element formation region requiring gettering to the gettering site existing on the wafer, and This is because it is advantageous for diffusion of impurities such as heavy metals necessary for the ring.

On the other hand, after forming a silicon oxide film arranged in stripes in the scribe line region, the cooling rate of the heat treatment for gettering is set to 3 ° C./min or less, and the gettering condition of each wafer formed by changing the outlet temperature is set. FIG. 6 shows the result estimated from the measurement of the pn junction leakage current. Here, the size of the method of forming the silicon oxide films arranged in a stripe on the semiconductor wafer is the same as that of the first embodiment of the present invention. The pn junction formation and measurement conditions for measuring the pn junction leakage current are the same as the measurement in FIG. Here, the heat treatment for diffusing the impurities into the wafer was performed in the DRAM manufacturing process, and the gettering was performed by changing the furnace temperature in the final heat treatment process from 900 ° C. to 300 ° C. in these processes. In the final step of the heat treatment, the furnace was heated at 900 ° C. for 10 minutes at 900 ° C. and then discharged at each temperature. A PBS wafer was used as the wafer. As can be seen from the measurement results in FIG. 6, the pn junction leak current is small when the furnace temperature is 700 ° C. to 400 ° C. From this, the cooling rate of the heat treatment for gettering is 3 ° C./min or less, and the furnace temperature is 700 ° C. ℃ -40
It is understood that the temperature of 0 ° C. is effective for gettering impurities in the element formation region to the silicon oxide film arranged in stripes.

Next, a third embodiment of the present invention will be described with reference to FIGS. In this embodiment, the case where the interface between the element isolation silicon oxide film and the semiconductor wafer is formed in the element formation region as a shape having unevenness by photoetching at the same time as the formation of the silicon oxide film arranged in stripes in the scribe line region. The gettering situation of the wafer in the case of no, is inferred from the pn junction leakage current measurement. FIG. 7 is a cross-sectional view showing a method of forming an element isolation region and a gettering region in the order of processes when an interface between an element isolation silicon oxide film and a semiconductor wafer is formed by photoetching into a shape having irregularities. In this embodiment, the size of the method of forming the silicon oxide films arranged in stripes in the scribe line region in the exposed portion of the wafer around the element formation region on the semiconductor wafer is the same as in the first embodiment of the present invention. . Further, the formation of the element isolation silicon oxide film in the element formation region is the same as that of the first embodiment of the present invention, but here, two or more irregularities are formed at the interface between the element isolation silicon oxide film and the semiconductor wafer. Some were not, and some were made with many irregularities.

FIG. 7 shows a method of forming a silicon oxide film arranged in stripes in the scribe line region and a device isolation silicon oxide film having a large number of irregularities at the interface with the semiconductor wafer in the device formation region. First, FIG.
1A, the surface of a silicon wafer 1 is thermally oxidized in an oxidizing atmosphere of water vapor and oxygen, and a silicon oxide film 2 having a thickness of 200 ° is formed on the entire surface of the silicon wafer 1. Next, a 2000 nm thick silicon nitride film 3 is formed on the entire surface by chemical vapor deposition. Next, as shown in FIG. 7B, the silicon nitride film 3 is selectively etched using a photolithography technique, and an opening 6 is formed in the element forming region 4 and an opening 7 is formed in the scribe line region 5. A plurality of stripes are formed. Thereafter, as shown in FIG. 7C, an oxidation process is performed to form an element isolation silicon oxide film 8 in the element formation region 4 and a silicon oxide film 9 in the scribe line region. Thereafter, the silicon nitride film 3 is removed as shown in FIG.

Here, the shape of the element isolation silicon oxide film 8 is such that the stripe size is such that the width of the silicon oxide film 9 is 0.5 μm and the width of the space 11 between them is 0.9 μm.
μm, the width of one silicon nitride film 9 and one space 1
The width of one pitch including the width of 1 was set to 1.4 μm. The direction of the stripe was parallel to the length direction of the scribe line region 5. The element formation region 4 is the same as in the first embodiment. The measurement conditions for forming the pn junction for measuring the pn junction leakage current are the same as those in FIG.
The heat treatment for diffusing impurities in the wafer was performed in a DRAM manufacturing process. Further, in the final step of the heat treatment, a PBS wafer was used as a wafer which was heated at 900 ° C. for 10 minutes after nitrogen treatment at 900 ° C. for 10 minutes. FIG. 8 shows the measurement results. The figure shows two or more wafers without irregularities at the interface between the element isolation silicon oxide film and the semiconductor wafer,
The pn junction leakage current of each of a large number of uneven wafers is shown for comparison.

Thus, a wafer having a large number of irregularities at the interface between the element isolation silicon oxide film 8 and the silicon wafer 1 has a higher p than a wafer having no two or more irregularities.
It can be seen that the n-junction leakage current is small. from this result,
It can be seen that forming a large number of irregularities at the interface between the element isolation silicon oxide film 8 and the silicon wafer 1 is effective for gettering impurities in the element formation region 4. this is,
If the interface between the element isolation silicon oxide film 8 and the silicon wafer 1 has two or more irregularities, the number of strain fields 10 is increased as compared with the case where there is only one irregularity. Therefore, when the diffusion length of an impurity such as a heavy metal is insufficient in gettering from the silicon oxide film in the surrounding region, the impurity such as the heavy metal is gettered by unevenness at an interface between the element isolation silicon oxide film and the silicon wafer. This is because

[0017]

As described above, according to the present invention, a stripe-shaped or island-shaped silicon oxide film is formed in a peripheral region of an element formation region, and an interface between the silicon oxide film and the semiconductor wafer is used as a gettering site. By using such a structure, the end portion of the silicon oxide film where a large strain field effective as a gettering side is formed can be enlarged, whereby the gettering site can be enlarged and the gettering ability can be increased. Further, according to the present invention, since a silicon oxide film as a gettering site can be formed simultaneously with formation of an element isolation oxide film in an element formation region, the gettering can be performed without increasing the number of manufacturing steps of a conventional semiconductor device. The ring effect can be enhanced. further,
According to the present invention, since the gettering site can be formed on the surface side of the semiconductor wafer, the gettering region can be formed in the vicinity of the element forming region, and the getter which is exposed to impurities such as heavy metals due to contamination from the surface side of the semiconductor frequency. There is also an effect that the ring effect can be increased and the manufacturing yield and throughput of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing method according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a plan view of a silicon oxide film in the semiconductor wafer of the embodiment of FIG.

FIG. 3 is a cross-sectional view for explaining the operation of the present invention.

FIG. 4 is a plan view of a silicon oxide film in a semiconductor wafer according to a second embodiment of the present invention.

FIG. 5 is a diagram showing characteristics of reverse bias voltage-pn junction leak current when the present invention is applied to a wafer having a defect-free layer, an epitaxial wafer, and a PBS wafer.

FIG. 6 is a graph showing characteristics of a reverse bias voltage-pn junction leakage current when the cooling rate of the heat treatment of the semiconductor wafer in the present invention is set to 3 ° C./min or less and the outlet temperature is changed.

FIG. 7 is a cross-sectional view showing a third embodiment of the present invention in the order of manufacturing steps.

FIG. 8 is a graph showing the relationship between the reverse bias voltage and the pn junction leakage current when the interface between the element isolation silicon oxide film and the semiconductor wafer is formed as a shape having irregularities in the third embodiment of the present invention; FIG.

[Explanation of symbols]

 Reference Signs List 1 silicon wafer 2 silicon oxide film 3 silicon nitride film 4 element formation region 5 scribe line region 6 opening 7 opening 8 silicon oxide film (element isolation oxide film) 9 silicon oxide film (gettering region) 10 strain field (gettering) Site) 11 space M impurity

Claims (5)

(57) [Claims] In a part of a process of manufacturing a semiconductor device by forming various elements on a semiconductor wafer, a plurality of stripe-shaped silicon oxide films arranged in parallel around an element formation region of the semiconductor wafer. Forming a semiconductor device. 2. A method for manufacturing a semiconductor device by forming various elements on a semiconductor wafer, comprising: forming a plurality of island-shaped silicon oxide films separated from each other in a peripheral region of an element forming region of the semiconductor wafer; Forming a semiconductor device. 3. A distance between the element formation region and a peripheral region of the element formation region is equal to or less than the thickness of the defect-free layer in the case of a wafer having a defect-free layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness is equal to or less than the thickness, and in the case of another wafer, the thickness is equal to or less than the thickness of the wafer. 4. After forming a silicon oxide film in the peripheral region, the cooling rate of the heat treatment and the temperature of the discharge furnace are each set at 3 ° C. /
4. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is 700 ° C. to 400 ° C. or less. 5. The semiconductor device according to claim 1, wherein the element isolation oxide film formed in the element formation region is formed in a stripe shape so that two or more irregularities are present at the interface with the semiconductor wafer. Production method.