JPH0464227A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the yield of an element by forming a thermal oxide film, in which all of a glass layer containing impurities are removed, or a thermal oxide film, in which one part of the glass layer containing impurities is taken off, as one part of a passivation film on the surface of a substrate. CONSTITUTION:A device, in which a P-type impurity layer 2 as a base region is formed previously on the surface of an N-type Si substrate l while using an oxide film 14 as a mask, is prepared, a window is bored to one part of the oxide film 4, and a phosphate glass film 5 is deposited on the whole surface through a vapor phase chemical reaction method, and an emitter region 3 is formed. The region 3 is diffused up to specified depth while a thermal oxide film 8 is grown on the interface of the emitter region and the phosphate glass film 5. The whole is thermally treated in an N2 gas atmosphere containing H2. All of the phosphate glass film 5 is removed by a hydrofluoric acid group etchant. A window hole for an electrode contact is bored to one part of the upper oxide film 4 on the region 2 and the region 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, particularly a bipolar transistor, and a method for manufacturing the same, and mainly relates to the formation of a semiconductor region by diffusion onto the surface of a silicon substrate and the passivation thereon. Concerning techniques for the formation of membranes.

[Conventional technology]

Regarding the technology for manufacturing semiconductor devices such as small signal npn) transistors with planar specifications,
[Latest LSI Process Technology JP, 156, published July 3
157 as the form of impurity diffusion.

According to this document, as a process for forming an n-type emitter region by diffusing phosphorus onto the surface of a silicon wafer, a plurality of wafers are housed in a process tube, and phosphorus oxychloride (POc63) is used as a processing gas in the tube. ) is supplied to the wafer using a carrier gas of N2 or 02.
(phosphorus) deposition and diffusion. After that, the processed wafer is taken out from the deposition furnace (first
(See Figures 4 to 4) All or part of the phosphorus glass (glass containing phosphorus oxide) layer 5 formed on the surface of the wafer 1 is removed using a hydrofluoric acid (HF) based etchant.

After that, it is placed in a heat treatment furnace with an oxidizing atmosphere and treated at a predetermined temperature and time to form a phosphorus diffusion layer 3 and to form a thermal oxide film 4 or a thermal oxide film containing phosphorus on its surface. form a layer.

After that, a part of the oxide film on the surface is opened using a photoresist process to form holes for electrode contact in the emitter and heath portions, and H2 Heat treatment is performed in a gaseous N2 gas atmosphere, and characteristics such as current amplification factor (hFE) are examined.

Incidentally, FIG. 1 is a process flowchart in such a conventional technique, and FIGS. 2 to 4 are sectional views of elements corresponding to the main steps of this process. That is,
FIG. 2 is a cross-sectional view of each element after phosphorus deposition, FIG. 3 after phosphorus glass removal, and FIG. 4 after diffusion (oxidation).

[Problem to be solved by the invention]

The conventional method described above has the following problems.

+J 7 In each heat treatment of deposition, diffusion, and annealing, it is necessary to charge the wafer to a heat treatment jig for each treatment, pass it through a processing furnace, and then take it out of the furnace after the treatment and perform a discharge operation. Therefore, over the entire process, the number of work steps increases and the number of times of handling increases, which tends to cause foreign matter to adhere to the wafer and also cause scratches.

The present invention aims to solve the above-mentioned problems by reducing the number of wafer charging and discharging operations, that is, the number of wafer handling operations.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a thermal oxide film formed by removing all of the impurity-containing glass layer once formed on one main surface of a semiconductor substrate, or by removing a part of the impurity-containing glass layer. The present invention relates to a semiconductor device characterized by having a thermal oxide film as part of a passivation film.

The present invention also provides phosphorus deposition on one main surface of a semiconductor substrate in the manufacturing process of a bipolar transistor.
Relating to a method for manufacturing a semiconductor device in which an emitter region is formed by continuous diffusion treatment and oxidation, a phosphor glass layer and a thermal oxide film are formed thereon, and the thermal oxide film from which the phosphor glass layer is removed is used as a passivation film. It is something.

The present invention further provides a bipolar transistor manufacturing process in which an emitter region is formed on one main surface of a semiconductor substrate by successive processes of phosphorus deposition, diffusion treatment, and oxidation, and at the same time, a phosphorus glass layer and a thermal oxide film are formed thereon. The present invention also relates to a method of manufacturing a semiconductor device in which a part of the phosphorus glass layer is removed and a thermal oxide film containing phosphorus glass is used as a passivation film.

[Effect]

According to the above method, the heat treatments of phosphorus deposition, diffusion, and annealing are performed continuously in one furnace, eliminating the need to perform wafer charging and discharging operations each time, and reducing the number of wafer handling operations compared to the conventional one. Therefore, the number of work steps associated with this decreases, and the potential for foreign matter to attach to the wafer or cause damage to the wafer is also reduced to 1/3.

Further, these treatments are also performed in the same furnace, making it possible to change and adjust the temperature and gas atmosphere according to the respective treatment conditions in a treatment sequence, which is effective in improving the quality of the product.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 5 to 8.

Of these, FIG. 5 shows a process flowchart from emitter region formation to characteristic inspection after contact photoresist processing, and FIGS. 6 to 8 are cross-sectional views corresponding to the main steps of the above process.

(a) Phosphorus deposition: As shown in Figure 6, n-type S
Prepare an i-substrate (wafer) on which a p-type impurity layer 2, which will serve as a base region, has already been formed using an oxide film 4 as a mask on one main surface of the i-substrate (wafer). Then, a phosphorus glass film 5 is deposited over the entire surface by the following vapor phase chemical reaction method using phosphorus oxychloride (PO(1!3)) as an impurity source to form an emitter region 3.

(b) Diffusion (oxidation): As shown in FIG. 7, the emitter region 3 is diffused to a predetermined depth (approximately 1 μm) by oxidation treatment, and the emitter region and phosphorus glass W! A thermal oxide film 8 of about 5,000 layers is grown on the interface of 5. Through this treatment, the thickness of the phosphorus glass film 4 and the concentration of phosphorus therein are reduced and the previous state is maintained.

(C) Annealing: Further at 470°C, N2 containing H2
Heat treatment (annealing) is performed in a gas atmosphere.

(d) Removal of phosphorus glass: As shown in FIG. 8, the entire phosphorus glass film 5 is removed using a hydrofluoric acid (HF) based etchant.

Alternatively, etching is performed so as to leave a portion of the phosphor glass film 5.

(e) Contact photoetching: Although not shown, a window hole for an electrode contact is then formed in a portion of the upper oxide film 4 above the base region 2 and emitter region 3 by an etching technique using photoresist.

(f) Characteristics inspection: At the end, characteristics are inspected by pin contact, and then the electrode process is started.

As another example, CV D (Chemical Va
As shown in FIG. 9, thermal oxidation (1t! P S G (Ph
Ospho 5ilicate Glass) 6 etc. can be deposited to form a bashyhesion structure.

Furthermore, in the embodiments shown in FIGS. 5(a) to (f),
By continuously processing phosphorus deposition (a) and diffusion (oxidation) (b) in the same processing furnace, it is possible to reduce the number of man-hours including wafer charging and discharging work, eliminate foreign matter adhering to the wafer, and improve step-by-step processing. This has the effect of improving retention and quality.

Furthermore, if the annealing (C) treatment is also performed continuously in the same treatment furnace following the treatments (a) and (b), the above effect becomes even more remarkable.

In addition, in the previous examples, a method using a gas phase chemical reaction method using phosphorus oxychloride (POCl2) was described as an emitter formation method using phosphorus deposition (a) and diffusion (b) in FIG. The CVD method is used instead of phosphorus deposition, and as shown in FIG. 10, after opening the oxide film 4, a PSG film 7 is deposited, and then the next diffusion and oxidation treatment (b) is performed. As shown in FIG. 11, an emitter region 3 and a thermal oxide film 8 are formed, and after removing phosphor glass, PSGPJ is further formed as a passivation film.
6, a structure substantially similar to that shown in FIG. 9 can be obtained.

FIGS. 12(a) to 12(g) show process flowcharts corresponding to the above embodiment.

In this example, in the diffusion (oxidation) (b) step, the emitter region is The formation of 3 and the formation of the thermal oxide film 8 are performed by continuous processing in the same processing furnace.

In the embodiments so far, the case of manufacturing an npnl-transistor has been described, but the same method can also be applied to the case of manufacturing a pnp transistor.

In this case, for example, the 5th F! ! 1(a) and FIG. 12(a), the lindeposition may be placed on the porondeposition.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

According to the present invention, phosphorus deposition, diffusion, and annealing processing can be performed continuously in the same processing furnace, and wafer charging and discharging operations can be saved, thereby reducing the number of work steps. It is possible to significantly reduce the occurrence of damage caused by foreign matter adhering to the device, and as a result, it is possible to improve the yield and quality of devices.

[Brief explanation of drawings]

FIG. 1 is a process flowchart from emitter formation to characteristic inspection after contact photoresisting according to the prior art. 2 to 4 are process cross-sectional views corresponding to the process in FIG. 1. FIG. 5 is an embodiment of the present invention, and is a process flowchart from emitter formation to characteristic inspection after contact photoresistration. 6 to 8 are process cross-sectional views corresponding to the process shown in FIG. 5. FIG. 9 is a cross-sectional view of a device in which PSGllllj is formed as a passivation film in an embodiment of the present invention. FIGS. 10 and 11 are process cross-sectional views of other embodiment processes of the present invention. FIG. 12 is a process flow chart corresponding to another embodiment of the present invention, and FIGS. 10 and 11 correspond to this. 13(A), 13(B), and 13(C) are condition diagrams (curve diagrams) of an example of the diffusion processing sequence in the embodiment of FIG. 12. l...n-type Si substrate, 2...p-type base region, 3
...n-type emitter region, 4...thermal oxide film, 5...
・Phosphorus glass film, 6... Passivation (PSG
) film, 7... PSG film for emitter impurity source 8.
...Thermal oxidation I formed on the emitter! lIi. Figure 1 Figure 2 Figure 2-p¥7 - 744p area Figure 12 Figure

Claims (1)

[Claims] 1. A thermal oxide film obtained by removing all of the impurity-containing glass layer once formed on one main surface of a semiconductor substrate, or a thermal oxide film obtained by removing a part of the impurity-containing glass layer formed on one main surface of a semiconductor substrate. 1. A semiconductor device comprising an oxide film as part of a passivation film on the surface of its substrate. 2. In the manufacturing process of bipolar transistors,
An emitter region is formed on one main surface of a semiconductor substrate by successive processes of phosphorus deposition, diffusion treatment, and oxidation, and at the same time, a phosphorus glass layer and a thermal oxide film are formed thereon, and a thermal oxide film is formed by removing the phosphorus glass layer. A method for manufacturing a semiconductor element using a passivation film. 3. In the manufacturing process of bipolar transistors,
An emitter region is formed on one main surface of a semiconductor substrate by successive processes of phosphorus deposition, diffusion treatment, and oxidation, and at the same time, a phosphorus glass layer and a thermal oxide film are formed thereon, and a portion of the phosphorus glass layer is removed. A method for manufacturing a semiconductor device using a thermal oxide film containing phosphorus glass as a passivation film.