JP2019140243A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device capable of suppressing generation of variations in characteristics and reliability of the semiconductor device to be manufactured as compared to the method for manufacturing conventional semiconductor devices, and the semiconductor device manufactured by the manufacturing method.SOLUTION: There are provided a method for manufacturing a semiconductor device in which a channel stopper is formed in a peripheral region, and the semiconductor device manufactured by the manufacturing method. The method for manufacturing the semiconductor device successively includes a semiconductor substrate preparing step (S10) of preparing a semiconductor substrate in which a first region of a first conductivity type is exposed on the surface thereof and an oxide film forming step (S20) of forming an oxide film so as to expose a surface of a portion in which a channel stopper is to be formed. The method further includes: a glass film forming step (S30) of forming a glass film containing an impurity of a first conductivity type; an annealing step (S40) of forming a channel stopper by diffusing the impurity into the first region by annealing; and a channel stop electrode forming step (S60) of forming a channel stop electrode.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, a manufacturing method of a semiconductor device in which a channel stopper is formed in a peripheral region and a semiconductor device manufactured by the manufacturing method are known (see, for example, Patent Document 1).

A conventional semiconductor device manufacturing method and semiconductor device will be described by exemplifying a semiconductor device 900 shown below.
First, a conventional semiconductor device 900 will be described.
As shown in FIG. 16, the conventional semiconductor device 900 includes a semiconductor substrate 910 having a first conductivity type first region 920 and an ohmic layer 940 in which a channel stopper 930 is formed in the peripheral region, and a first region 920. An oxide film 950 formed on the surface, a glass film 960 formed so as to cover the oxide film 950, and a channel stop electrode 970 are provided. In the semiconductor device 900, the first conductivity type is n-type.
FIG. 16 shows the end of the peripheral region of the conventional semiconductor device 900, and the right side of the drawing is the end of the semiconductor device 900. The left side of FIG. 16 is not the end of the semiconductor device 900, but actually the semiconductor substrate 910 is continuous, and there is an active region of the semiconductor device 900 (region that provides the main operation as the semiconductor device).

  In the present specification, when the “first conductivity type” is n-type or p-type, the type of impurities contained is distinguished, and the concentration of impurities (from other regions and components). The relative concentration of

  Note that the semiconductor device 900 includes components other than those described above, for example, various electrodes and components configuring an active region (a region that provides a main operation as a semiconductor device). Since it is a well-known component not directly related, description and illustration are omitted.

Next, a conventional method for manufacturing a semiconductor device will be described.
The conventional semiconductor device manufacturing method is a manufacturing method for manufacturing the conventional semiconductor device 900.

  As shown in FIG. 17, a conventional semiconductor device manufacturing method includes a semiconductor substrate preparation step S910, an oxide film formation step S920, an impurity deposition step S930, an impurity diffusion step S940, a glass film formation step S950, an annealing step S960, and a glass film. The removal step S970 and the channel stop electrode formation step S980 are included in this order.

  Hereinafter, each step will be described. In the following description, description and description of components that are not directly related to the process are omitted. In addition, since all the above-mentioned processes are well-known processes, description will be kept simple. Further, the above-described process is a process shown for comparison with a method for manufacturing a semiconductor device according to the present invention described later, and the entire semiconductor device 900 is not manufactured only by the above-described process.

  The semiconductor substrate preparation step S910 is a step of preparing the semiconductor substrate 910 in which the first conductivity type first region 920 is exposed on the surface (see FIG. 18A).

  The oxide film forming step S920 is a step of forming the oxide film 950 on the surface of the first region 920 so that the surface of the portion where the channel stopper 930 is to be formed is exposed (see FIG. 18B).

In the impurity deposition step S930, the diffusion source d of the first conductivity type impurity (for example, POCl ₃ when the first conductivity type impurity is phosphorus) is deposited (deposited) on the surface of the first region 920. This is a process (see FIG. 18C).

  The impurity diffusion step S940 is a step of forming a channel stopper 930 by diffusing the first conductivity type impurity contained in the impurity diffusion source d into the first region 920 in a high temperature environment (FIG. 18D). reference.).

  The glass film forming step S950 is a step of forming the glass film 960 so as to cover the surfaces of the oxide film 950 and the channel stopper 930 (see FIG. 19A). Note that the glass film 960 in the semiconductor device 900 is a component that functions as a protective film (passivation film).

  The annealing step S960 is a step of annealing the glass film 960. Note that because of the drawing method used for explanation, the drawing related to the annealing step S960 is the same as FIG. 19A, which is the drawing related to the glass film forming step S950, and therefore the illustration related to the annealing step S960 is omitted.

  The glass film removing step S970 is a step of removing at least a part of the glass film 960 covering the surface of the channel stopper 930 (see FIG. 19B).

  The channel stop electrode formation step S980 is a step of forming a channel stop electrode 970 that is in contact with the channel stopper 930 (see FIG. 19C).

  Through the above steps, the semiconductor device 900 described above can be manufactured.

  According to the conventional method for manufacturing a semiconductor device, the channel stopper 930 is formed by diffusing impurities, including the impurity deposition step S930 and the impurity diffusion step S940, so that the depletion layer is prevented from reaching the outer end of the semiconductor device 900. Thus, a semiconductor device 900 that can suppress a decrease in breakdown voltage can be manufactured.

  According to the conventional semiconductor device 900, since the channel stopper 930 is formed, it is possible to suppress a decrease in breakdown voltage by preventing the depletion layer from reaching the outer end of the semiconductor device 900.

Japanese Patent No. 3557158

  However, the conventional method for manufacturing a semiconductor device as described above has a problem in that variations may occur in characteristics and reliability of the semiconductor device to be manufactured.

Accordingly, the present invention has been made to solve the above-described problem, and suppresses the occurrence of variations in characteristics and reliability of a semiconductor device to be manufactured as compared with a conventional method for manufacturing a semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of performing
It is another object of the present invention to provide a semiconductor device capable of suppressing variations in characteristics and reliability as compared with conventional semiconductor devices.

[1] A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a channel stopper is formed in a peripheral region, and a semiconductor substrate in which a first region of a first conductivity type is exposed on the surface. A semiconductor substrate preparation step to be prepared; and an oxide film formation step in which an oxide film is formed on the surface of the first region so that the surface of the portion where the channel stopper is to be formed is exposed. As a step performed after the step, a glass film forming step of forming a glass film containing a first conductivity type impurity so as to cover a surface of a portion of the first region where the channel stopper is to be formed, and the glass In addition to annealing the film, the annealing causes the first conductivity type impurities contained in the glass film to diffuse into the first region to form the channel stopper. And Lumpur step, further comprising a channel stop electrode forming step of forming a channel stop electrode in contact with the channel stopper.

[2] In the method for manufacturing a semiconductor device of the present invention, the semiconductor substrate preparation step, the oxide film formation step, the glass film formation step, the annealing step, and the surface of the channel stopper are covered. It is preferable that a glass film removing step for removing at least a part of the glass film and the channel stop electrode forming step are included in this order.

[3] In the method for manufacturing a semiconductor device of the present invention, the semiconductor substrate preparation step, the oxide film formation step, the channel stop electrode formation step, the glass film formation step, and the annealing step are performed in this order. It is preferable to contain.

[4] In the method for manufacturing a semiconductor device of the present invention, it is preferable to use phosphorus as the first conductivity type impurity and to use phosphorus glass as a material for forming the glass film.

[5] In the method for manufacturing a semiconductor device of the present invention, the content rate of the first conductivity type impurity in the surface of the glass film after the annealing step is in the range of 6 wt% to 9 wt%, and after the annealing step. The glass film preferably has a thickness in the range of 0.5 μm to 2.0 μm.

[6] In the method for manufacturing a semiconductor device of the present invention, it is preferable that in the annealing step, the channel stopper is formed so that the depth of the channel stopper is in a range of 0.3 μm to 4 μm.

[7] In the method for manufacturing a semiconductor device of the present invention, in the annealing step, the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate, and the semiconductor device to be manufactured is It is preferable to form the channel stopper so that the main region of the channel stopper has a region where the concentration of the first conductivity type impurity changes by three digits or more within a depth range of 0.15 μm to 1.0 μm. .

[8] In the method for manufacturing a semiconductor device of the present invention, as a step performed after the semiconductor substrate preparation step, the first conductivity type impurity is contained in a place different from the place where the glass film is formed. The method further includes a second glass film forming step of forming a second glass film, and in the step performed after the second glass film forming step, the second glass film is annealed and the second glass film is annealed. It is preferable to diffuse the first conductivity type impurity contained in the semiconductor substrate.

[9] A semiconductor device of the present invention includes a semiconductor substrate in which a channel stopper is formed in the peripheral region of the first region of the first conductivity type, and a channel stop electrode in contact with the channel stopper, The depth of the stopper is in the range of 0.3 μm to 4 μm.

[10] In the semiconductor device of the present invention, when the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate, the main region of the channel stopper has a thickness of 0.15 μm to 1.. It is preferable that there is a region where the concentration of the first conductivity type impurity changes by three digits or more within a depth range of 0 μm.

  According to the method for manufacturing a semiconductor device of the present invention, an annealing step is performed in which a channel stopper is formed by annealing a glass film and diffusing the first conductivity type impurity contained in the glass film into the first region by the annealing. Therefore, it is possible to reduce the number of times that the semiconductor substrate is placed in a high temperature environment, and to suppress the variation in the change in the fixed charge Qss of the oxide film induced by the variation in the annealing temperature condition. As a result, the semiconductor device manufacturing method of the present invention is a semiconductor device that can suppress variations in characteristics and reliability of the semiconductor device to be manufactured, as compared with the conventional semiconductor device manufacturing method. It becomes a manufacturing method.

By the way, in the conventional method for manufacturing a semiconductor device, the semiconductor substrate is placed in a high temperature environment in both the impurity diffusion process and the annealing process. It becomes easy to do. As a result, a semiconductor device manufactured by a conventional method for manufacturing a semiconductor device is likely to vary in characteristics and reliability.
The completion of the present invention greatly contributes to the fact that the study of the inventors of the present invention has revealed that the change in the fixed charge Qss greatly depends on the temperature conditions in the impurity diffusion process and the annealing process (described later). See FIG.

  Since the semiconductor device of the present invention is a semiconductor device that can be manufactured by the above-described method for manufacturing a semiconductor device of the present invention, the occurrence of variations in characteristics and reliability compared to conventional semiconductor devices is suppressed. It becomes a semiconductor device capable of.

1 is a cross-sectional view of a semiconductor device 100 according to Embodiment 1. FIG. FIG. 1 is a view showing the end portion of the peripheral region of the semiconductor device 100, and the right side of the drawing (the side where the channel stopper 130 is formed) is the end side of the semiconductor device 100. The end portion on the left side of the semiconductor device 100 in FIG. 1 is not the terminal of the constituent elements such as the semiconductor device 100 and the semiconductor substrate 110 constituting the semiconductor device 100. Actually, the semiconductor device 100 is continuous so as to exceed the end portion on the left side of FIG. 1, and a so-called active region (not shown) or the like exists on this side. Also in a cross-sectional view of a semiconductor device to be described later, the same display method is used for illustration. 3 is a flowchart of a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram of the method for manufacturing the semiconductor device according to the first embodiment. It is a graph for demonstrating the factor which the variation of the fixed electric charge Qss of an oxide film generate | occur | produces. The horizontal axis of the graph in FIG. 5 indicates the factor, and the vertical axis indicates the fixed charge Qss. Among the factors, A1, A2, and A3 are the thicknesses of the oxide films, and increase in the order of A1, A2, and A3. B1, B2, and B3 are the thicknesses of the glass film (in this case, phosphorus glass), and become thicker in the order of B1, B2, and B3. C1, C2, and C3 are the contents of impurities (phosphorus) in the glass film, and the contents increase in the order of C1, C2, and C3. D1, D2, and D3 are diffusion temperatures in the impurity diffusion process, and the temperatures increase in the order of D1, D2, and D3. On the other hand, the broken lines of t1, t2, and t3 constituting the graph are annealing temperatures in the annealing process, and the temperatures increase in the order of t1, t2, and t3. Note that the graph of FIG. 5 is created based on actual measurement values obtained in experiments conducted under conditions that are considered to be appropriate (applicable to many semiconductor devices that are the subject of the present invention). It is a graph which shows the CV characteristic when the semiconductor device which concerns on an Example, and the semiconductor device which concerns on a comparative example are made into a MOS element. The horizontal axis in FIG. 6 represents the reverse current voltage VR (unit: V), and the vertical axis represents the capacitance Cj (unit: pF). Note that the graph of FIG. 6 is created based on actual measurement values obtained in experiments conducted under conditions that are considered appropriate (applicable to many semiconductor devices that are objects of the present invention). It is a figure which shows the concentration profile of the main area | region of the channel stopper in the semiconductor device which concerns on an Example, and the semiconductor device which concerns on a comparative example. The horizontal axis in FIG. 7 indicates the depth (unit: μm) based on the surface of the first region, and the vertical axis indicates the impurity concentration (unit: cm ⁻³ ). Note that the graph of FIG. 7 is created based on actual measurement values obtained in experiments conducted under conditions that are considered appropriate (applicable to many semiconductor devices that are the subject of the present invention). FIG. 6 is a cross-sectional view of a semiconductor device 102 according to a second embodiment. 6 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment. FIG. 6 is a process diagram of a method for manufacturing a semiconductor device according to a second embodiment. FIG. 6 is a process diagram of a method for manufacturing a semiconductor device according to a second embodiment. FIG. 6 is a cross-sectional view of a semiconductor device 104 according to a third embodiment. 6 is a flowchart of a method for manufacturing a semiconductor device according to a third embodiment. FIG. 6 is a process diagram of a method for manufacturing a semiconductor device according to a third embodiment. FIG. 6 is a process diagram of a method for manufacturing a semiconductor device according to a third embodiment. It is sectional drawing of the conventional semiconductor device 900. FIG. It is a flowchart of the manufacturing method of the conventional semiconductor device. It is process drawing of the manufacturing method of the conventional semiconductor device. It is process drawing of the manufacturing method of the conventional semiconductor device.

  Hereinafter, a method for manufacturing a semiconductor device and a semiconductor device of the present invention will be described based on each embodiment shown in the drawings. Each drawing is a schematic diagram, and does not necessarily reflect an actual structure or configuration. Each embodiment described below does not limit the invention according to the claims. In addition, all of the elements and combinations described in the embodiments are not necessarily essential to the solution of the present invention. In each embodiment, the same reference numerals are used for components having the same basic configuration and characteristics (including components whose shapes and configurations are not completely the same), and the description thereof may be omitted. is there.

[Embodiment 1]
1. Configuration of Semiconductor Device 100 First, the configuration of the semiconductor device 100 according to the first embodiment will be described.
The semiconductor device 100 according to the first embodiment is a planar type diode.
As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 110, an oxide film 150, a glass film 160, and a channel stop electrode 170.
Note that the semiconductor device 100 also includes components other than those described above, for example, various electrodes and components constituting a region (so-called active region) that provides a main operation as the semiconductor device. Are not directly related to each other, and thus the description and illustration are omitted.

The semiconductor substrate 110 has a first region 120 and an ohmic layer 140.
The first region 120 is a first conductivity type region, and a channel stopper 130 is formed in the peripheral region. In the semiconductor device 100 according to the first embodiment, the first conductivity type is n-type, and the first region 120 is an n ⁻ -type region.
The concentration of the impurity in the first region 120 can be, for example, in the range of 5 × 10 ¹³ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ . The thickness of the first region 120 can be, for example, in the range of 5 μm to 120 μm.

The channel stopper 130 is an n ⁺⁺ type region having a higher impurity concentration than the first region 120. The channel stopper 130 is formed so as to go around the outer periphery of the semiconductor device 100 (so as to surround the structure existing in the center).
The depth of the channel stopper 130 is in the range of 0.3 μm to 4 μm.

Further, when the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate 110, the main region of the channel stopper 130 has the first conductivity within a depth range of 0.15 μm to 1.0 μm. There is a region where the concentration of the impurity of the type changes by three orders of magnitude or more. For this reason, it is difficult to say the concentration of impurities in the channel stopper 130 in general, but at a position where the concentration of impurities is the highest, for example, it is within a range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ^−3. be able to.
In this specification, the “main region of the channel stopper” refers to a region where the depth of the channel stopper is substantially constant when viewed along a direction perpendicular to the depth direction of the semiconductor substrate, in other words, A region that does not include the side diffusion portion of the channel stopper.

The ohmic layer 140 is an n ⁺ type region having a higher impurity concentration than the first region 120.
The oxide film 150 is formed on the surface of the first region 120. The oxide film 150 is made of, for example, SiO ₂ .
The thickness of the ohmic layer 140 is, for example, in the range of 50 μm to 600 μm. The impurity concentration of the ohmic layer 140 can be set within a range of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , for example.
The glass film 160 is formed so as to cover the oxide film 150. The glass film 160 functions as a protective film (passivation film). The glass film 160 contains a first conductivity type impurity.
In the first embodiment, phosphorus is used as the first conductivity type impurity, and the glass film 160 is made of phosphorus glass (PSG).

In the first embodiment, the content of impurities of the first conductivity type on the surface of the glass film 160 is in the range of 6 wt% to 9 wt%, and the film thickness of the glass film 160 is in the range of 0.5 μm to 2.0 μm. Preferably, it exists in the range of 1 micrometer-1.4 micrometers.
In the present specification, the “film thickness of the glass film” refers to the film thickness of the glass film formed on the oxide film.

The channel stop electrode 170 is in contact with the channel stopper 130. The channel stop electrode 170 is made of a conductive material, for example, a metal such as aluminum or polysilicon having sufficient conductivity (high impurity concentration).
The channel stop electrode is sometimes referred to as an EQR (Equi-potential Ring) electrode or an EQR structure.

2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the first embodiment will be described.
The manufacturing method of the semiconductor device according to the first embodiment is a manufacturing method for manufacturing a semiconductor device in which the channel stopper 130 is formed in the peripheral region, that is, for manufacturing the semiconductor device 100 according to the first embodiment. It is a manufacturing method.

  As shown in FIG. 2, the method for manufacturing a semiconductor device according to the first embodiment includes a semiconductor substrate preparation step S10 and an oxide film formation step S20 in this order, and is a step performed after the oxide film formation step S20. The glass film forming step S30, the annealing step S40, and the channel stop electrode forming step S60 are further included.

More specifically, the semiconductor device manufacturing method according to the first embodiment includes a semiconductor substrate preparation step S10, an oxide film formation step S20, a glass film formation step S30, an annealing step S40, a glass film removal step S50, a channel The stop electrode forming step S60 is included in this order.
Note that in this specification, the description relating to the description of the method for manufacturing a semiconductor device will mainly describe the steps highly relevant to the present invention. That is, the entire semiconductor device is not manufactured only by the steps described in this specification. The method for manufacturing a semiconductor device of the present invention may include steps other than those described in this specification.
Hereinafter, each step will be described. In the following description, description and description of components that are not directly related to the process are omitted.

The semiconductor substrate preparation step S10 is a step of preparing the semiconductor substrate 110 having the first conductivity type first region 120 exposed on the surface (see FIG. 3A).
In the first embodiment, the first conductivity type is n-type, and phosphorus is used as the first conductivity type impurity.
In the semiconductor substrate 110 prepared in the semiconductor substrate preparation step S <b> 10 in the first embodiment, the first region 120 exists on the ohmic layer 140.

The oxide film forming step S20 is a step of forming the oxide film 150 on the surface of the first region 120 so that the surface of the portion where the channel stopper 130 is to be formed is exposed (see FIG. 3B).
In the oxide film forming step S20, after forming the oxide film 150 on the surface of the first region 120 including the surface of the portion where the channel stopper 130 is to be formed (for example, the entire surface of the first region 120 in the peripheral region), the channel stopper is formed. This can be performed by a procedure of removing the oxide film 150 existing on the surface of the portion where 130 is to be formed. In addition, in the oxide film forming step S20, the oxide film 150 may be formed so that the surface of the first region 120 where the channel stopper 130 is to be formed is exposed from the beginning.
In short, in the oxide film forming step S20, the surface of the portion where the channel stopper 130 is to be finally formed may be exposed.

The glass film forming step S30 is a step of forming the glass film 160 containing the first conductivity type impurity so as to cover the surface of the portion of the first region 120 where the channel stopper 130 is to be formed (FIG. 3C). reference.). The formation of the glass film 160 itself can be performed using a known technique such as a CVD method, and thus the description thereof is omitted.
In the glass film forming step S30 in the first embodiment, phosphorus glass is used as a material for forming the glass film 160.
Further, in the first embodiment, the content ratio of the first conductivity type impurities on the surface of the glass film 160 after the annealing step S40 is in the range of 6 wt% to 9 wt%, and the film thickness of the glass film 160 after the annealing step S40. Is in the range of 0.5 μm to 2.0 μm, preferably in the range of 1 μm to 1.4 μm. For this reason, in glass film formation process S30, phosphorus glass is selected so that the said conditions may be satisfied, and the glass film 160 is formed.

The annealing step S40 is a step of annealing the glass film 160 and diffusing the first conductivity type impurities contained in the glass film 160 into the first region 120 by the annealing to form the channel stopper 130 ( (See FIG. 4 (a)).
In the annealing step S40 in the first embodiment, the channel stopper 130 is formed so that the depth of the channel stopper 130 is in the range of 0.3 μm to 4 μm.

  Further, in the annealing step S40 in the first embodiment, when the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate 110, the main region of the channel stopper 130 of the semiconductor device 100 to be manufactured is set to 0. The channel stopper 130 is formed so that there is a region where the concentration of the first conductivity type impurity varies by three digits or more within a depth range of 15 μm to 1.0 μm.

When the channel stopper 130 is formed from the impurities contained in the glass film 160 in the first embodiment, the numerical setting regarding the depth of the channel stopper 130 and the impurity concentration in the first embodiment is annealing of the glass film. This can be achieved by performing the annealing step S40 along a generally performed step.
The annealing temperature can be set in the range of 800 ° C. to 1100 ° C., for example.

  The glass film removal step S50 is a step of removing at least a part of the glass film 160 covering the surface of the channel stopper 130 (see FIG. 4B).

  The channel stop electrode formation step S60 is a step of forming a channel stop electrode 170 that contacts the channel stopper 130 (see FIG. 4C).

  Through the above steps, the semiconductor device 100 according to the first embodiment can be manufactured (a peripheral region of the semiconductor device 100 is formed).

3. Experiment on Method for Manufacturing Semiconductor Device Hereinafter, an explanation will be given based on the experiment result with reference to FIGS.

  First, the inventors of the present invention examined how much the change in the fixed charge Qss is caused by which factor in the method of manufacturing a semiconductor device. Based on the preliminary examination, the temperature of the annealing process that is considered to have the most influence on the change of the fixed charge Qss was used as the indication factor. In addition, as a matter to be determined by the design and affecting the fixed charge Qss, the thickness of the oxide film, the thickness of the glass film, the concentration of impurities in the glass film, and the diffusion temperature in the impurity diffusion process were used as control factors. . Further, the variation at five points set in the wafer surface was taken as an error factor. These were assigned to the L9 orthogonal table for experiments.

  As a result, as shown in FIG. 5, it has been found that the diffusion temperature in the impurity diffusion process has a great influence on the change of the fixed charge Qss as a factor for changing the fixed charge Qss. That is, in the conventional method for manufacturing a semiconductor device including both the impurity diffusion step and the annealing step, slight variations in temperature conditions in both steps may eventually appear as variations in the fixed charge Qss. .

  On the other hand, according to the method for manufacturing a semiconductor device of the present invention, it is not necessary to perform an impurity diffusion step separately from the annealing step. Therefore, the number of times that the semiconductor substrate is placed in a high temperature environment is reduced, and variations in the fixed charge Qss are reduced. It becomes possible to suppress.

Next, in order to see the degree of change in the fixed charge Qss by the semiconductor device manufacturing method according to the present invention, the MOS element corresponding to the semiconductor device manufactured by the semiconductor device manufacturing method according to the present invention and the conventional semiconductor device manufacturing method are used. For the MOS elements corresponding to the manufactured semiconductor devices, CV characteristics serving as a basis for calculating the fixed charge Qss were measured and compared.
In addition, in FIG. 6 which shows the result of the said experiment, the result about this invention is described by the name of an Example, and the result about the past is described by the name of a comparative example.

  As a result, as shown in FIG. 6, the CV waveform according to the semiconductor device manufacturing method of the present invention is compared with the CV waveform according to the conventional semiconductor device manufacturing method when VR is viewed from 0V toward the negative side. It was found that the point (inflection point) at which Cj began to decrease greatly when approached was close to 0V. The results show that the change in the fixed charge Qss of the oxide film formed by the semiconductor device manufacturing method of the present invention is smaller than the change in the fixed charge Qss of the oxide film formed by the conventional semiconductor device manufacturing method. ing.

Next, for the channel stopper formed by the semiconductor device manufacturing method of the present invention and the channel stopper formed by the conventional semiconductor device manufacturing method, the impurity concentration distribution was calculated by spreading resistance measurement (SRP).
In FIG. 7 showing the results of the above-described experiment, the results for the present invention are described by the names of Examples, and the results for the prior art are described by the names of Comparative Examples.

  As a result, as shown in FIG. 7, the channel stopper formed by the semiconductor device manufacturing method of the present invention is shallower and deeper than the channel stopper formed by the conventional semiconductor device manufacturing method. It has been found that the impurity concentration decreases sharply when viewed along the vertical direction.

4). Effects of Semiconductor Device Manufacturing Method and Semiconductor Device 100 According to First Embodiment Hereinafter, the semiconductor device manufacturing method and the semiconductor device 100 according to the first embodiment will be described.

  In the manufacturing method of the semiconductor device according to the first embodiment, the glass film 160 is annealed, and the first conductivity type impurity contained in the glass film 160 is diffused into the first region 120 by the annealing, thereby the channel stopper 130. An annealing step S40 is formed. For this reason, according to the method for manufacturing a semiconductor device according to the first embodiment, the number of times that the semiconductor substrate 110 is placed in a high temperature environment is reduced, and the change in the fixed charge Qss of the oxide film 150 induced by variations in the annealing temperature condition. Variations can be suppressed. As a result, the semiconductor device manufacturing method according to the first embodiment can suppress the occurrence of variations in the characteristics and reliability of the semiconductor device to be manufactured as compared with the conventional semiconductor device manufacturing method. It becomes the manufacturing method of an apparatus.

  In addition, according to the method for manufacturing a semiconductor device according to the first embodiment, a semiconductor device in which the change in the fixed charge Qss of the oxide film 150 itself is small as compared with a semiconductor device manufactured by a conventional method for manufacturing a semiconductor device. It becomes possible. For this reason, according to the method for manufacturing a semiconductor device according to the first embodiment, the reduction in reliability life and the occurrence of abnormal reverse characteristics (occurrence of abnormal waveforms and creep) due to the increase in the fixed charge Qss of the oxide film 150 are suppressed. It becomes possible to manufacture the semiconductor device 100 capable of doing so.

  Meanwhile, the channel stopper 130 formed by the semiconductor device manufacturing method according to the first embodiment has a lower impurity concentration than the channel stopper formed by the conventional semiconductor device manufacturing method, and the first region. There is a tendency that the depth based on the surface of 120 becomes shallower (thickness becomes thinner). However, according to the manufacturing method of the semiconductor device according to the first embodiment, the channel stop electrode 170 in contact with the channel stopper 130 is formed in the channel stop electrode forming step S60, so that a sufficient breakdown voltage is ensured in the semiconductor device 100 to be manufactured. It becomes possible.

  In addition, according to the semiconductor device manufacturing method according to the first embodiment, the semiconductor device 100 can be manufactured with fewer steps than the conventional semiconductor device manufacturing method.

  In addition, according to the method for manufacturing a semiconductor device according to the first embodiment, phosphorus is used as the first conductivity type impurity and phosphorus glass is used as a material for forming the glass film 160. The channel stopper 130 can be efficiently formed using

  In the method for manufacturing the semiconductor device according to the first embodiment, the content of the first conductivity type impurity on the surface of the glass film 160 after the annealing step S40 is set in the range of 6 wt% to 9 wt%. According to the method for manufacturing a semiconductor device according to the first embodiment, the content ratio of the impurities (phosphorus) contained in the phosphor glass is sufficiently increased by setting the content ratio of the first conductivity type impurity to 6 wt% or more. The channel stopper 130 can be formed sufficiently stably. In addition, according to the method for manufacturing a semiconductor device according to the first embodiment, the impurity content of the first conductivity type is set to 9 wt% or less, so that the impurity content is sufficiently low and the channel stopper 130 is accurately formed. It becomes possible to form.

  In the semiconductor device manufacturing method according to the first embodiment, the film thickness of the glass film 160 after the annealing step S40 is set in the range of 0.5 μm to 2.0 μm. According to the manufacturing method of the semiconductor device according to the first embodiment, it is possible to ensure a sufficient amount of impurities by setting the film thickness of the glass film 160 to 0.5 μm or more, and to manufacture the semiconductor device 100. It is possible to sufficiently secure the strength of the glass film 160. Further, according to the method for manufacturing a semiconductor device according to the first embodiment, it is possible to suppress the occurrence of cracks during the formation of the glass film 160 by setting the thickness of the glass film 160 to 2.0 μm or less. It is possible to suppress the occurrence of pattern step breakage when forming the various electrodes and the channel stop electrode 170, and to prevent the amount of impurities from becoming excessive.

  In the method of manufacturing the semiconductor device according to the first embodiment, in the annealing step S40, the channel stopper 130 is formed so that the depth of the channel stopper 130 is in the range of 0.3 μm to 4 μm. According to the manufacturing method of the semiconductor device according to the first embodiment, by setting the depth of the channel stopper 130 to 0.3 μm or more, it is possible to ensure a sufficient depth of the channel stopper 130. Further, according to the semiconductor device manufacturing method according to the first embodiment, by setting the depth of the channel stopper 130 to 4 μm or less, the channel stopper 130 is deeper than the channel stopper formed by the conventional method as described later. As a result, the semiconductor device 100 to be manufactured can be further miniaturized.

  In the manufacturing method of the semiconductor device according to the first embodiment, in the annealing step S40, when the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate 110, the channel stopper 130 of the semiconductor device 100 to be manufactured. In the conventional method, the channel stopper 130 is formed in such a manner that there is a region in which the concentration of the first conductivity type impurity changes by three digits or more within a depth range of 0.15 μm to 1.0 μm. The impurity concentration in the channel stopper 130 decreases more rapidly than the channel stopper to be formed, and the side diffusion is reduced. As a result, according to the manufacturing method of the semiconductor device according to the first embodiment, the area of the peripheral region can be reduced, and the semiconductor device 100 to be manufactured can be further downsized.

  Since the semiconductor device 100 according to the first embodiment is a semiconductor device that can be manufactured by the method for manufacturing a semiconductor device according to the first embodiment, variations in characteristics and reliability occur compared to a conventional semiconductor device. It becomes a semiconductor device capable of suppressing the above.

  According to the semiconductor device 100 according to the first embodiment, the depth of the channel stopper 130 is in the range of 0.3 μm to 4 μm. According to the semiconductor device 100 according to the first embodiment, since the depth of the channel stopper 130 is 0.3 μm or more, it is possible to ensure a sufficient depth of the channel stopper 130. Further, according to the semiconductor device 100 according to the first embodiment, since the depth of the channel stopper 130 is 4 μm or less, it becomes possible to make the depth of the channel stopper 130 shallower than the channel stopper in the conventional semiconductor device, As a result, the semiconductor device 100 can be further reduced in size.

  According to the semiconductor device 100 according to the first embodiment, when the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate 110, the main region of the channel stopper 130 has 0.15 μm to 1.. Since there is a region where the concentration of the first conductivity type impurity changes by three orders of magnitude or more within a depth range of 0 μm, the concentration of impurities in the channel stopper 130 is sharper than the channel stopper in the conventional semiconductor device. Side diffusion is reduced. As a result, according to the semiconductor device 100 according to the first embodiment, the area of the peripheral region can be reduced, and the semiconductor device 100 can be further downsized.

[Embodiment 2]
The manufacturing method of the semiconductor device according to the second embodiment is basically the same as the manufacturing method of the semiconductor device according to the first embodiment, but the order of steps is the same as the manufacturing method of the semiconductor device according to the first embodiment. Different. In addition, there are processes that have slightly different contents due to the difference in order (described later).
The semiconductor device 102 according to the second embodiment basically has the same configuration as that of the semiconductor device 100 according to the first embodiment. However, due to the method for manufacturing the semiconductor device according to the second embodiment, a channel stop electrode is provided. In addition, the configuration of the channel stopper is different from that of the semiconductor device 100 according to the first embodiment.

As shown in FIG. 8, a channel stopper 132 having a shape different from that of the channel stopper 130 in the first embodiment is formed on the semiconductor substrate 110 of the semiconductor device 102 according to the second embodiment. The channel stopper 132 is in contact with a part of the lower surface of the channel stop electrode 172. That is, it is not in contact with all the lower surface of the channel stop electrode 172.
In addition, the semiconductor device 102 includes a channel stop electrode 172 having a shape different from that of the channel stop electrode 170 in the first embodiment. The channel stop electrode 172 is shaped to ride on the oxide film 150.

  The channel stopper 132 and the channel stop electrode 172 are different in shape from the channel stopper 130 and the channel stop electrode 170 in the first embodiment, respectively, but the role played in the semiconductor device 102 is the channel stopper 130 and the channel stop electrode in the first embodiment. Similar to the stop electrode 170.

  The manufacturing method of the semiconductor device according to the second embodiment is a manufacturing method for manufacturing the semiconductor device 102 according to the second embodiment. As shown in FIG. 9, a semiconductor substrate preparation step S10 and an oxide film formation step S20 are performed. A channel stop electrode forming step S62, a glass film forming step S32, an annealing step S42, and a glass film removing step S52 in this order.

  The semiconductor substrate preparation step S10 and the oxide film formation step S20 are the same steps as the steps with the same names and symbols in the first embodiment, and thus description thereof is omitted (see FIGS. 10A and 10B). .

  The channel stop electrode formation step S62 is basically the same as the channel stop electrode formation step S60 in the first embodiment, but is performed after the oxide film formation step S20 in the second embodiment (FIG. 10C). reference.). Note that the channel stop electrode 172 formed in the channel stop electrode formation step S62 is exposed to a high temperature in the subsequent annealing step S42, and thus needs to be formed of a material that can withstand the high temperature. The channel stop electrode 172 is made of, for example, polysilicon to which impurities are sufficiently added (having sufficient conductivity).

  The glass film forming step S32 is basically the same as the glass film forming step S30 in the first embodiment, but is performed after the channel stop electrode forming step S62 in the second embodiment (see FIG. 11A). .) Therefore, in the glass film forming step S32, the glass film 160 is formed so as to embed the channel stop electrode 172.

The annealing step S42 is basically the same as the annealing step S40 in the first embodiment. However, in the second embodiment, since the channel stop electrode 172 has already been formed, the channel stopper formed in the annealing step S42. 132 does not spread to contact the entire lower surface of the channel stop electrode 172.
The channel stopper 132 is in contact with the channel stop electrode 172 by a region formed by side diffusion (in the case where impurities contained in the channel stop electrode diffuse into the semiconductor substrate 110, the channel stopper 132 includes a region formed by the diffusion). Therefore, the effect of the channel stop electrode 172 is not impaired.

  The glass film removing step S52 is the same as the glass film removing step S50 in the first embodiment. Note that since the channel stop electrode 172 has already been formed, the glass film removing step S52 may not be performed if unnecessary.

  As described above, the manufacturing method of the semiconductor device according to the second embodiment is different from the manufacturing method of the semiconductor device according to the first embodiment in the process sequence, but the glass film 160 is annealed and the glass film 160 is annealed by the annealing. An annealing step S42 for forming a channel stopper 132 by diffusing the contained first conductivity type impurity into the first region 120 is included. For this reason, according to the method for manufacturing a semiconductor device according to the second embodiment, the number of times that the semiconductor substrate 110 is placed in a high-temperature environment is reduced as in the method for manufacturing the semiconductor device according to the first embodiment, and the temperature condition of the annealing varies. It is possible to suppress variation in the change in the fixed charge Qss of the oxide film 150 induced by the above. As a result, the semiconductor device manufacturing method according to the second embodiment is similar to the semiconductor device manufacturing method according to the first embodiment, as compared with the conventional semiconductor device manufacturing method. This is a method for manufacturing a semiconductor device capable of suppressing the occurrence of variations.

  In addition, the semiconductor device manufacturing method according to the second embodiment includes a semiconductor substrate preparation step S10, an oxide film formation step S20, a channel stop electrode formation step S62, a glass film formation step S32, an annealing step S42, and a glass film. Since the removal step S52 is included in this order, the semiconductor device 102 can be manufactured with fewer steps than the conventional method for manufacturing a semiconductor device.

  The semiconductor device 102 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in the configuration of the channel stop electrode and the channel stopper, but can be manufactured by the semiconductor device manufacturing method according to the second embodiment. Therefore, like the semiconductor device 100 according to the first embodiment, the semiconductor device can suppress variations in characteristics and reliability as compared with the conventional semiconductor device.

  The semiconductor device manufacturing method according to the second embodiment is basically the same method as the semiconductor device manufacturing method according to the first embodiment, and the semiconductor device 102 according to the second embodiment is the same as the semiconductor device 100 according to the first embodiment. Therefore, the semiconductor device manufacturing method or the semiconductor device 100 according to the first embodiment also has a corresponding effect.

[Embodiment 3]
The manufacturing method of the semiconductor device according to the third embodiment is basically the same method as the manufacturing method of the semiconductor device according to the first embodiment, but according to the first embodiment in that it further includes a second glass film forming step. This is different from the manufacturing method of the semiconductor device.
In addition, the semiconductor device 104 according to the third embodiment basically has the same configuration as the semiconductor device 100 according to the first embodiment, but due to the semiconductor manufacturing method according to the second embodiment, the configuration of the ohmic layer Is different from the semiconductor device 100 according to the first embodiment.

  The semiconductor device 104 according to the third embodiment includes a semiconductor substrate 112 having an ohmic layer 142 as shown in FIG. The ohmic layer 142 is formed by the method for manufacturing a semiconductor device according to the third embodiment to be described later.

  As shown in FIG. 13, the semiconductor device manufacturing method according to the third embodiment includes a semiconductor substrate preparation step S12, an oxide film formation step S20, a glass film formation step S30, a second glass film formation step S70, and an annealing process. The process S44, the glass film removing process S50, and the channel stop electrode forming process S60 are included in this order.

  The semiconductor substrate preparation step S12 is basically the same as the semiconductor substrate preparation step S10 in the first embodiment, but a semiconductor substrate 112 having no ohmic layer is prepared. In the third embodiment, a semiconductor substrate 112 is prepared in which the entire peripheral region handled in the third embodiment is the first region 120 (see FIG. 14A).

  Since the oxide film forming step S20 and the glass film forming step S30 are the same steps as those of the same name in the first embodiment, description thereof is omitted (see FIGS. 14B and 14C).

  The second glass film forming step S70 is a step of forming the second glass film 180 containing the first conductivity type impurity at a place different from the place where the glass film 160 is formed (see FIG. 14D). ). In the third embodiment, the second glass film 180 is formed on the surface opposite to the glass film 160. The first conductivity type impurity in the third embodiment is phosphorus, and the second glass film 180 is also made of phosphorus glass (PSG) in the same manner as the glass film 160. Note that the material constituting the second glass film 180 may be different from the material constituting the glass film 160. For example, when the ohmic layer 142 is formed of the second glass film 180 as in the third embodiment, it is preferable that the impurity concentration of the second glass film 180 is higher than the impurity concentration of the glass film 160.

  The annealing step S44 is basically the same as the annealing step S40 in the first embodiment, but in addition to the contents of the annealing step S40 in the first embodiment, the second glass film 180 is annealed and the annealing is performed. This is a step of diffusing impurities of the first conductivity type contained in the second glass film 180 into the semiconductor substrate 110. In the third embodiment, the ohmic layer 142 is formed by the annealing step S44.

  As described above, the manufacturing method of the semiconductor device according to the third embodiment is different from the manufacturing method of the semiconductor device according to the first embodiment in that it further includes the second glass film forming step. Then, an annealing step S44 for forming a channel stopper 132 by diffusing the first conductivity type impurity contained in the glass film 160 into the first region 120 by the annealing is included. For this reason, according to the method for manufacturing a semiconductor device according to the third embodiment, the number of times that the semiconductor substrate 112 is placed in a high-temperature environment is reduced, as in the method for manufacturing the semiconductor device according to the first embodiment. It is possible to suppress variation in the change in the fixed charge Qss of the oxide film 150 induced by the above. As a result, the semiconductor device manufacturing method according to the third embodiment is similar to the semiconductor device manufacturing method according to the first embodiment, as compared with the conventional semiconductor device manufacturing method. This is a method for manufacturing a semiconductor device capable of suppressing the occurrence of variations.

  In addition, according to the method for manufacturing a semiconductor device according to the third embodiment, the second glass film is formed to form the second glass film 180 containing the first conductivity type impurity at a place different from the place where the glass film 160 is formed. In addition to the step S70, the second glass film 180 is annealed in the step performed after the second glass film forming step S70, and the first conductivity type impurities contained in the second glass film are removed from the semiconductor by the annealing. In order to diffuse into the substrate 112, a region (ohmic layer 142) having a high impurity concentration different from that of the channel stopper 130 may be formed in the semiconductor substrate 112 by a method similar to the method of forming the channel stopper 130 with the glass film 160. It becomes possible.

  In addition, according to the method for manufacturing a semiconductor device according to the third embodiment, the second glass film 180 is annealed in the annealing step S44, and the first conductivity type impurities contained in the second glass film are removed by the annealing. In order to diffuse into the semiconductor substrate 112, a region (ohmic layer 142) having a high impurity concentration different from that of the channel stopper 130 can be formed in the semiconductor substrate 112 without increasing the number of times the semiconductor substrate 112 is placed in a high temperature environment. It becomes.

  The semiconductor device 104 according to the third embodiment is a semiconductor device that can be manufactured by the method for manufacturing a semiconductor device according to the third embodiment, although the configuration of the low-resistance semiconductor layer is different from that of the semiconductor device 100 according to the first embodiment. Therefore, similarly to the semiconductor device 100 according to the first embodiment, the semiconductor device can suppress variations in characteristics and reliability as compared with the conventional semiconductor device.

  The semiconductor device manufacturing method according to the third embodiment is basically the same as the semiconductor device manufacturing method according to the first embodiment, and the semiconductor device 104 according to the third embodiment is the same as the semiconductor device 100 according to the first embodiment. Therefore, the semiconductor device manufacturing method or the semiconductor device 100 according to the first embodiment also has a corresponding effect.

  As mentioned above, although this invention was demonstrated based on said each embodiment, this invention is not limited to each said embodiment. The present invention can be implemented in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) The shape, number, position, and the like of the constituent elements described in the above embodiments are examples, and can be changed within a range not impairing the effects of the present invention.

(2) The position of the second glass film 180 described in the third embodiment is an exemplification, and the second glass film 180 may be formed at another position and a region different from the ohmic layer 142 may be formed.

(3) The present invention is established even when the n-type and the p-type are opposite to the above embodiments. When the n-type and the p-type are opposite to the above embodiments, boron can be used as the first conductivity type impurity.

(4) In each of the above embodiments, the semiconductor device is a planar type diode, but the present invention is not limited to this. The present invention can also be applied to other semiconductor devices such as diodes other than the planar type (for example, mesa type diodes), thyristors, and triacs.

100, 102, 104 ... Semiconductor device, 110, 112 ... Semiconductor substrate, 120 ... First region, 130, 132 ... Channel stopper, 140, 142 ... Ohmic layer, 150 ... Oxide film, 160 ... Glass film, 170, 172 ... Channel stop electrode, 180 ... second glass film

Claims (10)

A method of manufacturing a semiconductor device in which a channel stopper is formed in a peripheral region,
A semiconductor substrate preparation step of preparing a semiconductor substrate in which a first region of the first conductivity type is exposed on the surface;
An oxide film forming step for forming an oxide film on the surface of the first region so that the surface of the portion where the channel stopper is to be formed is exposed, in this order,
As a step performed after the oxide film forming step,
A glass film forming step of forming a glass film containing an impurity of a first conductivity type so as to cover a surface of a portion of the first region where the channel stopper is to be formed;
An annealing step of performing annealing of the glass film and diffusing the first conductivity type impurity contained in the glass film by the annealing into the first region to form the channel stopper;
A method of manufacturing a semiconductor device, further comprising: a channel stop electrode forming step of forming a channel stop electrode in contact with the channel stopper. The semiconductor substrate preparation step;
The oxide film forming step;
The glass film forming step;
The annealing step;
A glass film removing step for removing at least a part of the glass film covering the surface of the channel stopper;
The method for manufacturing a semiconductor device according to claim 1, comprising the channel stop electrode forming step in this order. The semiconductor substrate preparation step;
The oxide film forming step;
The channel stop electrode forming step;
The glass film forming step;
The method of manufacturing a semiconductor device according to claim 1, wherein the annealing step is included in this order. Phosphorus is used as the impurity of the first conductivity type,
The method for manufacturing a semiconductor device according to claim 1, wherein phosphorous glass is used as a material for forming the glass film. The content rate of the first conductivity type impurity on the surface of the glass film after the annealing step is in the range of 6 wt% to 9 wt%,
5. The method of manufacturing a semiconductor device according to claim 4, wherein a film thickness of the glass film after the annealing step is set in a range of 0.5 μm to 2.0 μm.   6. The method of manufacturing a semiconductor device according to claim 1, wherein in the annealing step, the channel stopper is formed so that a depth of the channel stopper is in a range of 0.3 [mu] m to 4 [mu] m. Method.   In the annealing step, when the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate, the main region of the channel stopper of the semiconductor device to be manufactured is 0.15 μm to 1.0 μm. 7. The semiconductor according to claim 1, wherein the channel stopper is formed so that a region where the concentration of the impurity of the first conductivity type changes by three orders of magnitude or more exists within a depth range of 7. Device manufacturing method. As a step performed after the semiconductor substrate preparation step,
A second glass film forming step of forming a second glass film containing the first conductivity type impurity at a place different from the place where the glass film is formed;
In the step performed after the second glass film forming step, the second glass film is annealed, and the first conductivity type impurity contained in the second glass film is added to the semiconductor substrate by the annealing. The method for manufacturing a semiconductor device according to claim 1, wherein diffusion is performed. A semiconductor substrate having a channel stopper formed in a peripheral region of the first region of the first conductivity type;
An oxide film formed on the surface of the first region;
A glass film formed to cover the oxide film;
A channel stop electrode in contact with the channel stopper;
The depth of the channel stopper is in the range of 0.3 μm to 4 μm.   When the concentration of the first conductivity type impurity is viewed along the depth direction of the semiconductor substrate, the main region of the channel stopper has the first conductivity within a depth range of 0.15 μm to 1.0 μm. The semiconductor device according to claim 9, wherein there is a region where the concentration of the impurity of the type changes by three digits or more.

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