JP3951657B2 - Semiconductor element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element, and more particularly to a semiconductor element having a pn junction structure.
[0002]
[Prior art]
A semiconductor element such as a diode is configured such that electrodes are formed on an upper surface and a lower surface of a semiconductor substrate, respectively, and current flows in the thickness direction of the semiconductor substrate. As such a semiconductor element, there are a pn junction structure and a Schottky barrier structure. A semiconductor element having a pn junction structure has a characteristic that it is difficult to be destroyed even by a high voltage in the reverse direction. A semiconductor device having a structure is used.
[0003]
The semiconductor device of the pn junction structure, for example, a semiconductor substrate made of n ⁺ -type semiconductor, n formed by common epitaxial growth method on the upper surface of the semiconductor substrate ^- -type semiconductor region, n ^- generally on the upper surface of the semiconductor region A P-type semiconductor region formed by a typical impurity diffusion method, an anode electrode formed on the upper surface of the semiconductor substrate and electrically connected to the P-type semiconductor region, and an n ⁺ -type semiconductor substrate on the lower surface of the semiconductor substrate. And an electrically connected cathode electrode.
[0004]
Further, for example, a field limiting ring (FLR) formed in an annular shape so as to surround the P-type semiconductor region is provided on the outer peripheral side of the P-type semiconductor region on the upper surface of the n ⁻ -type semiconductor region, and the n ⁻ -type semiconductor A depletion layer formed by a pn junction between the region and the P-type semiconductor region is extended to the outer peripheral side of the FLR to increase the breakdown voltage of the semiconductor element.
[0005]
By the way, in such a diode, a silicon single crystal substrate having a (111) plane orientation of the main surface of the substrate is used as the semiconductor substrate. Further, since the n ⁻ type semiconductor region on the semiconductor substrate is formed on the upper surface of the semiconductor substrate by the epitaxial growth method, this plane orientation also becomes the (111) plane.
[0006]
[Problems to be solved by the invention]
However, in a diode using a silicon single crystal substrate having a (111) plane orientation, the reverse current (leakage current) tends to increase, and as a result, the variation in reverse current tends to increase. In particular, when the thickness of the n ⁻ type semiconductor region is increased, the reverse current and the variation in the reverse current tend to increase. FIG. 4 is a graph showing variations in reverse current (maximum value, minimum value, and average value of reverse current) when the thickness of the n ⁻ type semiconductor region is changed. As shown in FIG. 4, when the thickness of the n ⁻ type semiconductor region is increased, the maximum value of the reverse current is increased and the variation of the reverse current is increased. In particular, when the thickness of the n ⁻ -type semiconductor region is 30 μm or more, the maximum value of the reverse current suddenly increases, and the difference between the maximum value and the minimum value of the reverse current becomes 1000 times or more. Thus, when the variation in the reverse current becomes large, the reverse characteristic of the diode becomes unstable.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor element that can suppress variations in reverse current.
Another object of the present invention is to provide a semiconductor element capable of suppressing reverse current.
Furthermore, an object of the present invention is to provide a semiconductor device that can stably achieve high breakdown voltage while suppressing variations in reverse current.
[0008]
[Means for Solving the Problems]
To achieve the above object, a semiconductor element of the present invention includes a first conductivity type silicon substrate, a first conductivity type silicon semiconductor layer formed on the silicon substrate and having an impurity concentration lower than that of the silicon substrate, A silicon semiconductor region of a second conductivity type formed in a predetermined region on the upper surface of the silicon semiconductor layer and forming a pn junction at the interface with the silicon semiconductor layer, the silicon substrate, the silicon semiconductor layer, and wherein the silicon semiconductor region, a lifetime killer consisting heavy metal is introduced, the surface orientation of the upper surface and the silicon semiconductor layer of a silicon substrate (100) Mendea is, the thickness of the silicon semiconductor layer, at least 30μm It is characterized by that.
[0009]
According to this configuration, the plane orientation of the upper surface of the silicon substrate and the silicon semiconductor layer is the (100) plane. Since the plane orientation of the top surface of the silicon substrate and the silicon semiconductor layer is the (100) plane, stacking faults in the vertical direction of the silicon substrate that have a large influence on the reverse current are difficult to grow. For this reason, even if the thickness of the silicon semiconductor layer is increased, the reverse current is hardly increased, and the variation in the reverse current is not easily increased. Therefore, variations in reverse current and reverse current can be suppressed.
[0011]
The silicon semiconductor layer is preferably formed by epitaxial growth on the silicon substrate. In this case, the plane orientation of the silicon semiconductor layer is the same as the plane orientation of the upper surface of the silicon substrate.
[0012]
A second conductivity type field limiting ring formed in an annular shape so as to surround the silicon semiconductor region may be further provided on the upper surface of the silicon semiconductor layer. In this case, the depletion layer formed by the pn junction can be extended to the outer peripheral side of the field limiting ring, and the breakdown voltage of the semiconductor element can be increased.
[0013]
An equipotential ring formed in an annular shape so as to surround the silicon semiconductor region via the field limiting ring may be further provided on the upper surface of the silicon semiconductor layer. In this case, the depletion layer formed by the pn junction can be spread stably and satisfactorily in the lateral direction of the semiconductor element, and the depletion layer is prevented from spreading to the side surface of the semiconductor element, thereby increasing the breakdown voltage of the semiconductor element. It can be achieved stably.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the semiconductor element of the present invention will be described taking as an example the case of a high voltage diode having a so-called field limiting ring (FLR). FIG. 1 shows a cross-sectional view of the diode of the present embodiment.
[0015]
As shown in FIG. 1, the diode 1 includes a semiconductor substrate 2, an n ⁻ type semiconductor layer 3, a P ⁺ type semiconductor region 4, a field limiting ring (FLR) 5, and an equipotential ring (EQR) 6. , An insulating film 7, an upper electrode 8, and a lower electrode 9. In the semiconductor substrate 2, the n ⁻ type semiconductor layer 3, and the P ⁺ type semiconductor region 4, heavy metal, for example, Au is diffused as a lifetime killer.
[0016]
The semiconductor substrate 2 has a relatively high concentration such that the first conductivity type, for example, an n-type impurity (for example, antimony) is about 1.0 × 10 ¹⁸ cm ^{−3 to} 5.0 × 10 ¹⁸ cm ^−3. It is composed of an introduced n ⁺ type silicon single crystal substrate. This semiconductor substrate 2 functions as a cathode contact region. The semiconductor substrate 2 is a silicon single crystal substrate whose top surface has a (100) plane orientation. That is, the semiconductor substrate 2 functioning as a cathode contact region is constituted by a silicon single crystal substrate whose surface orientation is the (100) plane indicated by the Miller index.
[0017]
The n ⁻ type semiconductor layer 3 is formed on the semiconductor substrate 2. The n ⁻ type semiconductor layer 3 is formed by a general epitaxial growth method and functions as a cathode region. The n ⁻ type semiconductor layer 3 has a first conductivity type, for example, an n-type impurity (for example, phosphorus) is compared so that it is about 5.0 × 10 ¹³ cm ^{−3 to} 5.0 × 10 ¹⁴ cm ^−3. The semiconductor substrate 2 is composed of an n ⁻ type semiconductor layer having an impurity concentration lower than that of the semiconductor substrate 2.
[0018]
Further, since the n ⁻ type semiconductor layer 3 is formed on the semiconductor substrate 2 by epitaxial growth, the n ⁻ type semiconductor layer 3 is formed so as to inherit the plane orientation of the upper surface of the semiconductor substrate 2 and align the plane orientation with the upper surface of the semiconductor substrate 2. For this reason, the plane orientation of the n ⁻ -type semiconductor layer 3 is the (100) plane indicated by the Miller index like the upper surface of the semiconductor substrate 2.
[0019]
By the way, the value of reverse current (leakage current) depends on, for example, stacking faults generated by repeated thermal oxidation at a high temperature. In particular, the value of the reverse current greatly depends on defects generated in the direction perpendicular to the orientation flat (facet). For this reason, when the defect generated in the vertical direction grows, the value of the reverse current and the variation in the reverse current increase.
[0020]
This stacking fault occurs near the surface of the silicon wafer by, for example, thermally oxidizing the silicon wafer at a high temperature such as 1200 ° C. When the direction of the defect coincides with the direction of the crystal axis, It is considered that the growth is caused by each stress such as tensile stress and shear stress (for example, external stress generated by a thermal oxide film or metal or internal stress generated by impurity diffusion).
[0021]
Here, when the plane orientation is the (111) plane, this crystal axis has three crystal axes, that is, a crystal axis perpendicular to the orientation flat and two crystal axes intersecting with this crystal axis at 60 °. There is. On the other hand, when the plane orientation is the (100) plane, there are two crystal axes that intersect at 45 ° with respect to the orientation flat. For this reason, when the plane orientation is the (111) plane, the defect direction (vertical direction) that most affects the reverse current value coincides with the crystal axis direction, and the plane orientation is the (100) plane. In some cases, it does not coincide with the crystal axis direction.
[0022]
For this reason, if the surface orientation of the upper surface of the semiconductor substrate 2 and the n ⁻ type semiconductor layer 3 is the (111) plane, defects in the vertical direction grow to increase the value of the reverse current, and variations in the reverse current also occur. growing. On the other hand, when the surface orientation of the upper surface of the semiconductor substrate 2 and the n ⁻ type semiconductor layer 3 is the (100) plane, defects in the vertical direction are difficult to grow.
[0023]
In the present embodiment, since the plane orientation of the upper surface of the semiconductor substrate 2 is the (100) plane and the plane orientation of the n ⁻ type semiconductor layer 3 is the (100) plane, the value of the reverse current is most affected. Since the direction of the given defect (vertical direction) and the crystal axis direction do not coincide with each other, it is difficult for the defect to grow, the value of the reverse current does not increase, and the reverse current variation is suppressed.
[0024]
The thickness of the n ⁻ type semiconductor layer 3 is preferably 30 μm or more. When the thickness of the n ⁻ -type semiconductor layer 3 is 30 μm or more, the reverse current tends to increase and the reverse current tends to vary, which is suitable for the present invention that suppresses variations in the reverse current and the reverse current. Because. However, if the thickness of the n ⁻ type semiconductor layer 3 becomes too thick, various characteristics of the diode 1 are deteriorated. Therefore, the thickness of the n ⁻ type semiconductor layer 3 is preferably 30 μm to 110 μm, and preferably 30 μm to 30 μm. More preferably, it is 80 μm.
[0025]
The P ⁺ type semiconductor region 4 is formed in a predetermined region of the n ⁻ type semiconductor layer 3. The P ⁺ type semiconductor region 4 is formed by a general impurity diffusion method. For example, p-type impurities (e.g., boron) and n ^- by selectively introducing a predetermined area of the upper surface of the type semiconductor layer 3, n ^- diffused into a predetermined region on the upper surface of the type semiconductor layer 3, the A P ⁺ type semiconductor region 4 is formed in a predetermined region. This P ⁺ type semiconductor region 4 constitutes the anode region of the diode 1. In the present embodiment, the depth (diffusion depth) of the P ⁺ type semiconductor region 4 is set to about 16 μm from the upper surface of the n ⁻ type semiconductor layer 3.
[0026]
The field limiting ring (FLR) 5 is formed in an annular shape on the upper surface of the n ⁻ type semiconductor layer 3 so as to surround the P ⁺ type semiconductor region 4. The FLR 5 is formed by a general impurity diffusion method. For example, P ⁺ -type semiconductor region 4 and the same p-type impurity (e.g., boron) and, n ^- FLR5 by introducing -type semiconductor layer 3 on the upper surface P ⁺ -type semiconductor regions 4 in an annular shape so as to surround the form Is done. For example, the FLR 5 is formed by diffusing the same p-type impurity (for example, boron) in the step of forming the P ⁺ type semiconductor region 4. The FLR 5 can widen the depletion layer formed by the pn junction between the n ⁻ type semiconductor layer 3 and the P ⁺ type semiconductor region 4 to the outer peripheral side of the FLR 5, and can increase the breakdown voltage of the diode 1. In the present embodiment, as shown in FIG. 1, two FLRs 5 are formed. However, as the number of FLRs 5 is increased, the diode 1 can have a higher breakdown voltage. Accordingly, it is preferable to form a predetermined number of FLRs 5.
[0027]
The equipotential ring (EQR) 6 includes an n ⁺ type semiconductor region 6a and a metal film 6b. The n ⁺ type semiconductor region 6 a is formed in an annular shape on the outer edge of the upper surface of the n ⁻ type semiconductor layer 3 so as to surround the P ⁺ type semiconductor region 4 via the FLR 5. The n ⁺ -type semiconductor region 6a is formed by applying a first conductivity type, for example, an n-type impurity (for example, phosphorus) to the outer edge of the upper surface of the n ⁻ -type semiconductor layer 3 via the FLR 5 by a general impurity diffusion method. The p ⁺ type semiconductor region 4 is formed by being introduced into a ring so as to surround it. The metal film 6b is formed in an annular shape on the outer edge of the upper surface of the n ⁺ type semiconductor region 6a (n ⁻ type semiconductor layer 3). The metal film 6b is formed of, for example, an aluminum vapor deposition layer, and is electrically connected to the n ⁺ type semiconductor region 6a. The EQR 6 has a function of stabilizing the charge on the surface of the insulating film 7 and a function of preventing the depletion layer from spreading to the outer periphery. Thus, since the FLR 5 and the EQR 6 are formed, the depletion layer can be stably and satisfactorily spread in the lateral direction of the diode 1, and the depletion layer is prevented from spreading to the side surface of the diode 1. High breakdown voltage can be stably achieved.
[0028]
The insulating film 7 is formed so as to cover the upper surfaces of the n ⁻ type semiconductor layers 3 and FLR 5, the outer peripheral side of the upper surface of the P ⁺ type semiconductor region 4, and the inner peripheral side of the n ⁺ type semiconductor region 6 a. . In the present embodiment, for example, a silicon oxide film formed by thermal oxidation is used for the insulating film 7.
[0029]
The upper electrode 8 is formed on the upper surface of the P ⁺ type semiconductor region 4. The upper electrode 8 constitutes an anode electrode made of a metal film, and is electrically connected to the P ⁺ type semiconductor region 4 (anode region).
[0030]
The lower electrode 9 is formed on the lower surface of the semiconductor substrate 2. The lower electrode 9 constitutes a cathode electrode made of a metal film, and is electrically connected to the semiconductor substrate 2 (cathode contact region).
[0031]
In the diode 1 configured as described above, the plane orientation of the upper surface of the semiconductor substrate 2 is the (100) plane, and the plane orientation of the n ⁻ type semiconductor layer 3 is the (100) plane. For this reason, the reverse current which is the leakage current in the reverse bias state is suppressed, and the variation in the reverse current is suppressed.
[0032]
In order to confirm the effect of the present invention, the reverse current (leakage current) is measured for each thickness of the n ⁻ type semiconductor layer 3 for the diode 1 in which the thickness of the n ⁻ type semiconductor layer 3 is changed. The maximum value (MAX), minimum value (MIN), and average value (AVE) of the current were determined. The results are shown in FIGS. FIG. 3 also shows the difference (MAX−MIN) between the maximum value and the minimum value of the reverse current. For comparison, the maximum value, the minimum value, and MAX-MIN of the reverse current in the conventional case (the diode whose surface orientation of the semiconductor substrate 2 and the n ⁻ type semiconductor layer 3 is the (111) plane) are shown as comparative examples. It is shown in 3.
[0033]
As shown in FIG. 2 and FIG. 3, the maximum value of the reverse current can be obtained by using the semiconductor substrate 2 having the (100) plane orientation and the n ⁻ type semiconductor layer 3 having the (100) plane orientation. Decrease significantly. For this reason, the difference between the maximum value and the minimum value of the reverse current is reduced, and variations in the reverse current are suppressed. For example, when the thickness of the n ⁻ type semiconductor layer 3 is 30 μm, it is 0.1 μA in the example, whereas it is 179.97 μA in the conventional comparative example. As described above, the difference between the maximum value and the minimum value of the reverse current can be obtained by using the semiconductor substrate 2 having the (100) plane surface and the n ⁻ -type semiconductor layer 3 having the (100) plane direction. It could be about 1/1800, and it was confirmed that variations in reverse current could be suppressed.
[0034]
As described above, according to the present embodiment, the reverse current is obtained by using the semiconductor substrate 2 having the (100) plane orientation and the n ⁻ type semiconductor layer 3 having the (100) plane orientation. Is greatly reduced, and the reverse current is suppressed. For this reason, the difference between the maximum value and the minimum value of the reverse current is reduced, and variations in the reverse current are suppressed.
[0035]
According to this embodiment, n ^- the upper surface of the type semiconductor layer 3, so as to surround the P ⁺ -type semiconductor regions 4, since FLR5 is annularly formed, n ^- -type semiconductor layer 3 and the P ⁺ -type A depletion layer formed by a pn junction with the semiconductor region 4 can be extended to the outer peripheral side of the FLR 5 to increase the breakdown voltage of the diode 1.
[0036]
According to the present embodiment, the EQR 6 is formed in an annular shape so as to surround the P ⁺ type semiconductor region 4 via the FLR 5 on the outer edge of the upper surface of the n ⁻ type semiconductor layer 3. Charge stabilization on the surface of the film 7 and spread of the depletion layer to the outer periphery can be prevented. Thus, since the FLR 5 and the EQR 6 are formed, the depletion layer can be stably and satisfactorily spread in the lateral direction of the diode 1, and the depletion layer is prevented from spreading to the side surface of the diode 1. High breakdown voltage can be stably achieved.
[0037]
In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, other embodiments applicable to the present invention will be described.
[0038]
In the above embodiment, the present invention has been described by taking the case of the high breakdown voltage diode 1 having the field limiting ring 5 as an example. However, the present invention includes a semiconductor substrate 2, an n ⁻ type semiconductor layer 3, and a P ⁺ type semiconductor region. The plane orientation of the upper surface of the semiconductor substrate 2 and the n ⁻ type semiconductor layer 3 only needs to be a (100) plane. For example, the diode 1 in which the FLR 5 and the EQR 6 are not formed may be used.
[0039]
In the above embodiment, the present invention has been described by taking the case where the n ⁻ type semiconductor layer 3 is formed by epitaxial growth on the semiconductor substrate 2 as an example, but the top surface has a (100) plane orientation on the semiconductor substrate 2. The n ⁻ type semiconductor layer 3 having a (100) plane orientation may be formed, and the method for manufacturing the n ⁻ type semiconductor layer 3 is not limited to the epitaxial growth method.
[0040]
In the above embodiment, the present invention has been described by taking the case where the first conductivity type is n-type and a semiconductor substrate is used as the semiconductor substrate 2, but the first conductivity type is p-type and the conductivity type of each member is It may be reversed. In the above embodiment, the present invention has been described with respect to the case where the diode 1 is manufactured. However, the semiconductor element may be a semiconductor element having a pn junction structure.
[0041]
In the above embodiment, the present invention has been described by taking an example in which heavy metal (Au or the like) is diffused as a lifetime killer. However, the present invention can also be applied to a semiconductor element that does not diffuse a lifetime killer. However, when the lifetime killer is diffused, the variation in the reverse current becomes larger. Therefore, when the present invention is applied to a semiconductor device in which the lifetime killer is diffused, a remarkable effect can be obtained.
[0042]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress variations in reverse current.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a diode according to an embodiment of the present invention.
FIG. 2 is a graph showing the relationship between the thickness of the n ⁻ type semiconductor layer and the reverse current according to the embodiment of the present invention.
FIG. 3 is a table showing a relationship between an embodiment of the present invention and a conventional n ⁻ type semiconductor layer and a reverse current.
FIG. 4 is a graph showing the relationship between the thickness of a conventional n ⁻ type semiconductor layer and the reverse current.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Diode 2 Semiconductor substrate 3 n ⁻ type semiconductor layer 4 P ⁺ type semiconductor region 5 Field limiting ring (FLR)
6 Equipotential ring (EQR)
7 Insulating film 8 Upper electrode 9 Lower electrode

Claims (4)

A first conductivity type silicon substrate;
A silicon semiconductor layer of a first conductivity type formed on the silicon substrate and having an impurity concentration lower than that of the silicon substrate;
A second conductivity type silicon semiconductor region formed in a predetermined region on the upper surface of the silicon semiconductor layer and forming a pn junction at an interface with the silicon semiconductor layer;
With
A lifetime killer made of heavy metal is introduced into the silicon substrate, the silicon semiconductor layer, and the silicon semiconductor region,
The plane orientation of the upper surface and the silicon semiconductor layer of a silicon substrate (100) Mendea is,
A semiconductor element , wherein the silicon semiconductor layer has a thickness of at least 30 μm . The semiconductor element according to claim 1, wherein the silicon semiconductor layer is formed by epitaxial growth on the silicon substrate. The upper surface of the silicon semiconductor layer, a second conductivity type field limiting ring formed into an annular shape so as to surround the silicon semiconductor region, further comprising a semiconductor according to claim 1 or 2, characterized in that element. The semiconductor according to claim 3 , further comprising an equipotential ring formed in an annular shape so as to surround the silicon semiconductor region via the field limiting ring on an upper surface of the silicon semiconductor layer. element.

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