JP3951677B2 - Semiconductor element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element, and more particularly to a semiconductor element in which gold (Au) is introduced as a lifetime killer.
[0002]
[Prior art]
One of important element characteristics of a switching element such as a semiconductor element, for example, a fast recovery diode (fast diode) is a switching speed. In order to improve the switching speed of the semiconductor element, for example, a method of shortening the lifetime of the carrier is known. In this method, a heavy metal as a lifetime killer is thermally diffused in a semiconductor substrate to cause crystal defects in the semiconductor substrate, thereby forming a carrier recombination center and shortening the lifetime of the carrier.
[0003]
Examples of such heavy metals as lifetime killer include gold (Au), platinum (Pt), and the like, and an optimum heavy metal is used in accordance with characteristics required for a semiconductor element. For example, when Au is used as a lifetime killer, since Au has a deeper bandgap recombination trap center level than heavy metals such as Pt, the temperature dependence of reverse recovery time is small. For this reason, the reverse recovery time can be made relatively short even at high temperatures, and good switching characteristics can be obtained. Another characteristic is that it exhibits soft recovery characteristics.
[0004]
[Problems to be solved by the invention]
However, when Au is used as a lifetime killer for a semiconductor substrate containing phosphorus as an n-type impurity, there is a problem that variations in forward voltage become large. This is thought to be because the concentration of Au diffused as a lifetime killer locally increases and apparently decreases the impurity concentration in the semiconductor substrate.
[0005]
In particular, when an n-type semiconductor region (for example, a channel stopper) is formed by diffusing phosphorus as an n-type impurity on the surface of the semiconductor substrate, the forward voltage variation increases. Such a phenomenon occurs when Au is used as a lifetime killer, and does not occur when Pt is used as a lifetime killer, for example.
[0006]
Further, when arsenic (As) as an n-type impurity is diffused in the n-type semiconductor region constituting the cathode region, oxygen is easily taken in, and the forward voltage variation becomes significantly large.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor element capable of suppressing variations in forward voltage when gold (Au) is used as a lifetime killer. To do.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor element of the present invention includes a first semiconductor region composed of an n-type conductivity type semiconductor region, and an n-type conductivity type formed by epitaxial growth on one main surface of the first semiconductor region. comprising a second semiconductor region comprising a semiconductor region, a third semiconductor region made of the second predetermined surface area formed on p-type conductivity type semiconductor regions of the semiconductor region, the semiconductor substrate having said first semiconductor In the region, the second semiconductor region, and the third semiconductor region, a lifetime killer made of gold is introduced , phosphorus is diffused into a predetermined surface region of the second semiconductor region, and the first semiconductor region The oxygen concentration is 1.1 × 10 ¹⁸ cm ⁻³ or less.
[0009]
According to this configuration, the semiconductor substrate contains phosphorus, a lifetime killer made of gold is introduced, and the oxygen concentration of the first semiconductor region is 1.1 × 10 ¹⁸ cm ⁻³ or less. For this reason, even if the second semiconductor region is formed on one main surface of the first semiconductor region by epitaxial growth, oxygen does not precipitate on one main surface side of the first semiconductor region, and oxygen diffuses into the second semiconductor region. Not. Therefore, variations in forward voltage are suppressed.
[0011]
Preferably, arsenic is diffused in the first semiconductor region. This is because, when arsenic is diffused in the first semiconductor region, oxygen is easily taken in, and thus the forward voltage variation is likely to be significantly increased, and the remarkable effect of the present invention can be obtained.
[0012]
The semiconductor substrate may further include a field limiting ring formed in a predetermined surface region of the second semiconductor region so as to surround the third semiconductor region. In this case, the depletion layer formed by the pn junction can be extended to the outer peripheral side of the field limiting ring, and the breakdown voltage of the semiconductor element can be increased.
[0013]
The semiconductor substrate may further include a channel stopper formed in a predetermined surface region of the second semiconductor region so as to surround the third semiconductor region via the field limiting ring. In this case, electric field concentration in the depletion layer is prevented, thereby reducing junction leakage current and ensuring stable operation of the semiconductor element. For example, phosphorus is diffused in the channel stopper.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the semiconductor device of the present invention will be described by taking as an example the case of a so-called field limiting ring (FLR) and a fast recovery diode (hereinafter referred to as “diode”) having a channel stopper. FIG. 1 shows a cross-sectional view of the diode of the present embodiment.
[0015]
As shown in FIG. 1, the diode 1 includes a semiconductor substrate 2, an insulating film 3, an upper electrode 4, and a lower electrode 5.
[0016]
The semiconductor substrate 2 includes an n ⁺ -type semiconductor region 6 as a first semiconductor region, an n-type semiconductor region 7 as a second semiconductor region, a p-type semiconductor region 8 as a third semiconductor region, and a field limiting ring ( FLR) 9 and a channel stopper 10.
[0017]
The semiconductor substrate 2 is introduced with gold (Au) as a lifetime killer. Au as a lifetime killer is formed on a predetermined main surface of the semiconductor substrate 2 on which the n ⁺ type semiconductor region 6, the n type semiconductor region 7, the p type semiconductor region 8, the FLR 9, and the channel stopper 10 are formed. It is introduced into the entire depth direction in the semiconductor substrate 2 by vapor deposition and thermal diffusion. Thus, Au is introduced into the semiconductor substrate 2 because Au has a diffusion coefficient large enough to be introduced into the semiconductor substrate 2.
[0018]
The n ⁺ type semiconductor region 6 is composed of an n ⁺ type silicon single crystal substrate and functions as a cathode contact region. The n ⁺ type semiconductor region 6 functions as a starting base material and a supporting member for epitaxially growing the n type semiconductor region 7 on one main surface, for example, the upper surface. For this reason, the n ⁺ type semiconductor region 6 is formed to have a relatively thick thickness, for example, 200 μm to 500 μm. In the n ⁺ -type semiconductor region 6, arsenic as an n-type impurity is diffused at a relatively high concentration such as about 1.0 × 10 ¹⁸ cm ^{−3 to} 1.0 × 10 ²⁰ cm ^−3. It is set higher than 7. In the present embodiment, and a ^{1.0 × 10 19 cm -3 ~8.0 ×} 10 19 cm -3 or so.
[0019]
The oxygen concentration of the n ⁺ type semiconductor region 6 is set to 1.1 × 10 ¹⁸ cm ⁻³ or less, preferably 7.0 × 10 ¹⁷ cm ^{−3 to} 1.1 × 10 ¹⁸ cm ⁻³ . . This is because if the oxygen concentration of the n ⁺ type semiconductor region 6 is lower than 7.0 × 10 ¹⁷ cm ^−3, it becomes difficult to manufacture the n ⁺ type semiconductor region 6. For example, when the production method of the single crystal is the Czochralski method (CZ method), the yield is poor and production cannot be performed. On the other hand, when the oxygen concentration of the n ⁺ -type semiconductor region 6 is higher than 1.1 × 10 ¹⁸ cm ⁻³ , the forward voltage variation cannot be suppressed. In the present embodiment, the oxygen concentration of the n ⁺ type semiconductor region 6 is set to 8.8 × 10 ¹⁷ cm ⁻³ .
[0020]
The n-type semiconductor region 7 is formed on the n ⁺ -type semiconductor region 6. The n-type semiconductor region 7 is formed by a general epitaxial growth method and functions as a cathode region. n-type semiconductor region 7, n-type impurity is diffused in a relatively low concentration as about ^{4.0 × 10 13 cm -3 ~8.0 ×} 10 14 cm -3, from the ^{n +} -type semiconductor region 6 It is composed of an n-type semiconductor region having a low impurity concentration. The thickness of the n-type semiconductor region 7 is 20 μm to 80 μm.
[0021]
The p-type semiconductor region 8 is formed in a predetermined surface region of the n-type semiconductor region 7. The p-type semiconductor region 8 is formed by a general impurity diffusion method. For example, by selectively introducing a p-type impurity (for example, boron) into a predetermined region on the upper surface of the n-type semiconductor region 7, boron is diffused into a predetermined surface region on the upper surface of the n-type semiconductor region 7, A p-type semiconductor region 8 is formed in this predetermined surface region. The diffusion depth of the p-type semiconductor region 8 is 5 μm to 30 μm, and the impurity concentration is about 1.0 × 10 ¹⁷ cm ^{−3 to} 1.0 × 10 ¹⁹ cm ⁻³ . This p-type semiconductor region 8 functions as an anode region of the diode 1.
[0022]
The field limiting ring (FLR) 9 is formed in an annular shape on the upper surface of the n-type semiconductor region 7 so as to surround the p-type semiconductor region 8. The FLR 9 is formed by a general impurity diffusion method. For example, the FLR 9 is formed by introducing the same p-type impurity (for example, boron) as the p-type semiconductor region 8 in a ring shape so as to surround the p-type semiconductor region 8 formed on the upper surface of the n-type semiconductor region 7. Is done. The FLR 9 is formed, for example, by diffusing the same p-type impurity (for example, boron) in the step of forming the p-type semiconductor region 8. For this reason, FLR 9 and p-type semiconductor region 8 have substantially the same diffusion depth, impurity concentration, and the like.
[0023]
The FLR 9 can widen the depletion layer formed by the pn junction between the n-type semiconductor region 7 and the p-type semiconductor region 8 to the outer peripheral side of the FLR 9, and increase the breakdown voltage of the diode 1. In the present embodiment, as shown in FIG. 1, two FLRs 9 are formed. However, as the number of FLRs 9 is increased, the diode 1 can have a higher breakdown voltage. Accordingly, it is preferable to form a predetermined number of FLRs 9.
[0024]
The channel stopper 10 is formed in an annular shape on the outer edge of the upper surface of the n-type semiconductor region 7 so as to surround the p-type semiconductor region 8 via the FLR 9. The channel stopper 10 introduces phosphorus as an n-type impurity in a ring shape so as to surround the p-type semiconductor region 8 via the FLR 9 at the outer edge of the upper surface of the n-type semiconductor region 7 by a general impurity diffusion method. It is formed by doing. For this reason, the impurity concentration of the channel stopper 10 is higher than the impurity concentration of the n-type semiconductor region 7 such as about 1.0 × 10 ¹⁷ cm ^{−3 to} 1.0 × 10 ¹⁹ cm ⁻³ . The diffusion depth of the channel stopper 10 is 5 μm to 30 μm. As described above, the channel stopper 10 is formed on the outer edge of the upper surface of the n-type semiconductor region 7 to prevent the channel phenomenon near the surface, thereby reducing the surface leakage current and ensuring the stable operation of the diode 1.
[0025]
The insulating film 3 is formed so as to cover the upper surfaces of the n-type semiconductor region 7, the FLR 9 and the channel stopper 10 and the outer peripheral side of the upper surface of the p-type semiconductor region 8. In the present embodiment, for example, a silicon oxide film formed by thermal oxidation is used for the insulating film 3.
[0026]
The upper electrode 4 is formed on the upper surface of the p-type semiconductor region 8. The upper electrode 4 constitutes an anode electrode made of a metal film, and is electrically connected to the p-type semiconductor region 8 (anode region).
[0027]
The lower electrode 5 is formed on the lower surface of the n ⁺ type semiconductor region 6. The lower electrode 5 constitutes a cathode electrode made of a metal film, and is electrically connected to the n ⁺ type semiconductor region 6 (cathode contact region).
[0028]
The diode 1 configured as described above has a channel stopper 10 in which gold (Au) as a lifetime killer is introduced into the semiconductor substrate 2 and phosphorus is diffused on the upper surface of the semiconductor substrate 2 (n-type semiconductor region 7). is formed, arsenic to the ^{n +} -type semiconductor region 6 is diffused, the oxygen concentration of the ^{n +} -type semiconductor region 6 is ^{8.8 × 10 17 cm -3, 1.1} × 10 18 cm -3 or less Therefore, variations in forward voltage can be suppressed. The reason why the forward voltage variation can be suppressed in this manner is that the forward voltage is considered to vary for the following reason.
[0029]
If the oxygen concentration in the n ⁺ -type semiconductor region 6 is more than 1.1 × ¹⁰ 18 ^{cm -3,} an n-type semiconductor region 7 to the upper surface of the ^{n +} -type semiconductor region 6 when the epitaxial growth, the ^{n +} -type semiconductor region 6 Oxygen precipitates on the upper surface side. In particular, the arsenic n ⁺ -type semiconductor region 6 is diffused, since oxygen is incorporated easily into n ⁺ -type semiconductor region 6, the oxygen is likely to be deposited on the upper surface of the n ⁺ -type semiconductor region 6. The precipitated oxygen is taken into the epitaxial growth layer and diffuses into the n-type semiconductor region 7. The diffused oxygen is contracted by self-interstitial atoms formed by diffusion of phosphorus in the n-type semiconductor region 7. In particular, when the channel stopper 10 in which phosphorus is diffused is formed in the surface region of the n-type semiconductor region 7, self-interstitial atoms are easily formed in the n-type semiconductor region 7, and this tendency becomes remarkable. As a result, more Au is attracted to the n-type semiconductor region 7, and the substitutional Au concentration in the n-type semiconductor region 7 rises to the solid solution limit of Au. This Au functions as a p-type impurity in the n-type semiconductor region 7. For this reason, the n-type impurity concentration of the n-type semiconductor region 7 is practically lowered, the series resistance is increased, and as a result, the forward voltage variation is considered to increase.
[0030]
In this embodiment, ^{n +} -type oxygen concentration of the semiconductor region 6 is set to 8.8 × ¹⁰ 17 ^{cm -3,} since 1.1 × ¹⁰ 18 ^{cm -3} or less, the ^{n +} -type semiconductor region 6 Precipitation of oxygen on the upper surface side and incorporation of oxygen into the epitaxial growth layer are suppressed. For this reason, oxygen does not diffuse into the n-type semiconductor region 7, and variations in forward voltage can be suppressed.
[0031]
In order to confirm the effect of the present invention, the forward voltage variation was determined for the diode 1 in which the oxygen concentration of the n ⁺ type semiconductor region 6 was changed. In the present embodiment, the forward voltage variation was calculated as follows. First, ten wafers having substantially the same oxygen concentration in the n ⁺ type semiconductor region 6 are prepared. Next, the forward voltage of the diode formed in each prepared wafer is measured, and the average value of the forward voltage of each wafer is calculated. Then, the difference between the maximum value and the minimum value of the calculated average value was obtained, and this value was used as the forward voltage variation. The results are shown in FIG.
[0032]
As shown in FIG. 2, when the oxygen concentration of the n ⁺ -type semiconductor region 6 is 1.1 × 10 ¹⁸ cm ⁻³ or less, the forward voltage variation can be suppressed to 0.1 V or less. Thus, when the forward voltage variation is 0.1 V or less, the diode 1 can be sufficiently put into practical use, and the forward voltage variation is not a problem. On the other hand, when the oxygen concentration of the n ⁺ type semiconductor region 6 exceeds 1.1 × 10 ¹⁸ cm ⁻³ , the forward voltage variation exceeds 0.1 V, and the diode 1 cannot be put to practical use.
[0033]
When the oxygen concentration of the n ⁺ type semiconductor region 6 is set to 8.8 × 10 ¹⁷ cm ⁻³ which is 1.1 × 10 ¹⁸ cm ⁻³ or less as in the present embodiment, the forward voltage Variation is 0.006V, and variations in forward voltage can be suppressed. On the other hand, when the oxygen concentration of the n ⁺ type semiconductor region 6 exceeds 1.1 × 10 ¹⁸ cm ⁻³ , for example, 1.5 × 10 ¹⁸ cm ⁻³ , the forward voltage variation reaches 0.14V. As a result, the diode 1 cannot be put to practical use.
[0034]
As described above, according to the present embodiment, since the oxygen concentration of the n ⁺ type semiconductor region 6 is set to 1.1 × 10 ¹⁸ cm ⁻³ or less, variations in forward voltage can be suppressed. .
[0035]
According to the present embodiment, since the FLR 9 is formed in an annular shape so as to surround the p-type semiconductor region 8 on the upper surface of the n-type semiconductor region 7, it is possible to increase the breakdown voltage of the diode 1.
[0036]
According to the present embodiment, the channel stopper 10 is formed in an annular shape on the outer edge of the upper surface of the n-type semiconductor region 7 so as to surround the p-type semiconductor region 8 via the FLR 9. Operation can be secured.
[0037]
In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, other embodiments applicable to the present invention will be described.
[0038]
In the above embodiment, the present invention has been described by taking as an example the case where the channel stopper 10 in which phosphorus is diffused is formed on the upper surface (surface region) of the n-type semiconductor region 7. However, for example, the channel stopper 10 is not formed. Phosphorus may be diffused into the semiconductor substrate 2 so that phosphorus is introduced into the semiconductor substrate 2. Also in this case, the variation in the forward voltage tends to be large, and the variation in the forward voltage can be suppressed by the present invention.
[0039]
In the above embodiment, the invention has been described a case where the diffusing arsenic into n ⁺ -type semiconductor region 6 as an example, may contain antimony in the n ⁺ -type semiconductor region 6. However, if arsenic is contained in the n ⁺ type semiconductor region 6, oxygen can be easily taken in, so that the operational effect of the present invention is remarkably obtained.
[0040]
In the above embodiment, the present invention has been described by taking the case where the FLR 9 is formed on the upper surface of the n-type semiconductor region 7 as an example. However, for example, the FLR 9 may not be formed.
[0041]
【The invention's effect】
As described above, according to the present invention, it is possible to suppress variations in forward voltage when gold is introduced as a lifetime killer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a diode according to an embodiment of the present invention.
FIG. 2 is a graph showing the relationship between the oxygen concentration in the n ⁺ type semiconductor region and the forward voltage variation according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Diode 2 Semiconductor substrate 3 Insulating film 4 Upper electrode 5 Lower electrode 6 n ⁺ type semiconductor region 7 n type semiconductor region 8 p type semiconductor region 9 Field limiting ring (FLR)
10 Channel stopper

Claims (5)

a first semiconductor region comprising an n-type conductivity type semiconductor region;
A second semiconductor region comprising an n-type conductivity type semiconductor region formed by epitaxial growth on one main surface of the first semiconductor region;
A semiconductor substrate having a third semiconductor region formed of a p-type conductivity type semiconductor region formed in a predetermined surface region of the second semiconductor region,
A lifetime killer made of gold is introduced into the first semiconductor region, the second semiconductor region, and the third semiconductor region ,
Phosphorus is diffused into a predetermined surface region of the second semiconductor region;
The semiconductor element, wherein an oxygen concentration of the first semiconductor region is 1.1 × 10 ¹⁸ cm ⁻³ or less. The semiconductor device according to claim 1, wherein arsenic is diffused in the first semiconductor region. The said semiconductor substrate is further equipped with the field limiting ring formed in the predetermined surface area | region of the said 2nd semiconductor region so that the said 3rd semiconductor region may be surrounded, The Claim 1 or 2 characterized by the above-mentioned. The semiconductor element as described. The semiconductor substrate further includes a channel stopper formed in a predetermined surface region of the second semiconductor region so as to surround the third semiconductor region via the field limiting ring. The semiconductor device according to claim 3 . The semiconductor element according to claim 4 , wherein phosphorus is diffused in the channel stopper.

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