JP2003124477A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element capable of suppressing irregularity in a reverse current. SOLUTION: A diode 1 has a semiconductor substrate 2, a n<-> -type semiconductor layer 3 and a p<+> -type semiconductor region 4. The substrate 2 is constituted of an n<+> -type silicon single crystal substrate in which orientation of the upper surface is (100). The layer 3 is formed by an epitaxially growing method on the substrate 2, comprising an n<-> -type semiconductor layer of orientation (100). The layer 3 is formed in 30 μm or more. The region 4 is formed on the predetermined region of the layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a pn junction structure.

[0002]

2. Description of the Related Art A semiconductor element such as a diode has electrodes formed on the upper surface and the lower surface of a semiconductor substrate so that a current flows in the thickness direction of the semiconductor substrate. As such a semiconductor element, there are a pn junction structure and a Schottky barrier structure. However, since a semiconductor element having a pn junction structure has a characteristic of being less likely to be destroyed by a high voltage in the reverse direction, a pn junction for high breakdown voltage is used. A semiconductor device having a structure is used.

A semiconductor element having a pn junction structure is, for example, an n-type semiconductor element.
^A semiconductor substrate made of ⁺ type semiconductor, and n formed on the upper surface of the semiconductor substrate by a general epitaxial growth method.
^{A −} type semiconductor region, a P type semiconductor region formed on the upper surface of the n ⁻ type semiconductor region by a general impurity diffusion method,
An anode electrode formed on the upper surface of the semiconductor substrate and electrically connected to the P-type semiconductor region, and n ^{+ on} the lower surface of the semiconductor substrate.
Type cathode electrode electrically connected to the semiconductor substrate,
Is equipped with.

Further, for example, a field limiting ring (FLR) formed in a ring shape so as to surround the P-type semiconductor region is provided on the outer peripheral side of the P-type semiconductor region on the upper surface of the n ⁻ -type semiconductor region, and n ^The depletion layer formed by the pn junction between the ⁻ type semiconductor region and the P type semiconductor region is expanded to the outer peripheral side of the FLR to increase the breakdown voltage of the semiconductor element.

By the way, in such a diode, a silicon single crystal substrate in which the principal plane of the substrate is the (111) plane is used as the semiconductor substrate. Further, since the n ⁻ type semiconductor region on the semiconductor substrate is formed on the upper surface of the semiconductor substrate by the epitaxial growth method, the plane orientation also becomes the (111) plane.

[0006]

However, if the plane orientation is (1
The reverse current (leakage current) tends to be large in the diode using the 11) plane silicon single crystal substrate, and as a result, the reverse current tends to vary widely. In particular, when the thickness of the n ⁻ type semiconductor region is increased, the reverse current and the reverse current variation are likely to increase. FIG. 4 shows variations in the reverse current when the thickness of the n ⁻ type semiconductor region is changed (the maximum value, the minimum value, and the average value of the reverse current).
Is shown in the graph. As shown in FIG. 4, when the thickness of the n ⁻ type semiconductor region is increased, the maximum value of the reverse current is increased, and the variation of the reverse current is increased. In particular, when the thickness of the n ⁻ type semiconductor region is 30 μm or more, the maximum value of the reverse current rapidly increases, and the difference between the maximum value and the minimum value of the reverse current becomes 1000 times or more. As described above, when the variation in the reverse current becomes large, the reverse characteristic of the diode becomes unstable.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor element capable of suppressing the variation in reverse current. Another object of the present invention is to provide a semiconductor device capable of suppressing reverse current. A further object of the present invention is to provide a semiconductor element capable of stably achieving a high breakdown voltage while suppressing variations in reverse current.

[0008]

In order to achieve the above object, a semiconductor device of the present invention includes a first conductivity type silicon substrate and a first conductivity type silicon substrate having a lower impurity concentration than the silicon substrate. A conductive silicon semiconductor layer,
Formed in a predetermined region on the upper surface of the silicon semiconductor layer,
Second for forming a pn junction at the interface with the silicon semiconductor layer
A conductive type silicon semiconductor region, and the plane orientations of the upper surface of the silicon substrate and the silicon semiconductor layer are (10
0) surface.

According to this structure, the plane directions of the upper surface of the silicon substrate and the silicon semiconductor layer are the (100) plane. The surface orientations of the upper surface of the silicon substrate and the silicon semiconductor layer are (1
Because of the (00) plane, stacking faults in the vertical direction of the silicon substrate, which have a large effect on the reverse current, are less likely to grow.
Therefore, even if the thickness of the silicon semiconductor layer is increased, the reverse current is unlikely to be large, and the reverse current variation is unlikely to be large. Therefore, it is possible to suppress the reverse current and variations in the reverse current.

The silicon semiconductor layer preferably has a thickness of at least 30 μm. This is because, when the thickness of the silicon semiconductor layer is 30 μm or more, the reverse current and the reverse current generally tend to increase in variation, which is suitable for the present invention.

The silicon semiconductor layer is preferably formed by epitaxial growth on the silicon substrate. In this case, the plane orientation of the silicon semiconductor layer is the same as the plane orientation of the upper surface of the silicon substrate.

A second annularly formed on the upper surface of the silicon semiconductor layer so as to surround the silicon semiconductor region.
A conductive type field limiting ring may be further provided. In this case, the depletion layer formed by the pn junction can be expanded to the outer peripheral side of the field limiting ring, and the breakdown voltage of the semiconductor element can be increased.

An equipotential ring formed in a ring shape so as to surround the silicon semiconductor region via the field limiting ring may be further provided on the upper surface of the silicon semiconductor layer. In this case, the depletion layer formed by the pn junction can be stably and satisfactorily spread in the lateral direction of the semiconductor element, and the depletion layer is prevented from spreading to the side surface of the semiconductor element, so that the withstand voltage of the semiconductor element can be increased. It can be achieved stably.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a so-called field limiting ring (FLR) of a semiconductor device of the present invention will be described.
A case of a high breakdown voltage diode having the above will be described as an example. FIG. 1 shows a cross-sectional view of the diode of this embodiment.

As shown in FIG. 1, the diode 1 includes a semiconductor substrate 2, an n ⁻ type semiconductor layer 3, and a P ⁺ type semiconductor region 4.
A field limiting ring (FLR) 5, an equipotential ring (EQR) 6, an insulating film 7, and an upper electrode 8.
And a lower electrode 9. In addition, in the semiconductor substrate 2, the n ⁻ type semiconductor layer 3, and the P ⁺ type semiconductor region 4,
As a life time killer, heavy metals such as Au are diffused.

The semiconductor substrate 2 has a first conductivity type, for example, n.
Type impurities (eg, antimony) are 1.0 × 10 ¹⁸
It is composed of an n ⁺ -type silicon single crystal substrate introduced at a relatively high concentration such as about cm ^{−3 to} 5.0 × 10 ¹⁸ cm ⁻³ . This semiconductor substrate 2 functions as a cathode contact region. As the semiconductor substrate 2, a silicon single crystal substrate having an upper surface plane orientation of (100) plane is used. That is, the semiconductor substrate 2 functioning as the cathode contact region is composed of a silicon single crystal substrate whose upper surface has a plane orientation of (100) plane indicated by Miller index.

The n ⁻ type semiconductor layer 3 is formed on the semiconductor substrate 2. The n ⁻ type semiconductor layer 3 is formed by a general epitaxial growth method and functions as a cathode region. The n ⁻ type semiconductor layer 3 has a first conductivity type, for example,
The n-type impurity (for example, phosphorus) is 5.0 × 10 ¹³ c
It is composed of an n ⁻ type semiconductor layer which is introduced at a relatively low concentration such as m ^{−3 to} 5.0 × 10 ¹⁴ cm ^{−3 and} has a lower impurity concentration than the semiconductor substrate 2.

The n ^-- type semiconductor layer 3 is formed on the semiconductor substrate 2
Since it is formed by epitaxial growth on top,
Inheriting the plane orientation of the upper surface of the semiconductor substrate 2, the semiconductor substrate 2
Is formed so that the surface orientation is the same as the upper surface of the. Therefore, the plane orientation of the n ⁻ type semiconductor layer 3 is the same as that of the upper surface of the semiconductor substrate 2.
It is the (100) plane indicated by the Miller index.

By the way, the value of the reverse current (leakage current) depends on, for example, stacking faults generated by repeated thermal oxidation at high temperature. In particular, the value of the reverse current is greatly influenced by the defects generated in the direction perpendicular to the orientation flat (facet). Therefore, when the defects generated in the vertical direction grow, the value of the reverse current and the variation of the reverse current increase.

This stacking fault is generated in the vicinity of the surface of the silicon wafer by, for example, thermally oxidizing the silicon wafer at a high temperature of 1200 ° C. When the direction of the defect and the direction of the crystal axis coincide with each other, the stacking fault with respect to the wafer It is considered that growth is caused by each stress such as compressive stress, tensile stress, shear stress (for example, external stress generated by a thermal oxide film or metal or internal stress generated by impurity diffusion).

Here, when the plane orientation is the (111) plane, this crystal axis intersects the crystal axis in the direction perpendicular to the orientation flat and 60 ° with respect to this crystal axis.
There are three crystal axes with one crystal axis. On the other hand, when the plane orientation is the (100) plane, this crystal axis has two crystal axes that intersect at 45 ° with respect to the orientation flat. Therefore, when the plane orientation is the (111) plane, the direction of the defect that most affects the value of the reverse current (vertical direction).
And the direction of the crystal axis coincide with each other and the plane orientation is the (100) plane, the crystal axis direction does not coincide with the crystal axis direction.

Therefore, if the plane orientation of the upper surface of the semiconductor substrate 2 and the n ^-- type semiconductor layer 3 is the (111) plane, the defects in the vertical direction grow and the value of the reverse current increases, and the reverse current increases. Also increases. On the other hand, if the plane orientation of the upper surface of the semiconductor substrate 2 and the n ⁻ -type semiconductor layer 3 is the (100) plane, it becomes difficult for defects in the vertical direction to grow.

In the present embodiment, the plane orientation of the upper surface of the semiconductor substrate 2 is the (100) plane, and the n ⁻ type semiconductor layer 3 is also used.
Since the plane orientation of is the (100) plane, the direction of the defect (vertical direction) that most affects the value of the reverse current does not match the crystal axis direction. Does not increase, and variation in reverse current is suppressed.

The thickness of the n ⁻ type semiconductor layer 3 is preferably 30 μm or more. The thickness of the n ⁻ type semiconductor layer 3 is 30 μ.
This is because the reverse current tends to increase and the reverse current tends to fluctuate when m or more, which is suitable for the present invention that suppresses the reverse current and the variation in the reverse current. However, when the thickness of the n ⁻ type semiconductor layer 3 becomes too thick, various characteristics of the diode 1 are deteriorated.
The thickness of the ⁻ type semiconductor layer 3 is preferably 30 μm to 110 μm, and more preferably 30 μm to 80 μm.

P⁺The type semiconductor region 4 is n⁻Type semiconductor layer 3
Is formed in a predetermined area. P ⁺Type semiconductor region 4
Are formed by a general impurity diffusion method. example
For example, if a p-type impurity (for example, boron) is added to n⁻Type semiconductor layer
By selectively introducing into a predetermined area of the upper surface of 3,
n⁻Is diffused into a predetermined region on the upper surface of the type semiconductor layer 3,
P in a predetermined area⁺The type semiconductor region 4 is formed. This P
⁺The type semiconductor region 4 constitutes the anode region of the diode 1.
To achieve. In the present embodiment, P⁺Depth of type semiconductor region 4
(Diffusion depth) n⁻16 μm from the top surface of the semiconductor layer 3
And

Field limiting ring (FLR)
5 is a P ⁺ type semiconductor region 4 on the upper surface of the n ⁻ type semiconductor layer 3.
Is formed in an annular shape so as to surround the. FLR5 is
It is formed by a general impurity diffusion method. For example,
P ⁺ -type semiconductor region 4 and the same p-type impurity (e.g., boron) and, n ^- -type semiconductor layer 3 in the top surface ^{P +} -type semiconductor regions 4
The FLR5 is formed by introducing it in a ring shape so as to surround. The FLR 5 is formed by diffusing the same p-type impurity (for example, boron) in the step of forming the P ⁺ -type semiconductor region 4, for example. FLR5 is
The depletion layer formed by the pn junction between the n ⁻ type semiconductor layer 3 and the P ⁺ type semiconductor region 4 can be expanded to the outer peripheral side of the FLR 5 to increase the breakdown voltage of the diode 1. In the present embodiment, as shown in FIG. 1, two FLRs 5 are formed. However, as the number of FLRs 5 is increased, the withstand voltage of the diode 1 can be made higher, so that the withstand voltage required for the diode 1 can be increased. Accordingly, it is preferable to form a predetermined number of FLR5.

The equipotential ring (EQR) 6 includes an n ⁺ type semiconductor region 6a and a metal film 6b. The n ⁺ -type semiconductor region 6 a is provided on the outer edge of the upper surface of the n ⁻ -type semiconductor layer 3 with FL.
It is formed in a ring shape so as to surround the P ⁺ type semiconductor region 4 via R5. The n ⁺ -type semiconductor region 6a is made to have a first conductivity type, for example, n-type impurity (for example, phosphorus) by an ordinary impurity diffusion method at the outer edge of the upper surface of the n ⁻ -type semiconductor layer 3 via the FLR 5. It is formed by introducing it in a ring shape so as to surround the P ⁺ type semiconductor region 4. The metal film 6b is formed in a ring shape on the outer edge of the upper surface of the n ⁺ type semiconductor region 6a (n ⁻ type semiconductor layer 3). Metal film 6b
Is formed from, for example, a vapor-deposited layer of aluminum, and n ⁺
It is electrically connected to the type semiconductor region 6a. EQR6
Has a function of stabilizing the charge on the surface of the insulating film 7 and a function of preventing the depletion layer from spreading to the outer periphery. Since the FLR 5 and the EQR 6 are formed in this manner, the depletion layer can stably and satisfactorily spread in the lateral direction of the diode 1, and the depletion layer is prevented from spreading to the side surface of the diode 1 and the diode 1 The high breakdown voltage can be stably achieved.

The insulating film 7 is composed of the n ^-- type semiconductor layer 3 and the FLR.
5, the upper surface of the P ⁺ -type semiconductor region 4 on the outer peripheral side, and n
It is formed so as to cover the inner peripheral side of the ⁺ type semiconductor region 6a. In the present embodiment, for example, a silicon oxide film formed by thermal oxidation is used as the insulating film 7.

The upper electrode 8 is formed on the upper surface of the P ⁺ type semiconductor region 4. The upper electrode 8 constitutes an anode electrode made of a metal film, and is electrically connected to the P ⁺ type semiconductor region 4 (anode region).

The lower electrode 9 is formed on the lower surface of the semiconductor substrate 2. The lower electrode 9 constitutes a cathode electrode made of a metal film, and the semiconductor substrate 2 (cathode contact region)
Electrically connected to.

The diode 1 constructed as described above is
The plane orientation of the upper surface of the semiconductor substrate 2 is the (100) plane, and the plane orientation of the n ⁻ type semiconductor layer 3 is the (100) plane.
Therefore, the reverse current, which is the leakage current in the reverse bias state, is suppressed, and the fluctuation of the reverse current is suppressed.

In order to confirm the effect of the present invention, regarding the diode 1 in which the thickness of the n ⁻ type semiconductor layer 3 is changed, n ⁻
The reverse current (leakage current) is measured for each thickness of the semiconductor layer 3, and the maximum value (MAX) and the minimum value (MIN) of the reverse current are measured.
And the average value (AVE) was determined. The results are shown in FIGS. 2 and 3. Further, FIG. 3 also shows the difference (MAX-MIN) between the maximum value and the minimum value of the reverse current. For comparison, the maximum value of the reverse current of the conventional case (a diode in which the upper surface of the semiconductor substrate 2 and the n ⁻ -type semiconductor layer 3 have a (111) surface orientation),
The minimum value, MAX-MIN, is shown in FIG. 3 as a comparative example.

As shown in FIG. 2 and FIG. 3, the semiconductor substrate 2 whose upper surface has a plane orientation of (100) and whose surface orientation is (100)
By using the n ⁻ type semiconductor layer 3 on the surface, the maximum value of the reverse current is greatly reduced. For this reason, the difference between the maximum value and the minimum value of the reverse current becomes small, and the fluctuation of the reverse current is suppressed. For example, the thickness of the n ⁻ type semiconductor layer 3 is 3
In the case of 0 μm, it is 0.1 μA in the embodiment, whereas
In the conventional comparative example, it is 179.97 μA. As described above, by using the semiconductor substrate 2 having the (100) plane as the plane orientation and the n ⁻ type semiconductor layer 3 having the (100) plane as the plane orientation, the difference between the maximum value and the minimum value of the reverse current can be reduced. About 1/18
It was confirmed that the value could be set to 00 and the variation in the reverse current could be suppressed.

As described above, according to the present embodiment, by using the semiconductor substrate 2 having the plane orientation of (100) plane and the n ⁻ type semiconductor layer 3 having the plane orientation of (100) plane, The maximum value of the reverse current is greatly reduced, and the reverse current is suppressed. For this reason, the difference between the maximum value and the minimum value of the reverse current becomes small, and the fluctuation of the reverse current is suppressed.

According to the present embodiment, the n ^-- type semiconductor layer 3
On the upper surface of the FL so as to surround the P ⁺ type semiconductor region 4.
Since R5 is formed in a ring shape, the depletion layer formed by the pn junction between the n ⁻ type semiconductor layer 3 and the P ⁺ type semiconductor region 4 is expanded to the outer peripheral side of the FLR5 to increase the breakdown voltage of the diode 1. Can be achieved.

According to the present embodiment, the n ^-- type semiconductor layer 3
To the outer edge of the upper surface of the P ⁺ -type semiconductor region 4 via the FLR 5.
Since the EQR6 is formed in a ring shape so as to surround, the EQR6 can stabilize the charge on the surface of the insulating film 7 and prevent the depletion layer from spreading to the outer periphery. In this way, since FLR5 and EQR6 are formed,
The depletion layer can stably and satisfactorily spread in the lateral direction of the diode 1, and the depletion layer can be prevented from spreading to the side surface of the diode 1, so that the high breakdown voltage of the diode 1 can be stably achieved.

The present invention is not limited to the above embodiment, and various modifications and applications are possible. Hereinafter, another embodiment applicable to the present invention will be described.

In the above embodiment, the present invention has been described by taking the case of the high breakdown voltage diode 1 having the field limiting ring 5 as an example. However, the semiconductor substrate 2, the n ⁻ type semiconductor layer 3, and the P ⁺ type semiconductor region are described. And the plane orientation of the upper surface of the semiconductor substrate 2 and the n ⁻ -type semiconductor layer 3 is the (100) plane. For example, the diode 1 in which the FLR 5 and the EQR 6 are not formed may be used.

In the above embodiment, the present invention has been described by taking the case where the n ⁻ type semiconductor layer 3 is formed by epitaxial growth on the semiconductor substrate 2 as an example.
On the semiconductor substrate 2 of (0) plane, the plane orientation is n of (100) plane.
^It suffices that the ⁻ type semiconductor layer 3 is formed, and the method for manufacturing the n ⁻ type semiconductor layer 3 is not limited to the epitaxial growth method.

In the above embodiment, the present invention has been described by taking the case where the first conductivity type is n-type and a semiconductor substrate is used as the semiconductor substrate 2 as an example. The conductivity type may be reversed. Further, although the present invention has been described in the above embodiment in the case where the diode 1 is manufactured, the semiconductor element may be any semiconductor element having a pn junction structure.

In the above-described embodiment, the present invention has been described by exemplifying the case where a heavy metal (Au or the like) is diffused as the lifetime killer, but the present invention can be applied to a semiconductor element in which the lifetime killer is not diffused. However, when the lifetime killer is diffused, the variation of the reverse current becomes larger. Therefore, the present invention is applied to a semiconductor element in which the lifetime killer is diffused, and a remarkable effect can be obtained.

[0042]

As described above, according to the present invention,
Variation in reverse current can be suppressed.

[Brief description of drawings]

FIG. 1 is a sectional view of a diode according to an embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the thickness of the n ⁻ type semiconductor layer and the reverse current according to the embodiment of the present invention.

FIG. 3 is a table showing a relation between an n ⁻ type semiconductor layer according to an embodiment of the present invention and a conventional reverse current.

FIG. 4 is a graph showing the relationship between the thickness of a conventional n ⁻ type semiconductor layer and the reverse current.

[Explanation of symbols]

1 diode 2 semiconductor substrate 3 n ⁻ type semiconductor layer 4 P ⁺ type semiconductor region 5 field limiting ring (FLR) 6 equipotential ring (EQR) 7 insulating film 8 upper electrode 9 lower electrode

Claims (5)

[Claims] 1. A first conductivity type silicon substrate, a first conductivity type silicon semiconductor layer formed on the silicon substrate and having an impurity concentration lower than that of the silicon substrate, and a predetermined region on an upper surface of the silicon semiconductor layer. Formed in
Second for forming a pn junction at the interface with the silicon semiconductor layer
And a silicon semiconductor region of conductivity type, wherein the plane orientations of the upper surface of the silicon substrate and the silicon semiconductor layer are (100) planes. 2. The semiconductor device according to claim 1, wherein the silicon semiconductor layer has a thickness of at least 30 μm. 3. The silicon semiconductor layer is formed by epitaxial growth on the silicon substrate.
The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 4. A second annularly formed on the upper surface of the silicon semiconductor layer so as to surround the silicon semiconductor region.
4. The semiconductor device according to claim 1, further comprising a conductive type field limiting ring. 5. The equipotential ring formed in an annular shape on the upper surface of the silicon semiconductor layer so as to surround the silicon semiconductor region via the field limiting ring is further included. 4. The semiconductor device according to item 4.