JPS60130135A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To flatten the surface of a field oxide film produced in the peripheral portion of an Si substrate and to obtain a high-density semiconductor device, by a method in which an SiO2 film is adhered on the surface of the substrate, an Si3N4 film is provided only in the central portion thereof, impurity ions are implanted with the use of the Si3N4 film as a mask to produce inversion preventing regions; SiO2 films are adhered only on the both sides of the Si3N4 film, and the substrate is heat treated with the use of these SiO2 films as masks. CONSTITUTION:An SiO2 film 12 is adhered on the whole surface of an Si substrate 11 and provided in the central portion with an Si3N4 film 14. Impurity ions are implanted into the substrate with the use of the film 14 as a mask to form inversion preventing regions 15 on the both sides of the film 14 in the uppermost layer of the substrate 11. SiO2 films 17 are adhered only on the side faces of the film 14 and the substrate is heat treated with the films 17 used as masks to expand and disperse the regions 15 downward, while thick field oxide films 18 are produced on those regions. After that, a resist film 19 to be used as a flattening material is applied over there and etched to removed the film 19 together with the film 17. Thus, the surface of the field oxide films 18 connected to a film 20 consisting of the SiO2 film 12 is flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device in which the conversion difference during the formation of a field oxide film is reduced by l''.

[Technical background of the invention]

As is well known, one of the well-known element isolation technologies is LOC using a Si3N4 pattern as a mask.
O8 (Local Oxidation ofSili
con) method.

Conventionally, semiconductor devices such as MO8I transistors have been manufactured using the LOCO8 method as shown in FIGS. 1(a) and 1(b). First, for example, a S i s N4 pattern 3 is formed on a semiconductor substrate l with an insulating film 2 interposed therebetween. Next, using this S 13 N4 pattern 3 as a mask, impurities for field inversion prevention are ion-implanted into the surface of the substrate 1 to form inversion prevention impurity regions 4 (first
Figure (a) shown). Next, the Si, N4 pattern 3
Selective oxidation is performed using the field oxide film 5 as a mask.
(as shown in FIG. 1(b)). Although not shown, after sequentially removing the 5isN4 pattern 3 and the insulating film 2 by a conventional method and forming a gate insulating film on the surface of the substrate 1 surrounded by the field oxide film 5, the gate electrode, source, drain region, etc. A MOS transistor is manufactured by forming a MOS transistor. However, according to such a manufacturing method, firstly, the anti-inversion impurity region 4 can be formed in a self-aligned manner with respect to the S i , N, pattern 3, and secondly, the inversion prevention impurity region 4 can be formed in a region of about 45 mm in the thickness direction of the field oxide film 5. % penetrates into the substrate 1, so it is widely used because it can flatten the entire surface.

[Back (technical issues)]

However, the conventional technique has the disadvantage that the distance from the edge of the 5tsN4 pattern 3 to the edge of the field oxide film 5, that is, the conversion difference (ΔW) becomes large, as shown in FIG. 1(b).

The reason for this is that when performing all selective oxidation, as shown in Figure 2, (
This is because the oxidizing agent 6 diffuses from the edge of the Si3N4 pattern 3 and goes around to the substrate 1 below the S1sN4 backbone 3. Actually, ΔWz is 0.5 μm. Therefore, to obtain a separation region 7f of 2 μm: 5
t3N, a pattern is required, which becomes an obstacle to high density and high integration of elements.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its entire purpose is to provide a method for manufacturing a conductor device that achieves high density and high integration of elements by reducing conversion differences. .

[Summary of the invention]

According to the present invention, a first .DELTA. After forming a second mask material and using these mask materials to release the oxidation treatment to form field oxidation Mk, the first
After removing only the mask material and forming a flattening material on the entire surface, the flattening material and the second mask material are anisotropically etched,
After that, by removing the flattening material, LOCO8
In addition to maintaining the advantage of flatness in the law,
The aim is to achieve higher density and higher integration of elements.

[Embodiments of the invention]

Hereinafter, a case in which the present invention is applied to the manufacture of MO3I transistors will be described with reference to FIGS. 3(a) to 3(g).

[1] First, for example, a thermal oxide film (insulating H'J) 12 with a thickness of about 100 OA is formed by thermal oxidation on a P-type silicon substrate 11.
After forming VC, normal pressure CVD method is applied on this thermal oxide film No. 2.
j,! 7. jjlj, @approx. 1 (100A, (DSi
sN<de13 was deposited (as shown in FIG. 3(a)). Next, this S is N41JM 7? Si as the first mask material by photolithography process,
However, Si3N, JI
! CF of 13 etching UM direction etching
, /H2 gas atmosphere. Thereafter, impurity ions for preventing field inversion were ion-implanted into the surface of the substrate 1 using the Si, N4 vacuum 14 as a mask to form an impurity region 15 for preventing inversion. Next, 4P (coating) 16 was deposited on the SiO to a thickness of about 500 OA by atmospheric pressure CVD on the entire surface (as shown in FIG. 3(b)). After that,
This 5i02 film 16 was subjected to anisotropic etching on the entire surface in a CFt/Hz gas atmosphere. As a result, SiO, +Baku]/17 as the second mask material remained only on the side wall of Si, N, Bakuno 4, which had a large film thickness. This was confirmed by observation using a scanning electronic camera.

[11] Next, the Si3N4 patterns 14 and 5i0
Using the second pattern 17 as a mask, selective oxidation was performed by combustion oxidation at 1000'O to form a field oxide film 18. At this time, since the film thickness of the 5i02 backcoon 17 on the side wall of the Si3N4 pattern 14 is small, the 5ilN4 pattern 4
The moth of the lower blade prevents the oxidizing agent from diffusing into the plate 11, resulting in S i3
The extension of the field oxide film 18 below the N'4 pattern 14 has been suppressed. This also applies to scanning electron microscopes! This was confirmed by viewing the cherry blossoms using 7 mirrors. Subsequently, the Sia N4 backbone 14 was subjected to plasma etching in a CF gas atmosphere, and the 5itOz pattern 17 remained integrated with the field oxide film J8. (Illustrated). Next, a resist film J9 as a planarizing material was applied to the entire surface to a thickness of about 500 OA (as shown in FIG. 3(e)). Shikuru Ridge, this resist% 1
Etching was performed on the entire surface in a 9'x CF4 gas atmosphere with a selectivity ratio of 1 to the 5in2 film. As a result, the 5in2 pattern 17 generated during the oxidation described above was also etched at the same time.

During this period, after peeling off the remaining resist film 19 and further removing the thermal oxide film 12f, field oxidation 11j-J i
Group fi surrounded by s! Gate oxide film 20'2 on the surface of 11
- Formed (as shown in FIG. 3(f). Hereinafter, by a conventional method,
A gate electrode 21 is formed on the gate oxide film 20,
By using this gate electrode 2 as a mask, the substrate 11
N+ type source, do1/ear (iJI area 22.2
3f formation (7, further K layer fil insulation IA'& 24t
Contact hole 25.25 and extraction electrode ze, ze
A M0S transistor f was manufactured by forming (Fig. 3(g)
).

According to the present invention, when forming the field oxide film 18, selective oxidation is performed using the Si3N4 pattern 14 and the 5T02 pattern 17 with the thick sidewall of the Si3N pattern 14 as a mask, so that the oxidizing agent is applied to the Si, N4 pattern. 14 can be suppressed from spreading to the substrate 1 below,
Therefore, it is possible to perform element isolation with a conversion difference (ΔW) of 01 to 0.2 μm compared to the conventional method.

Furthermore, after forming the field oxide film 18 and peeling off the Si and N4 patterns 14, a resist film 19 is applied to the entire surface, and this resist film 19f is etched under predetermined conditions, so that the 5iCh pattern 17 can also be etched at the same time. . Therefore, the entire surface can be flattened.

Furthermore, it is a matter of course that the advantages of the LOCO3 method, such as the ability to form the anti-inversion impurity region 15 in a self-selected manner, can be utilized as is.

In addition, in the above embodiment, Si, N is used as the first mask material.
, and a 510t pattern was used as the second mask material, but the present invention is not limited to this. In addition, the flattening material is not limited to Regis) JK.

[Effects of 811] As detailed above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device that can reduce the conversion difference by /J and achieve high Wj degree and high integration of the device.

[Brief explanation of drawings]

Figures 1 (a) and (b) are cross-sectional views showing the conventional method for spinning MOS transistors in the order of steps; Figure 2 is a cross-sectional view of an intermediate step in manufacturing a MOS transistor to explain the shortcomings of the conventional method; Figures (a) to (g) are cross-sectional views illustrating a method of manufacturing a Mos transistor according to an embodiment of the present invention. 1no...P-type silicon substrate, 12...thermal oxide film (
Insulating film), l3-S i3 N4 film, 14 ・-8
t, N. Pattern (first mask material), 151 inversion prevention impurity region, 5...SiO, film (coating), 17...5i0
2 patterns (second mask material), 18... field oxide film, 19... resist film (planarization implantation 2θ...
Gate oxide film, 2)...gate electrode, 22...N
type source region, 23...Hy drain region, 2
4... Interlayer insulating film, 25... Contact hole, 2
5... Takeout electrode.

Claims (3)

[Claims] (1) A step of forming a first mask material on a semiconductor substrate via an insulating film, a step of forming a film on the entire surface, and anisotropic etching of this film so that it remains only on the sidewalls of the mask material. 19. forming a second mask material; Second
a step of forming a field oxide film by performing oxidation treatment using mask stripping; a step of removing the first mask material; 1.
A method for manufacturing a semiconductor device, comprising the steps of forming a planarizing material on the entire surface, anisotropically etching the planarizing material and the second mask material, and removing the planarizing material. . (2) 81. as the first mask material. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a SIO pattern is used as the second mask material. (3) A method for manufacturing a semiconductor device according to claim 1, characterized in that a resist film is used as a material for the planarization material.