JP2006196514A - Semiconductor device and its fabrication process - Google Patents

Semiconductor device and its fabrication process Download PDF

Info

Publication number
JP2006196514A
JP2006196514A JP2005003786A JP2005003786A JP2006196514A JP 2006196514 A JP2006196514 A JP 2006196514A JP 2005003786 A JP2005003786 A JP 2005003786A JP 2005003786 A JP2005003786 A JP 2005003786A JP 2006196514 A JP2006196514 A JP 2006196514A
Authority
JP
Japan
Prior art keywords
active layer
region
semiconductor active
oxide film
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005003786A
Other languages
Japanese (ja)
Inventor
Koki Matsumoto
弘毅 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2005003786A priority Critical patent/JP2006196514A/en
Priority to US11/322,304 priority patent/US20060157786A1/en
Priority to CNB2006100058243A priority patent/CN100521216C/en
Publication of JP2006196514A publication Critical patent/JP2006196514A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To form a gettering region without performing an ion implantation process. <P>SOLUTION: The semiconductor device comprises an SOI substrate 1 where a semiconductor active layer 1c is formed on a semiconductor wafer 1a through a pasted insulating film 1b, an insulating film 5 arranged in an isolation region 8 around the element forming region 9 of the SOI substrate 1 and on the semiconductor active layer 1c while having a plurality of meshed openings 5a, and a gettering region 6 arranged in a semiconductor active layer 1a in the vicinity of the opening 5a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、SOI基板を用いた半導体装置及びその製造方法に関し、特に、重金属などの汚染物質を捕獲するゲッタリング領域を有する半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device using an SOI substrate and a manufacturing method thereof, and more particularly to a semiconductor device having a gettering region that captures contaminants such as heavy metals and a manufacturing method thereof.

半導体ウエハに貼り合せ絶縁膜を介して半導体活性層を形成したSOI(Silicon On Insulator)基板を用いた半導体装置は、低電圧電源でも高速に動作するため、低消費電力LSIへの応用が検討されている。このようなSOI基板を用いた半導体装置は、半導体活性層の厚みが10μm程度と薄く、この半導体活性層は全領域が無欠陥領域となっており、半導体活性層の下には貼り合せ絶縁膜がある。このような構成では、製造プロセス中の重金属などの汚染物質は、半導体活性層で捕獲(吸収;ゲッタリング)されず、貼り合せ絶縁膜が汚染物質の通過を妨げるので、通常のウエハのように基板の裏面(SOI基板における半導体ウエハの裏面)をゲッタリングサイト(結晶欠陥、ひずみ層、応力場)として使うことができない。そのため、貼り合せ酸化膜上の半導体活性層中に汚染物質が取り残されることになり、SOI基板上に形成された素子にリーク電流が生じたり、ゲート酸化膜の膜質を劣化させるなど、SOI基板上に形成されるデバイスに悪影響を及ぼすことがある。具体的には、SOI基板上に形成された素子は、通常のウエハ上に形成された素子に比べ、ゲート酸化膜のQbd(Charge to breakdown;絶縁破壊電荷量)が小さくなる。したがって、SOI基板を用いた半導体装置において、汚染物質を効果的に捕獲し、素子の信頼性を向上させる必要がある。このような必要性から、SOI基板を用いた半導体装置において、素子分離領域にゲッタリング領域を形成したものが開示されている(特許文献1参照)。   A semiconductor device using an SOI (Silicon On Insulator) substrate in which a semiconductor active layer is formed on a semiconductor wafer by bonding an insulating film operates at a high speed even with a low voltage power source. Therefore, application to a low power consumption LSI has been studied. ing. In a semiconductor device using such an SOI substrate, the thickness of the semiconductor active layer is as thin as about 10 μm, and this semiconductor active layer is entirely a defect-free region, and a bonded insulating film is formed under the semiconductor active layer. There is. In such a configuration, contaminants such as heavy metals in the manufacturing process are not captured (absorbed; gettered) by the semiconductor active layer, and the bonded insulating film prevents the contaminants from passing through. The back surface of the substrate (the back surface of the semiconductor wafer in the SOI substrate) cannot be used as a gettering site (crystal defect, strained layer, stress field). Therefore, contaminants are left in the semiconductor active layer on the bonded oxide film, and leakage current is generated in the element formed on the SOI substrate, and the film quality of the gate oxide film is deteriorated. May adversely affect the devices formed. Specifically, the element formed on the SOI substrate has a smaller Qbd (Charge to breakdown) of the gate oxide film than the element formed on the normal wafer. Therefore, in a semiconductor device using an SOI substrate, it is necessary to effectively capture contaminants and improve element reliability. In view of the necessity, a semiconductor device using an SOI substrate in which a gettering region is formed in an element isolation region is disclosed (see Patent Document 1).

特許文献1に記載の半導体装置では、以下のようにしてゲッタリング領域を形成している。まず、半導体ウエハ101aに貼り合せ絶縁膜101bを介して半導体活性層101c(p型又はn型)を形成したSOI基板101を用意する。半導体活性層101cを貼り合せ絶縁膜101bに達する分離溝112で島状に分割し、分離溝112は酸化膜を介してポリシリコンで埋め込む(図4(A)参照)。次に、SOI基板101上に酸化膜102を形成し、この酸化膜102上に窒化膜103を形成し、この窒化膜103上にフォトレジスト104を被覆し、パターニング及びエッチングにより素子分離領域113上の窒化膜103とフォトレジスト104を除去する(図4(B)参照)。その後、フォトレジスト104と窒化膜103をマスクとして、酸化膜102の下の素子分離領域113に酸素原子又はSi原子をイオン化してイオン注入を行う(図4(C)参照)。続いて、フォトレジスト104を除去した後、熱酸化により、素子分離領域113にLOCOS(Local Oxidation of Silicon)酸化膜109を形成し、窒化膜103及び酸化膜102を除去する(図4(D)参照)。イオン注入物質が酸素原子の場合、熱酸化、または、その後の熱処理によって、素子分離領域113中に酸素原子の一部が析出した領域がゲッタリング領域108(ゲッタリングサイト)となる。イオン注入物質がSi原子の場合、熱処理による結晶化の過程で、Si原子によって局部応力が発生して、結晶欠陥が形成され、この結晶欠陥が形成された領域がゲッタリング領域108(ゲッタリングサイト)となる。このようにして、素子分離領域113のLOCOS酸化膜109の下に形成されたゲッタリング領域108によって、半導体素子を形成する時に導入される重金属などの汚染物質を捕獲(ゲッタリング)できるというものである。   In the semiconductor device described in Patent Document 1, the gettering region is formed as follows. First, an SOI substrate 101 is prepared in which a semiconductor active layer 101c (p-type or n-type) is formed on a semiconductor wafer 101a through a bonding insulating film 101b. The semiconductor active layer 101c is divided into island shapes by a separation groove 112 reaching the bonded insulating film 101b, and the separation groove 112 is filled with polysilicon through an oxide film (see FIG. 4A). Next, an oxide film 102 is formed on the SOI substrate 101, a nitride film 103 is formed on the oxide film 102, a photoresist 104 is coated on the nitride film 103, and patterning and etching are performed on the element isolation region 113. The nitride film 103 and the photoresist 104 are removed (see FIG. 4B). Thereafter, using the photoresist 104 and the nitride film 103 as a mask, ion implantation is performed by ionizing oxygen atoms or Si atoms into the element isolation region 113 below the oxide film 102 (see FIG. 4C). Subsequently, after removing the photoresist 104, a LOCOS (Local Oxidation of Silicon) oxide film 109 is formed in the element isolation region 113 by thermal oxidation, and the nitride film 103 and the oxide film 102 are removed (FIG. 4D). reference). When the ion-implanted material is oxygen atoms, a region in which part of the oxygen atoms is precipitated in the element isolation region 113 by thermal oxidation or subsequent heat treatment becomes the gettering region 108 (gettering site). When the ion-implanted material is Si atoms, local stress is generated by Si atoms during the crystallization process by heat treatment to form crystal defects, and a region where the crystal defects are formed is a gettering region 108 (gettering site). ) In this manner, the gettering region 108 formed under the LOCOS oxide film 109 in the element isolation region 113 can capture (getter) contaminants such as heavy metals introduced when forming the semiconductor element. is there.

特開平11−297703号公報JP 11-297703 A

しかしながら、特許文献1に記載の半導体装置の製造方法では、ゲッタリング領域を形成するために、酸素原子又はSi原子のイオン注入工程が必要であり、製造プロセスが冗長になるおそれがある。   However, in the method of manufacturing a semiconductor device described in Patent Document 1, an ion implantation step of oxygen atoms or Si atoms is necessary to form a gettering region, which may make the manufacturing process redundant.

本発明の課題は、ゲッタリング領域用のイオン注入工程を行うことなく、ゲッタリング領域を形成できるようにすることである。   An object of the present invention is to make it possible to form a gettering region without performing an ion implantation process for the gettering region.

本発明の第1の視点においては、半導体装置において、半導体ウエハに貼り合せ絶縁膜を介して半導体活性層を形成したSOI基板と、前記SOI基板の素子形成領域の周囲の素子分離領域に配されるとともに、前記半導体活性層上に配され、かつ、網目状又はライン状の複数の開口部を有する絶縁膜と、前記開口部の近傍の前記半導体活性層中に配されたゲッタリング領域と、を備えることを特徴とする。   In a first aspect of the present invention, in a semiconductor device, an SOI substrate in which a semiconductor active layer is formed on a semiconductor wafer through a bonding insulating film, and an element isolation region around the element formation region of the SOI substrate are arranged. And an insulating film disposed on the semiconductor active layer and having a plurality of mesh or line openings, and a gettering region disposed in the semiconductor active layer in the vicinity of the openings, It is characterized by providing.

本発明の第2の視点においては、半導体装置において、半導体活性層と、前記半導体活性層上であって素子形成領域を区画する素子分離領域に形成されるとともに、複数の開口部を有するLOCOS酸化膜と、前記開口部に対応して前記LOCOS酸化膜の下の前記半導体活性層中に形成されたゲッタリング領域と、を備えることを特徴とする。   According to a second aspect of the present invention, in a semiconductor device, a LOCOS oxide having a plurality of openings formed in a semiconductor active layer and an element isolation region on the semiconductor active layer and partitioning an element formation region. And a gettering region formed in the semiconductor active layer under the LOCOS oxide film corresponding to the opening.

本発明の第3の視点においては、半導体装置の製造方法において、半導体ウエハに貼り合せ絶縁膜を介して半導体活性層を形成したSOI基板上にシリコン酸化膜及びシリコン窒化膜を形成する工程と、前記シリコン窒化膜上であって、前記SOI基板の素子形成領域の全面、かつ、素子分離領域にて網目状又はライン状にフォトレジストを形成する工程と、前記フォトレジストをエッチングマスクとして、前記半導体活性層が表れるまで、少なくとも前記シリコン酸化膜及び前記シリコン窒化膜をエッチングする工程と、前記フォトレジストを除去した後、前記シリコン窒化膜をマスクとして、熱酸化法により、前記素子分離領域にゲッタリング領域を形成するための網目状又はライン状の複数の開口部を有するLOCOS酸化膜を形成する工程と、を含むことを特徴とする。   In a third aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming a silicon oxide film and a silicon nitride film on an SOI substrate in which a semiconductor active layer is formed on a semiconductor wafer through a bonding insulating film; Forming a photoresist on the entire surface of the element formation region of the SOI substrate on the silicon nitride film and in the element isolation region in a mesh or a line; and using the photoresist as an etching mask, the semiconductor Etching at least the silicon oxide film and the silicon nitride film until the active layer appears, and after removing the photoresist, gettering is performed on the element isolation region by thermal oxidation using the silicon nitride film as a mask. Forming a LOCOS oxide film having a plurality of mesh-like or line-like openings for forming a region; Characterized in that it comprises a step.

本発明によれば、SOI基板において、特別な工程を新たに増やすことなく、重金属などの汚染物質を効果的に捕獲することができる信頼性の高いデバイスを提供することができる。   According to the present invention, it is possible to provide a highly reliable device capable of effectively capturing contaminants such as heavy metals without newly adding special processes in an SOI substrate.

(実施形態1)
本発明の実施形態1に係る半導体装置について図面を用いて説明する。図1は、本発明の実施形態1に係る半導体装置の構成を模式的に示した(A)部分断面図、及び(B)部分平面図である。
(Embodiment 1)
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. 1A is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 1B is a partial plan view thereof.

この半導体装置は、SOI基板1にゲッタリング領域6を有する半導体装置であり、SOI基板1と、LOCOS酸化膜5と、ゲッタリング領域6と、分離溝7と、素子分離領域8と、素子形成領域9と、を有する。なお、図1では、説明の便宜上、半導体装置の中間体を示している。   This semiconductor device is a semiconductor device having a gettering region 6 on an SOI substrate 1, and includes an SOI substrate 1, a LOCOS oxide film 5, a gettering region 6, an isolation groove 7, an element isolation region 8, and an element formation. Region 9. Note that FIG. 1 shows an intermediate of a semiconductor device for convenience of explanation.

SOI基板1は、半導体ウエハ1aに貼り合せ絶縁膜1bを介して半導体活性層1cを形成した基板である。半導体活性層1cは、p型又はn型のシリコン単結晶よりなり、将来的にはp型又はn型ウエル領域となる。LOCOS酸化膜5は、LOCOS法によって半導体活性層1c上に形成されたシリコン酸化膜(絶縁膜)であり、素子分離領域8に形成されている。LOCOS酸化膜5は、平面方向から見て、メッシュ状(網状)に形成され、網目状(島状)に形成された複数の開口部5aを有する。ゲッタリング領域6は、重金属などの汚染物質を捕獲する領域であり、平面方向から見て素子分離領域8のうちLOCOS酸化膜5の開口部5a及びその近傍に配され、断面方向から見て開口部5a近傍の半導体活性層1cに配され、開口部5a近傍のLOCOS酸化膜5下の半導体活性層1cも含む。分離溝7は、隣り合う素子形成領域を素子分離するため溝であり、半導体活性層1cに形成され、深さが貼り合せ絶縁膜1bまである。分離溝7の内壁面にはシリコン酸化膜7aが形成されており、シリコン酸化膜7a内にはポリシリコン7bが埋め込まれている。素子分離領域8は、隣り合う素子形成領域を素子分離するための領域であり、平面方向から見て分離溝7によって囲まれた領域のうち素子形成領域9の周囲に配され、LOCOS酸化膜5の開口部5aとなる領域も含まれる。素子形成領域9は、素子を形成するための領域であり、平面方向から見て素子分離領域8に囲まれており、LOCOS酸化膜5の開口部5aとなる領域は含まない。   The SOI substrate 1 is a substrate in which a semiconductor active layer 1c is formed on a semiconductor wafer 1a through a bonding insulating film 1b. The semiconductor active layer 1c is made of p-type or n-type silicon single crystal and will become a p-type or n-type well region in the future. The LOCOS oxide film 5 is a silicon oxide film (insulating film) formed on the semiconductor active layer 1 c by the LOCOS method, and is formed in the element isolation region 8. The LOCOS oxide film 5 is formed in a mesh shape (net shape) when viewed from the plane direction, and has a plurality of openings 5a formed in a mesh shape (island shape). The gettering region 6 is a region that captures contaminants such as heavy metals. The gettering region 6 is disposed in and near the opening 5a of the LOCOS oxide film 5 in the element isolation region 8 when viewed from the planar direction, and is opened when viewed from the cross-sectional direction. The semiconductor active layer 1c is also disposed in the semiconductor active layer 1c near the portion 5a and under the LOCOS oxide film 5 near the opening 5a. The isolation trench 7 is a trench for isolating adjacent element formation regions, is formed in the semiconductor active layer 1c, and has a depth up to the bonded insulating film 1b. A silicon oxide film 7a is formed on the inner wall surface of the isolation trench 7, and polysilicon 7b is embedded in the silicon oxide film 7a. The element isolation region 8 is a region for isolating adjacent element formation regions. The element isolation region 8 is arranged around the element formation region 9 in a region surrounded by the isolation groove 7 when viewed from the plane direction, and the LOCOS oxide film 5. The region to be the opening 5a is also included. The element formation region 9 is a region for forming an element, is surrounded by the element isolation region 8 when viewed from the plane direction, and does not include a region that becomes the opening 5a of the LOCOS oxide film 5.

次に、本発明の実施形態1に係る半導体装置の製造方法について図面を用いて説明する。図2及び図3は、本発明の実施形態1に係る半導体装置の製造方法を模式的に示した工程部分断面図である。   Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. 2 and 3 are process partial cross-sectional views schematically showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

まず、半導体ウエハ1aに貼り合せ絶縁膜1bを介して半導体活性層1cを形成したSOI基板1を用意する(図2(A)参照)。   First, an SOI substrate 1 in which a semiconductor active layer 1c is formed on a semiconductor wafer 1a with a bonding insulating film 1b interposed therebetween is prepared (see FIG. 2A).

次に、半導体活性層1c上にシリコン酸化膜2を形成し、シリコン酸化膜2上にシリコン窒化膜3を形成し、シリコン窒化膜3上にフォトレジスト4を被覆し、フォトリソグラフィ法によりフォトレジスト4を所定の形状にパターニングする(図2(B)参照)。ここで、フォトレジスト4は、平面方向から見て、将来的に、素子形成領域9、及びLOCOS酸化膜の開口部(図2(D)の5a)となる領域上に形成される。   Next, a silicon oxide film 2 is formed on the semiconductor active layer 1c, a silicon nitride film 3 is formed on the silicon oxide film 2, a photoresist 4 is coated on the silicon nitride film 3, and a photoresist is formed by photolithography. 4 is patterned into a predetermined shape (see FIG. 2B). Here, the photoresist 4 is formed on an element formation region 9 and a region to be an opening of the LOCOS oxide film (5a in FIG. 2D) in the future as viewed from the planar direction.

次に、フォトレジスト4をエッチングマスクとして、ドライエッチング法により、半導体活性層1cが表れるまで、シリコン窒化膜3及びシリコン酸化膜2(並びに半導体活性層1cの一部)を除去する(図2(C)参照)。なお、LOCOS酸化膜(図2(D)の5)の表面と半導体活性層1cの表面を同じレベルに揃えるプレーナLOCOS構造にするために、LOCOS酸化膜の盛り上がりを見込んだ分、半導体活性層1cの一部を除去することが好ましい。   Next, the silicon nitride film 3 and the silicon oxide film 2 (and a part of the semiconductor active layer 1c) are removed by dry etching using the photoresist 4 as an etching mask until the semiconductor active layer 1c appears (FIG. 2 (FIG. 2 ( C)). In order to obtain a planar LOCOS structure in which the surface of the LOCOS oxide film (5 in FIG. 2D) and the surface of the semiconductor active layer 1c are aligned at the same level, the semiconductor active layer 1c is expected to rise. It is preferable to remove a part of.

次に、フォトレジスト(図2(C)の4)を除去した後、シリコン窒化膜3をマスクとして、熱酸化法により素子分離領域8にLOCOS酸化膜5を形成し、その後、熱酸化によって形成されたシリコン窒化膜3上の酸化膜(図示せず)、シリコン窒化膜(図2(C)の3)、及びシリコン酸化膜(図2(C)の2)を除去する(図2(D)参照)。これにより、複数の開口部5aを有するLOCOS酸化膜5が形成され、開口部5aの近傍の半導体活性層1c中にゲッタリング領域6が形成される。   Next, after removing the photoresist (4 in FIG. 2C), the LOCOS oxide film 5 is formed in the element isolation region 8 by thermal oxidation using the silicon nitride film 3 as a mask, and then formed by thermal oxidation. The oxide film (not shown), the silicon nitride film (3 in FIG. 2C), and the silicon oxide film (2 in FIG. 2C) on the formed silicon nitride film 3 are removed (FIG. 2D). )reference). Thereby, a LOCOS oxide film 5 having a plurality of openings 5a is formed, and a gettering region 6 is formed in the semiconductor active layer 1c in the vicinity of the openings 5a.

次に、半導体活性層1c及びLOCOS酸化膜5上にシリコン酸化膜12を形成し、シリコン酸化膜12上にシリコン窒化膜13を形成し、シリコン窒化膜13上にフォトレジスト14を被覆し、フォトリソグラフィ法によりフォトレジスト14を所定の形状にパターニングする(図3(E)参照)。ここで、フォトレジスト14は、平面方向から見て、将来的に、分離溝(図3(F)の7)となる領域以外の半導体活性層1c及びLOCOS酸化膜5上に形成され、網目状(島状)に分割した形状に形成される。   Next, a silicon oxide film 12 is formed on the semiconductor active layer 1c and the LOCOS oxide film 5, a silicon nitride film 13 is formed on the silicon oxide film 12, a photoresist 14 is coated on the silicon nitride film 13, and a photo The photoresist 14 is patterned into a predetermined shape by a lithography method (see FIG. 3E). Here, the photoresist 14 is formed on the semiconductor active layer 1c and the LOCOS oxide film 5 other than the region that will become the isolation trench (7 in FIG. 3F) in the future when viewed from the plane direction, and has a mesh shape. It is formed in a shape divided into (islands).

次に、フォトレジスト14をエッチングマスクとして、ドライエッチング法により、貼り合せ絶縁膜1bが表れるまで、シリコン窒化膜13、シリコン酸化膜12、LOCOS酸化膜5及び及び半導体活性層1cを除去する(図3(F)参照)。ここで、LOCOS酸化膜5及び半導体活性層1cを除去することによって、分離溝7が形成される。   Next, using the photoresist 14 as an etching mask, the silicon nitride film 13, the silicon oxide film 12, the LOCOS oxide film 5, and the semiconductor active layer 1c are removed by dry etching until the bonded insulating film 1b appears (FIG. 5). 3 (F)). Here, the isolation trench 7 is formed by removing the LOCOS oxide film 5 and the semiconductor active layer 1c.

次に、フォトレジスト4を除去した後、熱酸化法により、分離溝7の内壁面にシリコン酸化膜7aを形成する(図3(G)参照)。   Next, after removing the photoresist 4, a silicon oxide film 7a is formed on the inner wall surface of the separation groove 7 by thermal oxidation (see FIG. 3G).

次に、分離溝(図3(G)の7;シリコン酸化膜7a)内に、CVD法によりポリシリコン7bを埋め込んだ後、シリコン窒化膜(図3(G)の13)をストッパとして、CMP法によって平坦化し、シリコン窒化膜(図3(G)の13)、及びシリコン酸化膜(図3(G)の12)を除去する(図3(H)参照)。この後、素子形成領域9にて素子の形成が行われ、さらに配線の形成が行われることになる(図示せず)。なお、ここではCMP法によって不要なポリシリコン7bを除去しているが、ドライエッチングによるエッチバック法によって不要なポリシリコン7bを除去してもよい。   Next, after filling polysilicon 7b in the isolation trench (7 in FIG. 3G; silicon oxide film 7a) by CVD, CMP is performed using the silicon nitride film (13 in FIG. 3G) as a stopper. Then, the silicon nitride film (13 in FIG. 3G) and the silicon oxide film (12 in FIG. 3G) are removed (see FIG. 3H). Thereafter, an element is formed in the element forming region 9 and further a wiring is formed (not shown). Although unnecessary polysilicon 7b is removed here by CMP, unnecessary polysilicon 7b may be removed by etch-back using dry etching.

図2(D)の状態の半導体装置を平面方向から見ると、素子分離領域8に形成されるLOCOS酸化膜5は、SOI基板1上に網目状(島状)に多数の開口部5aを有する。SOI基板1上(半導体活性層1c上)にメッシュ状(網状)に多数の窪みを形成し、熱酸化を行う。半導体活性層1c(シリコン)の熱酸化に伴う応力により、半導体活性層1c/LOCOS酸化膜5の界面近傍において半導体活性層1c中のSi結晶格子に歪が生ずる。特に、SOI基板1上にLOCOS酸化膜5中の多数の開口部5aが存在するため、これら各開口部5aの(平面方向から見たときの)中心部の近傍において、結晶格子の歪みが大きくなり、半導体活性層1c中のゲッタリング領域6に多数の結晶欠陥が生成される。この結晶欠陥により、重金属汚染物質を吸収することができる。ゲッタリング領域6の形成は、イオン注入工程を行う必要がないので、製造工程が増えることはない。   When the semiconductor device in the state of FIG. 2D is viewed from the planar direction, the LOCOS oxide film 5 formed in the element isolation region 8 has a large number of openings 5 a in a mesh shape (island shape) on the SOI substrate 1. . A number of depressions are formed in a mesh shape (net shape) on the SOI substrate 1 (on the semiconductor active layer 1c), and thermal oxidation is performed. Due to the stress accompanying thermal oxidation of the semiconductor active layer 1c (silicon), strain is generated in the Si crystal lattice in the semiconductor active layer 1c in the vicinity of the interface of the semiconductor active layer 1c / LOCOS oxide film 5. In particular, since there are a large number of openings 5a in the LOCOS oxide film 5 on the SOI substrate 1, the distortion of the crystal lattice is large in the vicinity of the center (when viewed from the plane) of each of the openings 5a. Thus, a large number of crystal defects are generated in the gettering region 6 in the semiconductor active layer 1c. This crystal defect can absorb heavy metal contaminants. The formation of the gettering region 6 does not require an ion implantation process, so that the manufacturing process does not increase.

(実施形態2)
本発明の実施形態2として、LOCOS酸化膜5の開口部5aの平面方向から見たときの形状は、L字型、T字型、十字型、任意の多角形、ライン状でもよい。
(Embodiment 2)
As Embodiment 2 of the present invention, the shape of the opening 5a of the LOCOS oxide film 5 when viewed from the plane direction may be L-shaped, T-shaped, cross-shaped, arbitrary polygonal, or line-shaped.

本発明の実施形態1に係る半導体装置の構成を模式的に示した(A)部分断面図、及び(B)部分平面図である。1A is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 本発明の実施形態1に係る半導体装置の製造方法を模式的に示した第1の工程部分断面図である。It is the 1st process partial sectional view showing typically the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention. 本発明の実施形態1に係る半導体装置の製造方法を模式的に示した第2の工程部分断面図である。It is the 2nd process fragmentary sectional view showing typically the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention. 従来例に係る半導体装置の製造方法を模式的に示した工程部分断面図である。It is process partial sectional drawing which showed typically the manufacturing method of the semiconductor device which concerns on a prior art example.

符号の説明Explanation of symbols

1 SOI基板
1a 半導体ウエハ
1b 貼り合せ絶縁膜
1c 半導体活性層
2、12 シリコン酸化膜
3、13 シリコン窒化膜
4、14 フォトレジスト
5 LOCOS酸化膜(絶縁膜)
5a 開口部
6 ゲッタリング領域
7 分離溝
7a シリコン酸化膜
7b ポリシリコン
8 素子分離領域
9 素子形成領域
101 SOI基板
101a 半導体ウエハ
101b 貼り合せ絶縁膜
101c 半導体活性層
102 酸化膜
103 窒化膜
104 フォトレジスト
108 ゲッタリング領域
109 LOCOS酸化膜
112 分離溝
113 素子分離領域
DESCRIPTION OF SYMBOLS 1 SOI substrate 1a Semiconductor wafer 1b Bonding insulating film 1c Semiconductor active layer 2, 12 Silicon oxide film 3, 13 Silicon nitride film 4, 14 Photoresist 5 LOCOS oxide film (insulating film)
5a Opening 6 Gettering region 7 Separation groove 7a Silicon oxide film 7b Polysilicon 8 Element isolation region 9 Element formation region 101 SOI substrate 101a Semiconductor wafer 101b Bonding insulating film 101c Semiconductor active layer 102 Oxide film 103 Nitride film 104 Photoresist 108 Gettering region 109 LOCOS oxide film 112 Isolation groove 113 Element isolation region

Claims (6)

半導体ウエハに貼り合せ絶縁膜を介して半導体活性層を形成したSOI基板と、
前記SOI基板の素子形成領域の周囲の素子分離領域に配されるとともに、前記半導体活性層上に配され、かつ、網目状又はライン状の複数の開口部を有する絶縁膜と、
前記開口部の近傍の前記半導体活性層中に配されたゲッタリング領域と、
を備えることを特徴とする半導体装置。
An SOI substrate having a semiconductor active layer formed on a semiconductor wafer through an insulating film;
An insulating film disposed in an element isolation region around an element formation region of the SOI substrate, disposed on the semiconductor active layer, and having a plurality of mesh-shaped or line-shaped openings;
A gettering region disposed in the semiconductor active layer in the vicinity of the opening;
A semiconductor device comprising:
前記半導体活性層を前記素子形成領域ごとに島状に分割するとともに、前記素子分離領域にて前記絶縁膜及び前記半導体活性層を貫通して前記貼り合せ絶縁膜に達する分離溝を備えることを特徴とする請求項1記載の半導体装置。   The semiconductor active layer is divided into islands for each element formation region, and an isolation groove is provided that penetrates the insulating film and the semiconductor active layer in the element isolation region and reaches the bonded insulating film. The semiconductor device according to claim 1. 前記開口部を有する絶縁膜は、LOCOS酸化膜であることを特徴とする請求項1又は2記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the insulating film having the opening is a LOCOS oxide film. 半導体活性層と、
前記半導体活性層上であって素子形成領域を区画する素子分離領域に形成されるとともに、複数の開口部を有するLOCOS酸化膜と、
前記開口部に対応して前記LOCOS酸化膜の下の前記半導体活性層中に形成されたゲッタリング領域と、
を備えることを特徴とする半導体装置。
A semiconductor active layer;
A LOCOS oxide film formed on an element isolation region on the semiconductor active layer and defining an element formation region, and having a plurality of openings;
A gettering region formed in the semiconductor active layer below the LOCOS oxide film corresponding to the opening;
A semiconductor device comprising:
半導体ウエハに貼り合せ絶縁膜を介して半導体活性層を形成したSOI基板上にシリコン酸化膜及びシリコン窒化膜を形成する工程と、
前記シリコン窒化膜上であって、前記SOI基板の素子形成領域の全面、かつ、素子分離領域にて網目状又はライン状にフォトレジストを形成する工程と、
前記フォトレジストをエッチングマスクとして、前記半導体活性層が表れるまで、少なくとも前記シリコン酸化膜及び前記シリコン窒化膜をエッチングする工程と、
前記フォトレジストを除去した後、前記シリコン窒化膜をマスクとして、熱酸化法により、前記素子分離領域にゲッタリング領域を形成するための網目状又はライン状の複数の開口部を有するLOCOS酸化膜を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
Forming a silicon oxide film and a silicon nitride film on an SOI substrate on which a semiconductor active layer is formed by bonding to a semiconductor wafer via an insulating film;
Forming a photoresist on the silicon nitride film over the entire surface of the element formation region of the SOI substrate and in the element isolation region in a mesh or a line;
Etching at least the silicon oxide film and the silicon nitride film until the semiconductor active layer appears using the photoresist as an etching mask;
After removing the photoresist, using the silicon nitride film as a mask, a LOCOS oxide film having a plurality of mesh or line openings for forming a gettering region in the element isolation region is formed by thermal oxidation. Forming, and
A method for manufacturing a semiconductor device, comprising:
前記半導体活性層を前記素子形成領域ごとに島状に分割するとともに、前記素子分離領域にて前記LOCOS酸化膜及び前記半導体活性層を貫通して前記貼り合せ絶縁膜に達する分離溝を形成する工程を含むことを特徴とする請求項5記載の半導体装置の製造方法。   Dividing the semiconductor active layer into islands for each element formation region, and forming an isolation trench that penetrates the LOCOS oxide film and the semiconductor active layer and reaches the bonded insulating film in the element isolation region; The method of manufacturing a semiconductor device according to claim 5, comprising:
JP2005003786A 2005-01-11 2005-01-11 Semiconductor device and its fabrication process Pending JP2006196514A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005003786A JP2006196514A (en) 2005-01-11 2005-01-11 Semiconductor device and its fabrication process
US11/322,304 US20060157786A1 (en) 2005-01-11 2006-01-03 Semiconductor device and manufacturing method thereof
CNB2006100058243A CN100521216C (en) 2005-01-11 2006-01-10 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005003786A JP2006196514A (en) 2005-01-11 2005-01-11 Semiconductor device and its fabrication process

Publications (1)

Publication Number Publication Date
JP2006196514A true JP2006196514A (en) 2006-07-27

Family

ID=36683008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005003786A Pending JP2006196514A (en) 2005-01-11 2005-01-11 Semiconductor device and its fabrication process

Country Status (3)

Country Link
US (1) US20060157786A1 (en)
JP (1) JP2006196514A (en)
CN (1) CN100521216C (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5446388B2 (en) * 2009-03-31 2014-03-19 サンケン電気株式会社 Method for manufacturing integrated semiconductor device
CN101958317A (en) * 2010-07-23 2011-01-26 上海宏力半导体制造有限公司 Wafer structure and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213449A (en) * 1995-02-02 1996-08-20 Nec Corp Manufacture of semiconductor device
WO1996029731A1 (en) * 1995-03-17 1996-09-26 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
JPH10209169A (en) * 1997-01-20 1998-08-07 Nec Corp Manufacture of semiconductor device
JPH11297703A (en) * 1998-04-15 1999-10-29 Fuji Electric Co Ltd Fabrication of semiconductor device
JP2001513948A (en) * 1997-12-23 2001-09-04 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method of providing gettering means in manufacturing silicon-on-insulator (SOI) integrated circuits
JP2002033382A (en) * 2000-05-11 2002-01-31 Denso Corp Semiconductor device and its manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09120965A (en) * 1995-10-25 1997-05-06 Toshiba Corp Manufacture of semiconductor device
US6013954A (en) * 1997-03-31 2000-01-11 Nec Corporation Semiconductor wafer having distortion-free alignment regions
JP2000323484A (en) * 1999-05-07 2000-11-24 Mitsubishi Electric Corp Semiconductor device and semiconductor memory
US6830986B2 (en) * 2002-01-24 2004-12-14 Matsushita Electric Industrial Co., Ltd. SOI semiconductor device having gettering layer and method for producing the same
JP2004103613A (en) * 2002-09-04 2004-04-02 Toshiba Corp Semiconductor device and its manufacturing method
KR100538069B1 (en) * 2003-12-16 2005-12-20 매그나칩 반도체 유한회사 Isolation of image sensor for reducing dark signal

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08213449A (en) * 1995-02-02 1996-08-20 Nec Corp Manufacture of semiconductor device
WO1996029731A1 (en) * 1995-03-17 1996-09-26 Hitachi, Ltd. Semiconductor device and method of manufacturing the same
JPH10209169A (en) * 1997-01-20 1998-08-07 Nec Corp Manufacture of semiconductor device
JP2001513948A (en) * 1997-12-23 2001-09-04 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method of providing gettering means in manufacturing silicon-on-insulator (SOI) integrated circuits
JPH11297703A (en) * 1998-04-15 1999-10-29 Fuji Electric Co Ltd Fabrication of semiconductor device
JP2002033382A (en) * 2000-05-11 2002-01-31 Denso Corp Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
US20060157786A1 (en) 2006-07-20
CN100521216C (en) 2009-07-29
CN1819218A (en) 2006-08-16

Similar Documents

Publication Publication Date Title
JP2006344943A (en) Mos field effect transistor having trench isolation region and method of fabricating the same
TWI690025B (en) Semiconductor-on-insulator (soi)substrate, method for forming thereof, and integrated circuit
TWI593105B (en) Method for forming semiconductor device structure
KR100997315B1 (en) Manufacturing method of image sensor
JPH11297703A (en) Fabrication of semiconductor device
JP2006196514A (en) Semiconductor device and its fabrication process
JP2007250600A (en) Semiconductor device and fabrication process method
JP5917790B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2011525302A (en) Manufacturing method of semiconductor structure and semiconductor structure obtained by this method
JP2006005063A (en) Semiconductor device, and method of manufacturing the same
JP5130677B2 (en) Manufacturing method of semiconductor devices
JP2006303350A (en) Semiconductor device
JP2002343799A (en) Method for manufacturing soi substrate and semiconductor device
JP2005197405A (en) Semiconductor device and manufacturing method therefor
TWI458046B (en) Semiconductor device manufacturing method and electrical machine
JP2005286141A (en) Manufacturing method of semiconductor device
JP2006222447A (en) Semiconductor apparatus and manufacturing method therefor
JP5245327B2 (en) Manufacturing method of semiconductor device
JP2008270318A (en) Semiconductor and method of manufacturing the same
JP2009146917A (en) Semiconductor device
JP2009212266A (en) Semiconductor device and method of manufacturing the same
JP2015065281A (en) Method for manufacturing three-dimensional structure integrated circuit
CN114864479A (en) Semiconductor device and method for manufacturing the same
JP2007227600A (en) Method of manufacturing semiconductor device, photomask, and semiconductor device
JP2006332221A (en) Method of removing impurity of semiconductor wafer and method of manufacturing semiconductor

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071212

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101221

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101222

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110218

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110315