JP2944228B2 - Data collection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data collecting apparatus for judging the amplitude of a pulse signal whose voltage amplitude changes with time and storing it as digital data in a storage circuit.

[0002]

2. Description of the Related Art Conventionally, there has been known a data collecting apparatus provided with a wave height discriminating circuit as shown in FIG. In the figure, 2
Is a detection unit having a built-in sensor and the like for measuring the object to be measured. It has a conversion function such as detecting an incoming radiation pulse and outputting an electric signal Sin having an amplitude corresponding to the energy of the radiation pulse.

Reference numeral 4 denotes a wave height discrimination circuit, which detects an electric signal Sin from the detector 2 that is higher than a predetermined threshold level Vth, converts the amplitude into digital data D, and outputs the digital data D. That is, the wave height discrimination circuit 4 includes the detection circuits 4a, A
It has a / D converter 4b and a timing signal generation circuit 4c. Then, as shown in FIG. 5, the detection circuit 4a compares the electric signal Sin with the threshold level Vth one by one, and changes the logical value level from “L” at the timing when the amplitude of the electric signal changes from Sin <Vth to Sin ≧ Vth. The logic signal S1 at "H" level and the amplitude of the electric signal are from Sin> Vth to Sin≤Vth
The logic signal S2 whose logical value level changes from "L" to "H" level is output at the timing of the change.

The timing signal generating circuit 4c performs a period τ from the time t1 when the logic signal S1 rises to the “H” level to the time t2 when the logic signal S2 rises to the “H” level.
A logic signal S3 having a middle "H" level is generated, and during this period τ, the A / D converter 4b converts the electric signal Sin into a digital signal. Although not shown, instead of the A / D converter 4b, the electric signal Sin is input in parallel to a plurality of analog comparators, and the comparison reference voltages of the respective analog comparators are set to be different from each other. Thus, a conversion circuit configured such that a logical output group of these comparators becomes digital data D corresponding to the electric signal Sin is used, and the conversion timing is synchronized with the timing signal S3 of the timing signal generation circuit 4c. And used a wave height discrimination circuit.

Reference numeral 6 denotes a storage circuit composed of a semiconductor memory, which stores the detection data D transferred from the peak-height discrimination circuit 4. A control circuit 8 generates a synchronization signal for synchronously controlling the timing of the discrimination operation of the pulse height discrimination circuit 4 and the timing of the storage operation of the storage circuit 6 at a predetermined cycle. With the circuit having such a configuration, the electric signal Sin is detected one by one, converted into digital data D, and stored in the storage circuit, thereby enabling digital signal processing.

[0006]

However, in such a data collection device, when the number of detection items increases, that is, when a detection unit having a large number of sensors or a plurality of detection units is applied, When performing the wave height discrimination processing for each of a large number of electric signals generated for each sensor, a plurality of circuits shown in FIG. 4 are provided in parallel for each sensor, or the output signals of the sensors are scanned in a time-division manner and the wave heights are sequentially determined. Means for performing the discrimination process is used, but when the former is provided with a plurality of circuits, a problem that the whole circuit becomes extremely large and complicated is caused. In the case of the latter, the processing speed is slow. Had caused problems.

[0007] The present invention has been made in view of such a problem, and it is possible to perform high-speed wave height discrimination processing on a plurality of signals to be measured and to simplify the circuit scale. It is intended to provide a collection device.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention comprises a FIFO memory for temporarily storing data in each of a plurality of circuits, and outputs the output data of each FIFO memory as a signal. A configuration in which the data is supplied to the storage circuit via the select circuit and stored, and the signal select circuit switches the channel in which new data is input to the FIFO memory, so that data collected in multiple channels is stored in one storage circuit. To be remembered.

[0009]

According to the data collection device having such a configuration, even if a plurality of channels operate in parallel, the data of the collected channels is selected and stored in a common storage circuit, so that the plurality of channels can be stored in real time. It can be operated. Further, even if there are a plurality of channels, the data can be stored in one system of storage circuit, so that the circuit can be simplified.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the data collecting apparatus according to the present invention will be described below with reference to FIG. First, the circuit configuration will be described with reference to FIG. 1. 10a and 10b are separate detection units. For example, in the case of a density measurement device, a sensor or the like for measuring an object to be measured is built in. It has a conversion function such as measuring a radiation pulse passing through the object to be measured and outputting electric signals Sin1 and Sin2 having an amplitude corresponding to the energy of the radiation pulse.

The circuit relating to the first detector 10a is a first detector.
A circuit related to the channel CH1 and the second detection unit 10b is defined as a second channel CH2. Each channel CH1,
Since the internal circuit of CH2 has the same configuration as shown in the figure, it will be described collectively.
The electric signals Sin1 and Sin2 output by the
2a, 12b and timing signal generating circuits 16a, 16b
And the digital data D1 and D2 output from the wave height discrimination circuits 12a and 12b are supplied to the FIFO memories 14a and 14b.
b.

The wave height discriminating circuits 12a and 12b have A / D converters for converting analog input signals Sin1 and Sin2 into digital data D1 and D2 of predetermined bits, respectively. The timing signal generation circuit 16a compares the electric signal Sin1 with the threshold level Vth1 one by one, as shown in FIG.
The logical value level changes from “L” to “H” at the timing when the amplitude of the electric signal changes from Sin1 <Vth1 to Sin1 ≧ Vth1.
The level of the logic signal S11 and the amplitude of the electrical signal are Sin1
> Vth1 to Sin1.ltoreq.Vth1 The logic signal S whose logic level changes from "L" to "H" level
The logic control signal S is internally generated and is at the "H" level during the period from the time when the logic signal S11 rises to the "H" level to the time when the logic signal S21 rises to the "H" level.
31 is generated, and during this period, the A / D converter converts the electric signal Sin1 into digital data D1 of predetermined bits N (for example, 10 bits).

The one timing signal generating circuit 16b
Similarly, a logic control signal S32 for causing the A / D converter to convert the electric signal Sin2 into digital data D2.
Occurs. As shown in FIG. 2, the FIFO memories (first-in, first-out memories) 14a and 14b have a configuration of an M-stage shift register set to N bits (for example, 10 bits or more) for each stage. , The lowest (M
SB), and shifts to the uppermost (LSB) side in synchronization with the generation timing of the logic control signals S31 and S32 and a system clock signal Sc from the timing signal generator 20 described later, thereby shifting the previously input data. Output first.

Each of the FIFO memories 14a and 14b has
Bit data for identifying which FIFO memory is used is added to the digital data D1 and D2 and output. For example, bit data "1" is added to the most significant bit of the digital data D1, and "0" is added to the most significant bit of the digital data D2. Signal select circuit 1
8 is a FIFO according to the channel selection signals CD1 and CD2.
The multiplexer circuit is configured to transfer one of the output data of the memories 14a and 14b to the storage circuit 22 side. That is, when the FIFO memory 14a outputs the most significant data in synchronization with the logical control signal S31, a channel selection signal CD1 is generated in synchronization with this timing, and the signal selection circuit 18 stores the data in the FIFO memory 14a in the storage circuit 2
2 and conversely, the FIFO memory 14b receives the logical control signal S
When the most significant data is output in synchronization with 32, a channel selection signal CD2 is generated in synchronization with this timing, and the signal selection circuit 18 transfers the data in the FIFO memory 14b to the storage circuit 22.

The signal selection circuit 18 also operates in synchronization with the system clock signal Sc from the timing signal generation circuit 20. The storage circuit 22 is composed of a random access memory (RAM), and sequentially stores data from the signal selection circuit 18 in synchronization with the system clock signal Sc. At the time of the storage operation, the above-mentioned "1" or "0" bit data added to the data D1 and D2 is identified and allocated to a predetermined storage area and stored.

The timing signal generating circuit 20 includes a system clock signal S for synchronizing the operation of the entire system.
c and generates an address signal Sad in the storage circuit 22.
Generates r. The control circuit 24 controls the start and stop of the operation in accordance with instruction data input from a keyboard or the like by an operator, or an interface circuit for storing data in the storage circuit 22 and outputting the data to another signal processing device. Built-in.

According to this embodiment, since the data measured by the two-channel measurement system can be stored in one storage circuit by switching between the FIFO memory and the signal selection circuit, the circuit can be simplified. . Also, instead of performing time-division processing such as completing the processing of one channel and proceeding to the processing of the next channel as in the related art, the two-channel circuit performs parallel processing and the signal selection circuit 18 Since the time division processing is performed according to the channel selection signals CD1 and CD2, both channels operate in real time, and the delay time can be ignored.

In this embodiment, the case of two channels is shown. However, as shown in FIG. 3, a signal selection circuit 18 having a large number of inputs and a large number of selections is used, and the FI of each channel is used.
Output data D1, D of the FO memories 14a, 14b to 14n
2 to Dn are supplied to the respective inputs of the signal selection circuit 18. Further, the timing signal generation circuit 16 of each channel
By configuring the switching operation with the channel selection signals CD1, CD2 to CDn in synchronization with the output signals a, 16b to 16n, a circuit with an arbitrary number of channels can be realized, which is versatile.

[0019]

As described above, according to the present invention, data is temporarily held in each of the circuits of a plurality of channels.
A configuration is provided in which a FIFO memory is provided, and output data of each FIFO memory is supplied to a storage circuit via a signal selection circuit and stored therein, and the signal selection circuit switches a channel to which new data is input to the FIFO memory. As a result, the data of a plurality of channels is stored in the storage circuit in a time-division manner, so that the plurality of channels can be operated in real time. Further, even if there are a plurality of channels, the data can be stored in one system of storage circuit, so that the circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the configuration and functions of a FIFO memory;

FIG. 3 is a block diagram showing a development example of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 10a, 10b to 10n: Detector 12a, 12b to 12n: Crest discrimination circuit 14a, 14b to 14n: FIFO memory 16a, 16b to 16n: Timing signal generator 18: Signal select circuit 20: Timing signal generator 22: Storage circuit 24: Control circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-247571 (JP, A) JP-A-63-181958 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G01D 21/00 G06F 3/05 G06F 17/40 G01R 13/00-13/42

Claims (1)

(57) [Claims] 1. A data collection device having a circuit of a plurality of channels for converting a pulse signal supplied from a detection unit into digital data by a wave height discrimination circuit, and storing digital data of each channel in a storage circuit. In the channel circuit, a FIFO memory for temporarily holding digital data converted by the wave height discrimination circuit is provided, and the channel in which new data is input to the FIFO memory is switched to output the FIFO memory output data of the channel. A data collection device comprising a signal selection circuit for supplying the data to the storage circuit.