KR0141525B1 - Switching address generating circuit - Google Patents

Abstract

The present invention discloses a switching address generating circuit. The circuit inputs an address selection signal for selecting an address and a cell delay priority signal specifying the priority of the upper and lower addresses to generate the upper and lower priority reservation signals for reserving the upper and lower priorities, If the upper and lower priorities have already been reserved, a cell delay priority reservation means for generating a feedback signal, the upper priority reservation signal, the address selection signal, and an upper cell delay priority signal are generated in response to an upper cell read priority signal. And upper and lower address read signal generating means for generating a lower address read signal in response to the lower priority reservation signal, the address selection signal, and the lower cell delay priority signal, and the upper and lower address read signals. In parallel, the address of the predetermined bit inputted in parallel And a latch, and when the enable signal is input routing comprises the address of the latched predetermined bit to the upper and the lower address generating means for outputting the serial bit by bit.

Therefore, when a plurality of cells having the same destination are input, the output priority is determined according to the cell delay priority bits to generate a switching address, thereby preventing data transmission through the same input and output ports.

Description

Switching address generating circuit

1 is a block diagram of a switching address generating circuit having a cell delay priority function of the present invention.

FIG. 2 is a detailed circuit diagram of the cell delay priority reservation unit shown in FIG.

3 is a circuit diagram of the upper and lower address read signal generation circuits shown in FIG.

4 is a detailed circuit diagram of the upper and lower address generators shown in FIG.

5 is an operation timing diagram for describing an operation when three high priority asynchronous transmission mode cells having the same destination are input.

6 is an operation timing diagram for explaining the operation when three lower priority asynchronous transmission mode cells having the same destination are input.

FIG. 7 is an operation timing diagram for explaining an operation when two high priority and two low priority asynchronous transmission mode cells having the same destination are input.

The present invention relates to a switching address generating circuit, and more particularly to a switching output address generating circuit having a cell delay priority (CDP) function.

In a general asynchronous transfer mode (ATM) switch, since image data has to be processed in real time compared to general data, the effect of transmission delay is very large. Image data has a higher priority than normal data, and this priority information is determined by detecting the cell delay priority bit in the header of an asynchronous transfer mode cell (data with a specific format).

Therefore, in the asynchronous transmission mode switch, when a plurality of cells having the same destination are inputted, the priority of the output should be determined according to this cell delay priority bit to generate a switching address.

An object of the present invention is to provide a switching address generating circuit having a cell delay priority function for generating a switching address according to the priority of cell delay in switching of asynchronous transmission mode cells having the same destination.

In order to achieve the above object, the switching address generating circuit having the cell delay priority function of the present invention inputs an address selection signal for selecting an address and a cell delay priority signal specifying priority of upper and lower addresses. A cell delay priority reservation means for generating a high and low priority reservation signal for reserving a low priority, and for generating a feedback signal if the high and low priority have already been reserved; Generating an upper address read signal in response to a selection signal and an upper cell delay priority signal, and generating a lower address read signal in response to the lower priority reservation signal, the address selection signal, and the lower cell delay priority signal. Upper and lower address read signal generating means, and The upper and lower address read signals are latched in parallel to an address of a predetermined bit input, and when a routing enable signal is input, upper and lower addresses are generated to serially output the latched predetermined bit addresses in bit units. It is characterized by having a means.

Referring to the accompanying drawings, a switching address generating circuit having a cell delay priority function according to the present invention will be described.

1 is a block diagram of a switching address generating circuit having a cell delay priority function according to the present invention. The cell delay priority (CDP) reservation unit 10, the address read signal generating circuit 12, the upper address generator 14, And a lower address generator 16. In FIG. 1, a circuit for detecting a destination and generating a signal TAKE and a circuit for generating a cell delay priority (CDP) signal by extracting cell delay priority bits from the header of an asynchronous transmission mode cell are shown. Not.

The flip-flops 40, 42, 46, and 48 are reset in response to the output signals of the AND gates 28 and 32, which are the logical AND of the clear signal CLEAR and the reset signal RST, and the clock signal CK. In response to), the input signal is stored and output.

The AND gate 22 logically multiplies the signal TAKE and the cell delay priority (CDP) signal inverted by the inverter 20. The AND gate 24 ANDs the signal TAKE and the cell delay priority (CDP) signal. The OR gate 26 logically combines the signal fed back from the output with the output signal of the AND gate 22. The OR gate 30 ORs the signal fed back from the output with the output signal of the AND gate 24. The flip-flops 40 and 46 input and shift the output signal of the OR gate 26 in response to the clock signal CK.

The flip-flops 42 and 48 input and shift the output signal of the OR gate 30 in response to the clock signal CK. The AND gate 34 logically multiplies the signal fed back from the output with the output signal of the AND gate 22. The AND gate 36 logically multiplies the signal fed back from the output with the output signal of the AND gate 24. The AND gate 38 ANDs the signals fed back from the output, and the signal TAKE. The OR gate 44 ORs the output signals of the AND gates 34, 36, 38. The AND gate 50 logically multiplies the selection signal CD_SEL and the output signal of the OR gate 44 to output the feedback signal FB_CDP.

The cell delay priority (CDP) reservation unit 10 inputs a signal TAKE, a cell delay priority (CDP) signal and a cell delay priority selection signal (CDP_SEL) signal to generate a signal (TAKE) generated by the destination detection. And output reservation signals CDP_RES0 and CDP_RES1 according to the delay priority signal CDP of the asynchronous transmission mode cell and the feedback signal FB_CDP according to the plurality of cells having a destination.

The address read signal generation circuit 12 enables read signals READ0 and READ1 for reading addresses according to priorities based on the reservation signals CDP_RES0 and CDP_RES1 and the validity of the output addresses. Generate signals XRESA, XRESB.

The upper address generator 14 inputs the unique output address signal OWCNT and the input routing enable start signal XROUTE inverted by the inverter 18 and in response to the read signal READ0, the unique address of the crossbar output port. Is outputted and serially converted to generate a crossbar switching address signal XOWNER1.

The lower address generator 16 inputs the unique output address signal OWCNT and the input routing enable start signal XROUTE inverted by the inverter 18 and in response to the read signal READ1, the unique address of the crossbar output port. Is outputted and serially converted to generate a crossbar switching address signal (XOWNER2).

FIG. 2 is a detailed circuit diagram of the cell delay priority reservation unit 10 shown in FIG. 1, which includes inverters 20, 52, 54, AND gates 22, 24, 32, 34, 38, 50, and OR. Gates 26, 30, and flip-flops 40, 42, 46, 48.

The signal TAKE is a corresponding destination enable signal according to a extracted destination by detecting a virtual path identifier (VPI) and a virtual channel identifier (VCI) of an asynchronous transmission mode cell to be input, When this signal TAKE is enabled, it operates as follows according to the cell delay priority (CDP) state extracted from the header of the asynchronous transmission mode cell.

When the Cell Delay Priority (CDP) bit is 0, it means data with high priority, such as image data, having a high delay effect, and an enable signal (CDP_RES0) for reserving crossbar output in preference to low priority data. Occurs.

When the cell delay priority (CDP) bit is 1, it means information data with low priority, and generates an enable signal (CDP_RES1) for reserving the lower crossbar output in preference to the high priority.

When a cell having the same priority is input, it is first determined whether to use the cell delay priority function according to the state of the signal CD_SEL. When the selection signal CD_SEL is 1, the following operation is performed and the selection signal CD_SEL is performed. If 0, the cell delay priority function is not used.

When two or more cells having a cell delay priority (CDP) signal of 1 are input, one generates a signal (CDP_RES0) for reserving the upper crossbar output, and generates a feedback signal (FB_CDP) indicating that the cell is fed back. At this time, the signal CDD_RES1 is disabled.

When two or more cells having a zero cell delay priority (CDP) signal are input, one generates a signal (CDP_RES1) for reserving the lower crossbar output, and generates a feedback signal (FB_CDP) indicating that the cell is fed back. At this time, the signal CDDP_RES0 is disabled.

FIG. 3 is a circuit diagram of the upper and lower address read signal generation circuits shown in FIG. 1, and the inverters 60 AND gates 62, 64, 70, 72, 74, flip-flops 66, 68, and JK flip It consists of flops 80, 82, and buffers 76, 78.

The flip-flops 66 and 68 are reset in response to the reset signal RST and input a signal in response to the clock signal CK. The AND gate 72 logically multiplies the reset signal RST and the clear signal CLEAR. The JK flip-flops 80 and 82 are reset in response to the output signal of the AND gate 72 and input the signal in response to the clock signal CK.

AND gate 62 ANDs the signals TAKE, CDP_RES0, and the cell delay priority (CDP) signal inverted by inverter 60. The flip-flop 66 inputs the output signal of the AND gate 62 in response to the clock signal CK. The flip-flop 68 inputs the output signal of the AND gate 64 in response to the clock signal CK. The AND gate 70 logically multiplies the selection signal CD_SEL and the output signal of the flip-flop 66 to output the read signal READ0.

The AND gate 74 outputs the read signal READ1 by ANDing the selection signal CD_SEL and the output signal of the flip-flop 68. The JK flip-flops 80 and 82 input output signals of the AND gates 70 and 74 inverted by the inverters 76 and 78 in response to the clock signal CK and output signals XRES0 and XRES1. )

When the selection signal CD_SEL is 0, the upper address read signal READ0 for reading the crossbar output address and the signal XRESA indicating the valid address are disabled by the AND gate 70, and the lower address read signal READ1. ) And a signal XRESB indicating that it is a valid address are disabled by the AND gate 74.

When the selection signal CD_SEL is 1, the reset signals RST and the clear signal CLEAR are initialized to initialize the JK flip-flops 80 and 82 that make an effective address signal, and then, when the signal TAKE is generated, When the crossbar reservation signal CDP_RES0 is generated, a read signal READ0 is generated, and a signal XRESA indicating that an address to be read by the read signal is valid is generated.

When the lower crossbar reservation signal CD_RES1 is generated during the signal TAKE, a read signal READ1 is generated, and a signal XRESB indicating that an address to be read by the read signal is valid is generated.

4 is a detailed circuit diagram of the upper and lower address generators shown in FIG. 1, which includes an OR gate 92, flip-flops 94, 96, 98, 100, and 110, multiplexers 102, 104, 106 and 108. , Buffers 112, 114, 116, 118, and scan flip-flops 120, 122, 124, 126.

The OR gate 92 ORs the signals XROUTE and READ. Flip-flops 94, 96, 98, 100, 110, and scan flip-flops 120, 122, 124, 126 are reset in response to a reset signal RST. The flip-flops 94, 96, 98, and 100 input 1 bit of the 4-bit signal OWCNT, respectively, in response to the clock signal CK.

The flip-flop 110 inputs an output signal of the OR gate 92 in response to the clock signal CK. The multiplexers 102, 104, 106, and 108 select and output the output signals of the flip-flops 94, 96, 98, and 100, respectively, in response to the signal XROUTE, or 0, the scan flip-flops 120, Output signals fed back from the outputs of 122 and 124 are output, respectively. The buffers 112, 114, 116, 118 buffer the output signal of the multiplexers 102, 104, 106, 108. The scan flip-flops 120, 122, 124, 126 are arranged in the flip-flop 110. In response to the output signal, the output signals of the buffers 112, 114, 116, and 118 are output or the output signals to be fed back are output.

The 4-bit signal OWCNT is determined according to the size of asynchronous transfer mode switching, and is an address signal of 16 input and output ports. In the case of an asynchronous transfer mode switch having eight input and output ports, three bits are applied to the signal OWCNT.

The scan flip-flops 120, 122, 124, and 126 are enabled through the flip-flop 110 when the input read signal READ0 or READ1 is generated, and the address selected by the multiplexers 102, 104, 106, and 108 is selected. The signal OWCNT is input. The signal is shifted through the multiplexers 104, 106, and 108 in response to the clock signal CK and output as the output signal DOUTA of the scan flip-flop 126.

5 is an operation timing diagram for describing an operation when three high priority asynchronous transmission mode cells having the same destination are input.

The operation of the circuit shown in FIGS. 1, 2, 3, and 4 will be described with reference to FIG.

The flip-flops 94, 96, 98, and 100 of the upper and lower address generators shown in FIG. 4 input the 4-bit address signal OWCNT in order from 0 to 1111 in response to the clock signal CK.

The AND gate 22 of the cell delay priority reservation unit shown in FIG. 2 outputs 1 by ANDing the signal TAKE 204 of 1 and the inverted signal 0 of CDC206. The flip-flops 40 and 46 wait for the clear signal CLEAR of 0 and the reset signal RST 201 of 1 by the AND gate 28 in the reset state by the signal of 0 logically ANDed. have. The OR gate 26 then ORs the feedback output signal of 0 and the output signal of AND gate 22 of 1 and outputs a signal of 1.

This signal is input to the flip-flop 40 and shifted to output a signal of 1 through the flip-flop 46, which is inverted by the inverter 46 so that the output signal (CDP_RES0) 207 becomes zero. . At this time, the output signal CDP_RES1 becomes one. That is, a higher priority is reserved.

At this time, the AND gate 62 of the address read signal generating circuit shown in FIG. 3 is the signal TAKE 205 of 1, the signal CD_RES0 of 1, and the CDP signal of 0 inverted by the inverter 60. By multiplying 206 and outputting a signal of 1, the flip-flop 66 outputs a signal of 1 in response to the clock signal CK 202, which is output by the AND gate 70 to a signal of 1. The read signal (READ0) 210 of 1 is output by ANDing the (CDP_SEL).

At this time, the read signal READ1 211 becomes zero. Since the signal TAKE generated after this is already reserved for the higher priority, the feedback signal FB_CDP 209 is generated.

The scan flip-flops 120, 122, 124, and 126 of the address generating circuit shown in FIG. 4 input an address signal of 1 selected by the multiplexers 102, 104, 106, and 108 in response to the read signal of 1. do. When the read signal READ0 210 becomes 0, the scan flip-flops 120, 122, 124, and 126 are disabled to latch and output their own signals. Thus, the output signal XOWNER1 213 of the scan flip-flop 126 is maintained at 1. This signal is maintained until the signal XROUTE 212 becomes 1, and when it is 1, the scan flip-flop 126 outputs 0 in response to the clock signal CK 202 in order.

6 is an operation timing diagram for explaining the operation when three lower priority asynchronous transmission mode cells having the same destination are input.

The timing diagram shown in FIG. 6 is for explaining the operation when three signals CD1 are input. An address of 1 is selected by the signal TAKE, and the lower priority address generator uses a clock signal ( In response to CK), it can be known by sequentially generating signals 1 to 000, which are the least significant bits.

FIG. 7 is an operation timing diagram for explaining an operation when two high priority and two low priority asynchronous transmission mode cells having the same destination are input.

FIG. 7 is a timing diagram illustrating an operation when two signals CD of 1 are input and two signals CD of 0 are input. The upper address is selected, and the upper and lower address generators generate the signals of 0 to 010, which are the least significant bits, in order in response to the clock signal CK, and the signals of 1 to 000, which are the least significant bits, in the lower addresses. You can see this as it happens.

Accordingly, the switching address generating circuit of the present invention determines the priority of the output according to the cell delay priority bit when multiple cells having the same destination are input, generates a switching address, and transmits data through the same input and output ports. This can eliminate data conflicts.

Claims (4)

Inputs an address selection signal for selecting an address and a cell delay priority signal specifying priority of upper and lower addresses to generate upper and lower priority reservation signals for reserving upper and lower priorities; Cell delay priority reservation means for generating a feedback signal if a lower priority has already been reserved; An upper address read signal is generated in response to the upper priority reservation signal, the address selection signal, and an upper cell delay priority signal, and generated to the lower priority reservation signal, the address selection signal, and the lower cell delay priority signal; Upper and lower address read signal generating means for generating a lower address read signal in response; And an upper and lower address for latching an address of a predetermined bit input in parallel in response to the upper and lower address read signals, and outputting the address of the latched predetermined bit serially in bit units when a routing enable signal is input. And a switching address generating circuit having a generating means. 2. The apparatus of claim 1, wherein the cell delay priority reservation means comprises: first logical multiplication means for ANDing the address selection signal and the inverted cell delay priority signal; Second logical product means for ANDing the address selection signal and the cell delay priority signal; First logical sum means for ORing the output signal of the first logical multiplication means and the inverted higher priority reservation signal; Second logical sum means for ORing the output signal of the second logical multiplication means and the inverted lower priority reservation signal; First latch means for latching an output signal of the first logical sum means to generate the inverted higher priority reservation signal; And second latch means for latching an output signal of the second logical sum means to generate the inverted lower priority reservation signal. 2. The apparatus of claim 1, wherein the upper and lower address read signal generating means comprises: first logical multiplication means for ANDing the address selection signal, the upper priority reservation signal, and the inverted cell delay priority signal; First latch means for latching an output signal of the first logical multiplication means to generate the upper address read signal; Second logical multiplication means for ANDing the address selection signal, the lower priority reservation signal, and a cell delay priority signal; And second latch means for latching an output signal of said second logical product to generate said lower address read signal. 2. The apparatus of claim 1, wherein the upper and lower address generating means latch an address of a predetermined bit input in parallel in response to the upper address read signal, and serially latch the latched signal in response to the routing enable signal. An upper address generating means for outputting to And lower address generating means for latching an address of a predetermined bit input in parallel in response to the lower address read signal and outputting the latched signal serially in bit units in response to the routing enable signal. A switching address generation circuit.