JPH04242121A - Data collecting apparatus - Google Patents

Abstract

PURPOSE:To perform high-speed wave-height discrimination for a plurality of signals to be measured and to simplify the circuit scale in a data collecting apparatus which discriminates the amplitude of a pulse signal whose voltage amplitude is changed with time and stores the value into a memory circuit as the digital data. CONSTITUTION:FIFO memories 14a and 14b which temporarily store data in a plurality of channel circuits are provided. The output data of the respective FIFO memories 14a and 14b are supplied and stored in a memory circuit 22 through a signal selecting circuit 18 in this constitution. The channel through which new data are inputted into the FIFO memories 14a and 14b is changed with the signal selecting circuit 18. Thus, the data which are collected with a plurality of the channels are stored in one memory circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data acquisition device that determines the amplitude of a pulse signal whose voltage amplitude changes with time and stores it in a storage circuit as digital data.

0002

2. Description of the Related Art A data acquisition device equipped with a pulse height discrimination circuit as shown in FIG. 4 is conventionally known. In the same figure, 2
is a detection unit that has a built-in sensor, etc. for measuring the object to be measured. For example, in a density measuring device for measuring the density of the object to be measured, radiation emitted from a radiation source and passing through the object to be measured is a detection unit. It is equipped with a conversion function such as detecting an incoming radiation pulse and outputting an electric signal Sin having an amplitude corresponding to the energy of the radiation pulse.

[0003] Reference numeral 4 denotes a pulse height discrimination circuit which detects the electric signal Sin from the detection section 2 that is larger than a predetermined threshold level Vth, converts the amplitude into digital data D, and outputs the signal. That is, the wave height discrimination circuit 4 is the detection circuit 4a.
, an A/D converter 4b, and a timing signal generation circuit 4c. As shown in FIG. 5, the detection circuit 4a compares the electrical signal Sin and the threshold level Vth point by point, and changes the logic value level from "L" at the timing when the amplitude of the electrical signal changes from Sin<Vth to Sin≧Vth. The logic signal S1 which becomes “H” level and the amplitude of the electrical signal are
Logic signal S whose logic value level changes from “L” to “H” level at the timing of changing from >Vth to Sin≦Vth
Outputs 2.

The timing signal generating circuit 4c generates a logic signal S3 that is at the "H" level during a period τ from time t1 when the logic signal S1 rises to the "H" level to time t2 when the logic signal S2 rises to the "H" level. During this period τ, the A/D converter 4b digitally converts the electrical signal Sin. Also, although not shown, A/
These comparisons can be performed by inputting the electric signal Sin to a plurality of analog comparators in parallel instead of the D converter 4b, and setting the comparison reference voltages of the respective analog comparators to be different from each other. The logic output group of the device is the electric signal Sin
A conversion circuit configured to generate digital data D corresponding to 1 is used, and a pulse height discrimination circuit is used that performs conversion timing in synchronization with the timing signal S3 of the timing signal generation circuit 4c.

Reference numeral 6 denotes a storage circuit consisting of a semiconductor memory, which stores the detection data D transferred from the pulse height discrimination circuit 4. A control circuit 8 generates a synchronization signal for synchronously controlling the timing of the discrimination operation of the pulse height discrimination circuit 4 and the timing of the storage operation of the memory circuit 6 at a predetermined period. The circuit configured as described above detects the electrical signal Sin one by one, converts it into digital data D, and stores it in the storage circuit, thereby enabling digital signal processing.

[0006]

[Problems to be Solved by the Invention] However, in such a data collection device, when the number of detection items increases, in other words, when a detection section equipped with a large number of sensors or a plurality of detection sections are applied, the number of detection items increases. When performing wave height discrimination processing on each of a large number of electrical signals generated at each sensor, a large number of circuits shown in Fig. 4 may be installed in parallel for each sensor, or the output signals of the sensors may be scanned in a time-division manner and the wave heights may be determined in order. Means for performing discrimination processing is used, but in the case of the former, when a plurality of circuits are provided, the problem arises that the entire circuit becomes extremely large and complicated.
In the case of the latter time-sharing processing, a problem arises in that the processing speed becomes slow.

The present invention has been developed in view of these problems, and is a data processing system that can perform high-speed pulse height discrimination processing on a plurality of signals under test and can simplify the circuit scale. The purpose is to provide a collection device.

[0008]

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a FIFO memory for temporarily holding data in each of a plurality of channel circuits.
The output data of the IFO memory is supplied to the storage circuit via the signal selection circuit and stored therein, and the signal selection circuit switches the channel to which new data is input to the FIFO memory, allowing data to be collected on multiple channels. The data is stored in one memory circuit.

[0009]

[Operation] According to the data acquisition device with such a configuration, even if multiple channels operate in parallel, the data of the collected channels is selected and stored in a common storage circuit, so multiple channels can be processed in real time. It becomes possible to operate it. Furthermore, even if there are multiple channels, data is stored in one storage circuit, so the circuit can be simplified.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data collection device according to the present invention will be described below with reference to FIG. First, the circuit configuration will be explained based on FIG. 1. 10a and 10b are each a separate detection section. For example, in the case of a density measuring device, a sensor etc. for measuring the object to be measured is built-in, A radiation pulse passing through the object to be measured is measured to generate electrical signals Sin1 and Sin2 with amplitudes corresponding to the energy of the radiation pulse.
It is equipped with conversion functions such as outputting .

[0011] Note that the circuit related to the first detection section 10a is
The circuit related to the channel CH1 and the second detection section 10b is referred to as a second channel CH2. Each channel CH1,
The internal circuits of CH2 have similar configurations as shown in the figure, so they will be explained together: detection units 10a, 10b
The electrical signals Sin1 and Sin2 output by the wave height discrimination circuits 12a and 12b and the timing signal generation circuit 16a
, 16b and output from the pulse height discrimination circuits 12a, 12b are supplied to the FIFO memories 14a, 14b.

The pulse height discrimination circuits 12a and 12b incorporate A/D conversion for converting analog input signals Sin1 and Sin2 into predetermined bits of digital data D1 and D2, respectively. As shown in FIG. 4, the timing signal generation circuit 16a generates an electric signal Sin1 and a threshold level Vth.
1 is compared point by point, and the amplitude of the electrical signal is Sin1 < Vt
The logic signal S11 whose logic value level changes from "L" to "H" level at the timing when Sin1≧Vth1 changes from h1, and the amplitude of the electrical signal is Sin1 > Vth1.
A logic signal S whose logic value level changes from “L” to “H” level at the timing when Sin1 ≦Vth1 changes from
21 is generated internally, and a logic control signal S31 is generated which remains at the "H" level during the period from the time when the logic signal S11 rises to the "H" level until the time when the logic signal S21 rises to the "H" level, and during this period. In the step, the electric signal Sin1 is digitally converted into digital data D1 of predetermined bits N (for example, 10 bits) by an A/D converter.

[0013] Also, one timing signal generation circuit 16b
Similarly, it generates a logic control signal S32 for causing the A/D converter to digitally convert the electric signal Sin2 into digital data D2. As shown in FIG. 2, the FIFO memories (first-in, first-out memories) 14a and 14b have an M-stage shift register configuration in which each stage is set to N bits (for example, 10 bits or more). , input from the least significant bit (MSB) to the highest significant bit (LSB)
By shifting to the side in synchronization with the generation timing of logic control signals S31 and S32 and a system clock signal Sc from a timing signal generator 20, which will be described later, data input first is output first.

[0014] Furthermore, each FIFO memory 14a, 14b
adds bit data for identifying which FIFO memory it is to the digital data D1 and D2 and outputs the resultant data. For example, bit data of "1" is added to the most significant bit of the digital data D1, and "0" is added to the most significant bit of the digital data D2. The signal selection circuit 18 is composed of a multiplexer circuit that transfers either one of the output data of the FIFO memories 14a, 14b to the storage circuit 22 side according to the channel selection signals CD1, CD2. That is, when the FIFO memory 14a outputs the most significant data in synchronization with the logic control signal S31, the channel selection signal CD1 is output in synchronization with this timing.
occurs, and the signal select circuit 18 selects the FIFO memory 14.
When the data of a is transferred to the storage circuit 22, and conversely, the FIFO memory 14b outputs the most significant data in synchronization with the logic control signal S32, the channel selection signal CD2 is generated in synchronization with this timing, and the signal select circuit 18 is F
The data in the IFO memory 14b is transferred to the storage circuit 22.

Note that the signal selection circuit 18 also operates in synchronization with the system clock signal Sc from the timing signal generation circuit 20. The storage circuit 22 is composed of a random access memory (RAM) and receives a system clock signal Sc.
The data from the signal select circuit 18 is sequentially stored in synchronization with the . Furthermore, during the storage operation, data D1 and D2
The bit data of "1" or "0" added to the above is identified, and allocated and stored in respective predetermined storage areas.

The timing signal generation circuit 20 generates a system clock signal S for synchronizing the operation of the entire system.
c and also sends an address signal S to the memory circuit 22.
generate adr. The control circuit 24 is an interface circuit, etc. that controls the start and stop of operations according to instruction data input by the operator from a keyboard, etc., and stores the data in the storage circuit 22 and outputs the data to other signal processing devices. Built-in.

According to this embodiment, the data measured by the two-channel measurement system can be stored in one storage circuit by switching between the FIFO memory and the signal selection circuit, making it possible to simplify the circuit. . In addition, instead of performing time-sharing processing in which processing of one channel is completed and then processing of the next channel is performed as in the past, the circuits of two channels perform parallel processing and the signal selection circuit 18 performs parallel processing. Channel selection signal CD1, CD2
Since time-sharing processing is performed according to the timing, both channels operate in real time, making it possible to ignore delay time.

Although this embodiment shows the case of two channels, as shown in FIG. 3, a signal select circuit 18 with multiple inputs and a large number of selections is used to
Output data D1 of IFO memories 14a, 14b to 14n
, D2 to Dn are supplied to each input of the signal select circuit 18. Furthermore, by configuring the switching operation to be performed using the channel selection signals CD1, CD2-CDn in synchronization with the output signals of the timing signal generation circuits 16a, 16b-16n of each channel, a circuit with an arbitrary number of channels can be realized. It is possible and versatile.

[0019]

As explained above, according to the present invention, each of a plurality of channel circuits is provided with a FIFO memory for temporarily holding data, and the output data of each FIFO memory is stored via a signal selection circuit. By supplying the data to the circuit and storing it, the signal select circuit switches the channel to which new data is input to the FIFO memory, so that the data of multiple channels can be stored in the storage circuit in a time-sharing manner. It is possible to operate multiple channels in real time. Furthermore,
Even if there are multiple channels, the data is stored in one storage circuit, so the circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Figure 2] Explanatory diagram showing the configuration and functions of FIFO memory

[Figure 3
]Block diagram showing an example of development of the embodiment

[Figure 4] Block diagram showing the configuration of a conventional example

[Fig. 5] Timing chart for explaining the operation of the conventional example

[Explanation of symbols]

10a, 10b to 10n: detection units 12a, 12b to 12n: pulse height discrimination circuits 14a, 14b
~14n: FIFO memory 16a, 16b~16n: Timing signal generation circuit 18: Signal selection circuit 20: Timing signal generation circuit 22: Storage circuit 24: Control circuit

Claims (1)

[Claims] 1. A data acquisition device comprising a plurality of channels of circuitry for converting a pulse signal supplied from a detection section into digital data using a pulse height discriminator circuit, and storing digital data of each channel in a storage circuit, wherein each of the above-mentioned The channel circuit is equipped with a FIFO memory that temporarily holds the digital data converted by the pulse height discriminator circuit.
1. A data acquisition device comprising a signal selection circuit that switches a channel through which new data is input to an FO memory and supplies output data of the FIFO memory of the channel to the storage circuit.