JPH0679055B2 - Integrated circuit test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Field of Use of the Present Invention> The present invention sequentially inputs pattern signals to a plurality of input terminals of an integrated circuit and outputs output data output from a plurality of output terminals of the integrated circuit. The present invention relates to an integrated circuit test device for analyzing and testing the operation of this integrated circuit.

<Prior Art> (FIG. 4) In order to efficiently test the response of an output to an input data signal of an integrated circuit having a plurality of input terminals and output terminals,
Conventionally, a predetermined parallel pattern signal is sequentially input to a plurality of input terminals of this integrated circuit, and output data output from the plurality of output terminals is predetermined (that is, a pattern signal to be input). An integrated circuit tester is used which is adapted to be compared with reference data.

FIG. 4 is a block diagram showing an example of such a conventional integrated circuit test apparatus.

In the figure, M input terminals 2 ₋₁ to
2-m is a pattern generator of the integrated circuit test apparatus 10.
11 M parallel outputs are connected, and a maximum of 2 ^M different parallel pattern signals are given to the input terminals 2 _-1 to 2-m of the DUT 1.

Further, the N output terminals 3 _{-1 to} 3 _-n of the DUT 1 are
Output data from the output terminals 3 _{-1 to} 3 _-n ,
It is input to the acquisition circuits 12 _{-1 to} 12 _-n for reading in synchronization with the clock signal of the pattern generator 11.

The output data output from the acquisition circuits 12 _{-1 to} 12 _-n are sequentially stored in the memory 13 as N-bit parallel data.

The address of this memory 13 counts the clock signal,
It is specified by the address specifying circuit 14 which outputs the address value corresponding to the counting result.

In this way, when the number of output data sequentially stored in the storage device 13 reaches the desired number of data (maximum 2 ^M ), the output data stored in the storage device 13 is
And is compared with predetermined reference data, and the comparison result is output, for example.

Thus, the number of input / output terminals of the DUT to be tested and its operating speed vary depending on the integrated circuit.

Therefore, in particular, the number of acquisition circuits 12 _{-1 to} 12 _-n and the storage capacity of the storage unit 13 are provided in advance by the number and the capacity corresponding to the maximum number of output terminals of the measured integrated circuit to be tested, Further, the acquisition circuits 12 _{-1 to} 12 _-n and the storage unit 13 have an operating speed corresponding to the upper limit frequency of the integrated circuit under test to be tested.

<Problems to be Solved by the Present Invention> However, when the degree of integration and the operating speed of an integrated circuit increase as in today's day, in the conventional integrated circuit test device as described above, the output of the measured integrated circuit is increased. The number of acquisition circuits corresponding to the number of output terminals increases as the number of terminals increases.
_{-1 to} 12 _-n and the storage capacity of the storage device 13 are required,
For this reason, the integrated circuit test equipment becomes large-scale,
As the memory device 13, a memory device capable of high-speed operation and having a large memory capacity must be used, and there is a problem that the cost of the integrated circuit test device becomes very high.

Also, when testing the measurement integrated circuit having an operating speed of up to a GHz band is the upper limit frequency, the parallel output data signals from the output terminals of the metering integrated circuit phase shift and the acquisition circuit 12 _-1 12 _- Variations in the characteristics of _n (delay time, output waveform rise time, fall time, etc.), or memory
Due to the limitation of the operation speed of 13, the parallel output data cannot be stored in the storage device 13 without fail, and the test frequency is limited.

<Means of the Present Invention> In order to solve the above-mentioned problems, the integrated circuit test apparatus of the present invention initializes by a start signal and outputs a series of predetermined parallel pattern signals to a plurality of inputs of the measured integrated circuit. A pattern generator for sequentially inputting in parallel to terminals, and a selection circuit for sequentially selecting and outputting any one of output data signals output from a plurality of output terminals of the integrated circuit under test according to an output selection signal; And a converter that converts and outputs a series of serial output data signals output from the output terminals into parallel output data signals for each predetermined data length,
A storage device that sequentially stores output data signals output from this converter and outputs the stored output data by a transfer signal and a comparison analysis of the output data from this storage device based on predetermined reference data. Each time a predetermined number of output data is stored in the data analysis unit and the storage device, a transfer signal is output to the storage device, and the predetermined number of output data is transferred to the data analysis unit, or data analysis is performed. And a control unit for outputting a start signal and an output selection signal to the pattern generator and the selection circuit, respectively, when the comparison analysis of the predetermined number of output data is completed by the unit.

<Operation> Therefore, the output data from the output terminal selected by the selection circuit among the plurality of output terminals of the measured integrated circuit which has received a series of pattern signals output in parallel from the pattern generator is predetermined by the converter. It is converted into parallel data for each data length and stored in the storage device.

When a predetermined number of output data is stored in the storage device, the output data is transferred to the data analysis unit by the transfer signal from the control unit and compared and analyzed based on the predetermined reference data.

The control unit outputs a start signal and an output selection signal when the predetermined number of output data is transferred to the data analysis unit or when the data analysis unit completes the comparative analysis of the predetermined output data. , The pulse generator is initialized, the selection circuit is switched, and output data signals from different output terminals of the integrated circuit under test are selectively output.

<One Embodiment of the Present Invention> (FIG. 1) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an integrated circuit test apparatus 20 according to an embodiment of the present invention.

In the figure, reference numeral 21 has at least M number of output terminals 2 _-1 to 2-m of the integrated circuit 1 to be measured, and sequentially outputs a predetermined series of parallel pattern signals to the output terminals. It is a pattern generator. This pattern generator 21
Is almost synchronized with the pattern signal (that is, the delay of the output signal with respect to the input signal of the integrated circuit under test 1 is taken into consideration).
When a clock signal is output and a start signal from the control unit 32, which will be described later, is received, a strobe signal is output and initialization is performed to output a series of predetermined parallel pattern signals.

Reference numeral 22 denotes a selection circuit which is composed of, for example, a multiplexer and which selectively outputs any one of the output data signals output from the output terminals 3 _{-1 to} 3 _{-n of the} integrated circuit under test 1.

This selection circuit is sequentially switched each time it receives an output selection signal from the control unit 32 described later.

Reference numeral 23 is an acquisition circuit which is composed of a delay type (D type) flip-flop and the like, which waveform-shapes the serial output data signal from the selection circuit 22 as a data signal synchronized with the clock signal, and outputs this.

Reference numeral 24 denotes a converter which is composed of a demultiplexer or the like and sequentially switches and outputs the serial output data signal from the acquisition circuit 23 to the plurality of P parallel lines L _{-1 to} L _-p in synchronization with the clock signal.

Therefore, the serial output data signal from the acquisition circuit 23 is output to the parallel lines L _{-1 to} L _-p at the P-divided operating speed.

The operating position of this converter 24 is initialized (for example, L ₋₁ ) by the strobe signal from the pattern generator 21.

Reference numeral 25 is a storage device that sequentially stores the output data signals of the P column output from the converter 24 as parallel data at the addresses designated by the addressing circuit 26.

This memory 25 can store a data signal input at a high speed (for example, several 100 MHz), and at least one output terminal 3 _{-1 to} 3 _{-n of the} integrated circuit under test 1 should be analyzed. It has a storage capacity corresponding to the number of data.

Therefore, the storage device 25 can store serial output data having an operation speed P times the operation upper limit speed of the storage device 25 by the conversion operation of the converter 24.

The storage device 25 outputs the stored output data in response to a transfer signal from the control circuit 32 described later.

The addressing circuit 26 is initialized by the strobe signal from the pattern generator 21, counts the clock signal, and stores the address value corresponding to the count result in the memory 25.
Send to.

27 stores the output data transferred from the storage device 25,
The data analysis unit compares this with reference data determined in advance for the pattern signal and outputs the comparison result.

The data analysis unit 27 stores the output data transferred from the storage unit 25 in a predetermined storage area as output data for each output terminal of the DUT 1, and a predetermined data storage unit 28. The reference data memory 29 storing the data (reference data) to be responded to by the integrated circuit under test to the pattern signal, and the output data stored in the data memory 28 and the reference data memory 29. Comparator that compares the reference data that is present and outputs this comparison result
30 are provided.

The data memory 28 has a low operation speed and has a memory capacity corresponding to the number of output data output from all the output terminals 3 _{-1 to} 3 _-n of the integrated circuit under test 1.

The output terminal of the integrated circuit under test 1 to the data memory 28
The addressing corresponding to 3 _{-1 to} 3 _-n is performed by the control unit 32 described later.
Is performed by the address designating circuit 31 which counts the transfer signals from and sequentially outputs the address value corresponding to the counting result.

32 is a predetermined number (that is, the number of data to be analyzed of the selected output terminal) stored in the memory 25,
A transfer signal is output to the storage unit 25, the stored output data is transferred to the data analysis unit 27, a start signal is sent to the pattern generator 21 after this transfer, and an output selection signal is sent to the selection circuit 22. It is a control unit for sending out.

The control unit 32 controls the addressing circuits 26 and 31 to specify the number of data to be stored in the storage device 25 and the data storage device 28, and to store the number of data items specified in the storage devices 25 and 28, respectively. When it is detected that the data is stored, the address designation is stopped.

<Operation> (FIGS. 2 to 3) Next, with respect to the operation of the above-described embodiment, for example, in the case of testing the integrated circuit under test 1 having 10 input terminals and 8 output terminals and an operating speed of 1 GHz. Will be described.

After the input terminals and 2 _-1 to 2 _-10 and output terminals 3 _{-1 to} 3 _-8 of the measured integrated circuit 1 are connected to the pattern generator 21 and the selection circuit 22, respectively, as shown in FIG. Pattern generator
When 21 is started, the input terminals 2 ₋₁ to 2 of the integrated circuit under test 1 are measured.
_-10 includes a series of predetermined 10-bit parallel pattern signals (A ₁ B ₁ C ₁ ...... J ₁ ), as shown in FIG.
(A ₂ B ₂ C ₂ …… J ₂ ), …… are sequentially input at a speed of 1 GHz.

At this time, _assuming that the output terminal 3 _-1 of the integrated circuit under test ₁ is selected by the selection circuit 22, the selection circuit 22 outputs serial output data signals as shown in FIG. 2 (b).
a ₁ , a ₂ , ... Are sequentially output. This output data signal
The a ₁ , a ₂ , ... Are shaped and output by the acquisition circuit 23 and input to the converter 24.

The output data signals a ₁ , a ₂ , ..., Input to the converter 24 are
In synchronization with the clock signal, it is sequentially switched and output to a plurality of P (for example, 8) parallel lines.

Therefore, the initial address of the memory 25 (and 00 address), as shown in FIG. 2 (c), the output data a ₁ ~a ₈ 8
As parallel data of bits, for example, 125MHz (1GHz / 8)
It is stored at the operating speed of.

Similarly, the output data sequentially output from the converter 24 are sequentially stored in the storage device 25 as 8-bit parallel data.

In this way, to be stored in the output terminal 3 output data output from the _-1, for example, 200 storage unit 25 of the metering integrated circuit 1 (i.e., output data a ₁ ~a ₂₀₀ is stored), A transfer signal is output from the control unit 32 to the storage device 25.

Therefore, the 200 output data a ₁ stored in the memory 25
3 to a ₂₀₀ are stored in a predetermined area of the data storage unit 28 of the data analysis unit 27, as shown in FIG.

When this transfer is completed, the control unit 32 determines that the pattern generator 21
Send a start signal to.

Therefore, the pattern generator 21 again generates a series of 10-bit parallel pattern signals (A ₁ B ₁ C ₁ ...... J ₁ ), (A ₂ B ₂ C ₂ ......
J ₂ ), ... Is sent to the input terminals 2 _-1 to 2 _-10 of the integrated circuit under test 1.

At the same time as this start signal, the output selection signal is
Since the data is output from 32 to the selection circuit 22, the selection circuit 22 is switched to the output terminal 3 _-2 of the integrated circuit under test 1.

Therefore, similarly to the above, the serial output data signals b ₁ , b ₂ , ... Output from the output terminal 3 _-2 are the acquisition circuits.
It is sent to the converter 24 via 23 and is sequentially stored in the memory 25 for each 8-bit parallel output data (b ₁ b ₂ …… b ₈ ), (b ₉ b ₁₀ …… b ₁₆ ) ,. It

When the number of output data b ₁ , b ₂ , ... From the output terminal 3 _-2 reaches 200, a transfer signal is again sent from the control unit 32 to the memory 25, and these output data b _{1 to} b ₂₀₀ are shown in FIG. As shown in, the data is stored in a predetermined area of the data storage 28.

After that, the same operation is repeated, and the output data (a _{1 to} a ₂₀₀ ), (b ₁ ) output from all the output terminals 3 _{-1 to} 3 _-8 of the integrated circuit under test 1 are stored in the data memory 28. ~ B ₂₀₀ ), …… (h ₁
~ H ₂₀₀ ) are stored in respective predetermined areas.

In this way, the output data stored in the data storage unit 28 is compared with the reference data stored in the reference data storage unit 29 by the comparator 30, and the comparison result is output.

<Other Embodiments of the Present Invention> In the above embodiment, the output data of all output terminals of the integrated circuit under test 1 are stored in the data storage unit 28 of the data analysis unit 27.
Although the comparison with the reference data is performed after the storage is stored in the storage device, it may be performed each time the output data from the selected one output terminal is transferred from the storage device 25.

Further, the data analysis unit 27 may analyze not only the comparison result of the output data and the reference data but also the characteristic of the measured integrated circuit based on the comparison result.

<Effects of the Present Invention> Since the integrated circuit test apparatus of the present invention is configured as described above, it is possible to cope with an increase in the number of output terminals of the integrated circuit under test by simply increasing the number of selection circuits selected. A memory device capable of performing high-speed operation needs to have a memory capacity equivalent to the number of output data output from one output terminal of the integrated circuit under test, and the device scale is small and the cost is low. It will be much lower.

Even when the test frequency is high, it is not affected by the phase shift between multiple output terminals of the IC under test, the delay time of the acquisition circuit, the variation of the output waveform rise time, the fall time, etc. Since the serial output data from the circuit is converted into parallel signals in multiple columns and stored, the test can be performed at a significantly higher operating speed than the operating speed of the memory, and the test frequency is not limited and the frequency It is possible to reliably perform the test at the upper limit frequency of the measured integrated circuit having high characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 (a) is a diagram showing a pattern signal, and FIG. 2 (b) is a diagram showing a selectively output output data signal. Figure 2 (c)
FIG. 3 is a diagram showing output data stored in a main part (memory device 25) of one embodiment, and FIG. 3 is a main part (data analysis part of one embodiment.
It is a figure which shows the output data memorize | stored in 27). FIG. 4 is a block diagram showing a conventional device. 1 ... Integrated circuit under test, 20 ... Integrated circuit tester, 21 ...
… Pattern generator, 22 …… Selection circuit, 24 …… Converter, 25
...... Memory device, 27 ...... Data analysis unit, 32 ...... Control unit.

Claims (1)

[Claims] 1. An integrated circuit under test, wherein parallel pattern signals are sequentially input to a plurality of input terminals of the integrated circuit under test, and output data signals output from a plurality of output terminals of the integrated circuit under test are analyzed. An integrated circuit tester for testing the operation of a pattern generator for sequentially inputting a series of predetermined parallel pattern signals initialized by a start signal to a plurality of input terminals of the integrated circuit under test in parallel. A selection circuit for sequentially selecting and outputting any one of output data signals output from a plurality of output terminals of the integrated circuit under test according to an output selection signal; and the integrated circuit under test selected by the selection circuit. Output a series of serial output data signals from
Convert to a parallel output data signal for each predetermined data length,
A converter that sequentially outputs, and an output data signal that is output from the converter are sequentially stored,
A storage device that outputs the stored output data as a transfer signal, a data analysis unit that compares and analyzes the output data output from the storage device based on predetermined reference data, and a predetermined number of storage devices in the storage device. Each time the output data is stored, a transfer signal is output to the storage device and the predetermined number of output data is transferred to the data analysis unit, or the data analysis unit compares the predetermined number of output data. An integrated circuit test apparatus comprising: a control unit that outputs a start signal and an output selection signal to the pattern generator and the selection circuit, respectively, when analysis is completed.