JP2003057292A - Semiconductor integrated circuit tester, testing board and semiconductor integrated circuit testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-speed test of semiconductor devices. SOLUTION: This is a semiconductor integrated circuit tester for testing the operation of each semiconductor device, by dividing a large number of semiconductor devices into a plurality of test groups, and successively supplying a testing signal to the semiconductor devices in each test group. The tester is provided with testing boards 1, which have a large number of mounted IC sockets a11 to amn for fitting semiconductor devices, and clock selection supply means S for performing a changeover of clock signals, supplied from outside in synchronization with a group selection signal for specifying a test group and supplying it to each of the IC sockets a11 to amn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test device, a test board, and a semiconductor integrated circuit test method.

[0002]

2. Description of the Related Art As one type of semiconductor integrated circuit test equipment,
There is a test burn-in system. This test burn-in apparatus is an apparatus for performing a burn-in (aging) of a semiconductor device (device under test) to be tested in an operating state under a predetermined temperature environment, and making a pass / fail judgment. In burn-in using such a test burn-in device, a plurality of semiconductor devices are mounted on a test burn-in board (test board) via IC sockets, and a plurality of such test burn-in boards are stored in the test burn-in device. To be tested. Each semiconductor device is electrically connected to the test burn-in device via a circuit pattern formed on the test burn-in board, receives power from the test burn-in device and various test signals, and outputs the test signals. Output a response signal to the test burn-in device.

[0003]

By the way, the test burn-in board performs a parallel test on a plurality of semiconductor devices by supplying a test signal to each of the mounted semiconductor devices in parallel. That is, each signal line formed on the test burn-in board is connected in parallel to a plurality of semiconductor devices. For this reason, the driver of the test burn-in device that supplies a test signal to a plurality of semiconductor devices via such a signal line has an input capacitance of the input terminal of each semiconductor device and an input capacitance of each terminal of the IC socket. A relatively large capacity load consisting of an electric capacity and an electrostatic capacity proportional to the wiring distance of the signal line and the like is connected.

Since such a large capacitive load distorts the test pulse signal so as to prolong the rise time and fall time of the test pulse signal output from the driver,
Restricting the supply of high frequency test pulse signals to semiconductor devices. Although it is possible to realize a high-speed test of a semiconductor device by increasing the frequency of the test signal, in the conventional test burn-in board, since the maximum frequency of the test signal is limited by the large capacitive load, High speed test could not be realized. In particular, in the test of a digital semiconductor integrated circuit such as a memory, the clock signal which is the basis of the operation is the test signal of the highest frequency, and the high frequency test enables the high-speed test.

On the other hand, each semiconductor device on the test burn-in board is divided into a plurality of test groups, and a scan signal (group selection signal) is individually input to each test group. That is, the test groups are sequentially designated based on the scan signal, and the semiconductor devices are sequentially tested for each test group. However, since the clock signal is commonly wired to all semiconductor devices (that is, IC sockets) on the test burn-in board, when a certain semiconductor device is a defective device in which the input end of the clock signal is short-circuited, for example, The influence of this defective device extends to other normal semiconductor devices and the clock signal is not normally supplied. That is, when a certain test group has a defective device related to the input terminal of the clock signal, the influence of this defective device spreads to other test groups and the test of all the test groups on the test burn-in board cannot be executed. Leading to.

The present invention has been made in view of the above-mentioned problems, and aims at the following points. (1) Realize high-speed testing of semiconductor devices. (2) An operation test is performed without affecting a defect related to a clock signal input terminal in a semiconductor device of a certain test group to a test of another test group.

[0007]

In order to achieve the above object, the present invention relates to a semiconductor integrated circuit test apparatus according to a first aspect.
A semiconductor integrated circuit test apparatus for testing the operation of each semiconductor device by grouping a large number of semiconductor devices into a plurality of test groups and sequentially supplying a test signal to the semiconductor devices of each test group as a means of A large number of IC sockets for mounting semiconductor devices are mounted, and a clock selection supply means for switching the clock signal supplied from the outside in synchronization with a group selection signal designating the test group and supplying it to each IC socket is provided. Adopt a means of having the test board provided.

A second aspect of the semiconductor integrated circuit test apparatus
In the first means, the clock selection supply means is a plurality of open / close switches provided in the middle of the clock signal supply wiring for each test group and using the group selection signal as a switching signal. adopt.

As the third means relating to the semiconductor integrated circuit test apparatus, the means applied to the test burn-in apparatus in the first or second means is adopted.

On the other hand, in the present invention, as a first means relating to the test board, a large number of semiconductor devices are divided into a plurality of test groups, and a test signal is sequentially supplied to the semiconductor devices of each test group. It is housed in a semiconductor integrated circuit tester that tests the operation of each semiconductor device, and the semiconductor device I is mounted on the semiconductor integrated circuit tester.
A test board in which a large number of C sockets are mounted and test signals are supplied in parallel to semiconductor devices mounted in respective IC sockets, and a clock signal supplied from the outside specifies the test group. A means for providing a clock selection supply means for switching to and synchronizing with the group selection signal and supplying it to each IC socket is adopted.

As the second means relating to the test board, in the first means, the clock selection supply means is provided in the middle of the clock signal supply wiring for each test group and switches the group selection signal. A means of being a plurality of open / close switches for signals is adopted.

As a third means relating to the test board,
In the first or second means, the semiconductor integrated circuit test device is a test burn-in device.

Further, according to the present invention, as a first means relating to the semiconductor integrated circuit test method, a large number of semiconductor devices are divided into a plurality of test groups and a test signal is sequentially supplied to the semiconductor devices of each test group. A method of testing the operation of each semiconductor device by
A means for performing an operation test of each semiconductor device by switching and supplying a clock signal supplied to the semiconductor device as one of the test signals for each test group is adopted.

As a second means relating to the semiconductor integrated circuit testing method, in the first means, an open / close switch is provided in the middle of the clock signal supply wiring for each test group, and the open / close switch is designated to the test group. The means for switching and supplying the clock signal to each test group by opening and closing based on the group selection signal is adopted.

As the third means relating to the semiconductor integrated circuit testing method, the means applied to the test of the semiconductor device using the test burn-in device in the first or second means is adopted.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit test device, a test board and a semiconductor integrated circuit test method according to the present invention will be described below with reference to the drawings.

FIG. 1 is a system configuration diagram of a test burn-in device (semiconductor integrated circuit test device) in this embodiment. As shown in this figure, this test burn-in device includes a plurality of test burn-in boards 1 (test boards), a constant temperature bath 2, a basic control circuit 3, a pattern generation circuit 4, a bias power supply circuit 5, a driver / comparator circuit 6 and It is composed of a controller 7 and the like.

The constant temperature bath 2 accommodates a plurality of test burn-in boards 1 in a rack, and a semiconductor device (for example, a digital semiconductor device such as a memory IC) mounted on each test burn-in board 1 is subjected to a temperature load. give. A test signal is input from the driver / comparator circuit 6 to each semiconductor device in such a temperature load state via the test burn-in board 1 and is output from each semiconductor device in response to the test signal. The response signal is input to the driver / comparator circuit 6 via the test burn-in board 1.

The test signal is controlled by the basic control circuit 3, and the pattern generation circuit 4 and the bias power supply circuit 5 are supplied.
And is supplied to the driver / comparator circuit 6. The response signal is evaluated by comparing the expected value signal with the driver / comparator circuit 6, and the evaluation result is input to the controller 7.

Next, FIG. 2 is a circuit diagram of the test burn-in board 1. In this circuit diagram, reference symbols a11 to
amn is an IC socket, b1 to bm are open / close switches, and d1 to
dm, e1 to en and f are input / output terminals, and S is a clock selection supply circuit (clock selection supply means).

The IC sockets a11 to amn are arranged in a matrix of n rows × m columns on the test burn-in board 1, and a semiconductor device is mounted on each of them. These I
Of the C sockets a11 to amn, each column constitutes a test group, and the n IC sockets a11 to an in each column.
A test signal is simultaneously supplied to each of the semiconductor devices mounted on 1n, a21 to a2n, ... Am1 to amn to perform a test. That is, the test burn-in board 1 is configured of m test groups each including columns, and a test signal is sequentially supplied to each of these test groups in a predetermined order to perform a test.

Of the plurality of input / output terminals d1 to dm, e1 to en and f, the scan signals SCAN1 to SCANm from the driver / comparator circuit 6 are input to the input / output terminals d1 to dm, respectively. Input / output signals I / O 1 to I / O n are input from the IC sockets a11 to amn to e1 to en, respectively, and a clock signal CLK is input from the driver / comparator circuit 6 to the input / output terminal f. .

More specifically, the input / output terminals d1 to dm are
It is provided for each test group and supplies individual scan signals SCAN 1 to SCAN m to each test group. The scan signal SCAN 1 input to the input / output terminal d1 is supplied to the IC sockets a11 to a1n forming the test group (first test group) in the first column (the rightmost column), and the input / output terminal d1
The scan signal SCAN 2 input to 2 is the IC socket a that constitutes the second row test group (second test group).
The scan signals SCAN m supplied to the input terminals 21 to a2n, ... And the input to the input / output terminal dm are the IC sockets am1 to aa constituting the m-th column test group (m-th test group).
supplied to mn.

On the other hand, the input / output terminals e1 to en are individually provided for each row, and the input / output terminals e1 are the semiconductors mounted on the IC sockets a11, a21 ... Am1 of the first row (top row). Input / output signal I / O 1 is transmitted / received to / from the device, and the input / output terminal e 2 is connected to the IC sockets a 12 and a 2 of the second row.
2 …… I / O signal I / O 2 is sent / received to / from each semiconductor device mounted on am2, and also I / O terminal en
Transmits / receives an input / output signal I / O n to / from each semiconductor device mounted in the IC sockets a1n, a2n ... Amn on the n-th row.

The input / output terminal f is commonly connected to one ends of m open / close switches b1 to bm provided for each test section loop. The other end of each open / close switch b1 to bm is
As shown, they are individually connected to the IC sockets a11 to a1n, a21 to a2n, ... Am1 to amn of the corresponding test loops. The open / close switches b1 to bm have scan signals SCAN1 to SCAN m corresponding to their test group.
Is supplied as a switching signal.

That is, the open / close switch b1 has a scan signal SCAN 1 corresponding to the first test group as a switching signal.
, The scan signal SCAN 2 corresponding to the second test group is supplied to the open / close switch b2, ... And the scan signal SCAN m corresponding to the m-th test group is supplied to the open / close switch bm. Each open / close switch b1
.About.bm are mechanical switches having a relatively small input / output capacitance (electrostatic capacitance), for example.

Next, the operation of the test burn-in system thus constructed will be described.

In this test burn-in device, when the test groups are sequentially selected based on the scan signals SCAN 1 to SCAN m, this selection operation (that is, the scan signals SCAN 1 to SC
The opening / closing operation of each of the opening / closing switches b1 to bm is controlled in synchronization with (change of AN m) and the clock signal CLK is supplied only to the test group to be tested.

For example, if the scan signal SCAN 1
When the test group is set as the test target, the open / close switch b1 is set to the closed state in synchronization with this, and the other open / close switches b2 to bm are set to the open state. As a result, the clock signal CLK is supplied only to the first test group. Then, each time the test groups are sequentially switched based on the scan signals SCAN 1 to SCAN m, the clock signal CLK is sequentially switched and supplied only to the single test group selected as the test target in synchronization with this switching. .

According to the present embodiment, since the clock signal CLK is switched and supplied only to the test group to be tested, comparison is made when the clock signal CLK is supplied in parallel to all the test groups as in the conventional case. Then, since the additional capacitance of the signal line of the clock signal CLK is reduced, the frequency of the clock signal CLK can be increased and a high speed test can be realized. Even if a semiconductor device in a certain test group includes a defective device related to the clock signal CLK, the clock signal CLK is normally supplied to the other test groups other than the test group. Tests can be conducted on the test group without any problems.

In the present embodiment, the clock selection supply means is configured as the clock selection supply circuit S consisting of a plurality of open / close switches b1 to bm, but the configuration method of the clock selection supply means is not limited to this. .

[0032]

As described above, according to the present invention,
Since the clock signal is switched for each test group and supplied, the additional capacitance of the signal line of the clock signal can be reduced, and thus the clock signal can be increased in frequency to realize a high-speed test. Even if a semiconductor device in a certain test group includes a defective device related to the clock signal, the clock signal is normally supplied to the other test groups other than the test group. The test can be performed without the influence of the defective device.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a test burn-in device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a test burn-in board according to an embodiment of the present invention.

[Explanation of symbols]

1-Test burn-in board (test board) 2 ... Constant temperature bath 3 ... Basic control circuit 4 ... Pattern generation circuit 5 ... Bias power supply circuit 6 ... Driver / comparator circuit 7 ... Controller a11 ～ amn …… IC socket b1-bm …… Open / close switch d1 to dm, e1 to en, f ... I / O terminals S: Clock selection supply circuit (clock selection supply means)

Claims (9)

[Claims] 1. A semiconductor integrated circuit test apparatus for testing the operation of each semiconductor device by grouping a large number of semiconductor devices into a plurality of test groups and sequentially supplying a test signal to the semiconductor devices of each test group. IC sockets (a11 to a11) for mounting the semiconductor device.
mn) are mounted and the clock signals supplied from the outside are switched in synchronization with the group selection signal designating the test group, and each IC socket (a11 to amn) is switched.
1. A semiconductor integrated circuit test apparatus, comprising: a test board (1) provided with a clock selecting and supplying means (S) for supplying to. 2. The clock selection supply means (S) is a plurality of open / close switches (b1 to bm) provided in the middle of a clock signal supply wiring for each test group and using the group selection signal as a switching signal. The semiconductor integrated circuit testing device according to claim 1, wherein 3. The semiconductor integrated circuit test device according to claim 1, which is applied to a test burn-in device. 4. A semiconductor integrated circuit test apparatus for testing the operation of each semiconductor device by grouping a large number of semiconductor devices into a plurality of test groups and sequentially supplying a test signal to the semiconductor devices of each test group. And an IC for mounting the semiconductor device
A large number of sockets (a11 to amn) are mounted and each I
A test board (1) for supplying test signals in parallel to semiconductor devices mounted in C sockets (a11 to amn), and a group selection for specifying an externally supplied clock signal to the test group. Each IC can be switched in synchronization with the signal
A test board comprising a clock selection supply means (S) for supplying to the sockets (a11 to amn). 5. The clock selection supply means (S) is a plurality of open / close switches (b1 to bm) provided in the middle of the clock signal supply wiring for each test group and using the group selection signal as a switching signal. The test board according to claim 4, wherein: 6. The semiconductor integrated circuit testing device is a test burn-in device.
Test board as described. 7. A method for testing the operation of each semiconductor device by grouping a large number of semiconductor devices into a plurality of test groups, and sequentially supplying a test signal to the semiconductor devices of each test group. A semiconductor integrated circuit test method for performing an operation test of each semiconductor device by switching a clock signal supplied to a semiconductor device as one of the signals for each test group and supplying the clock signal. 8. An open / close switch (b1 to bm) is provided in the middle of a clock signal supply wiring for each test group, and the open / close switch (b1 to bm) is opened / closed based on a group selection signal designating a test group. 8. The semiconductor integrated circuit test method according to claim 7, wherein the clock signal is switched and supplied to each test group. 9. The semiconductor integrated circuit test method according to claim 7, which is applied to a test of a semiconductor device using a test burn-in apparatus.