JP2587928B2 - IC inspection equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an IC inspection for measuring an IC under test by selectively connecting a measurement circuit to a pin connection terminal to which each pin of the IC under test is connected. The present invention relates to an apparatus, and particularly to an improvement relating to control of connection between a pin connection terminal and a measurement circuit in such an IC inspection apparatus.

[Prior art] In general, an IC inspection apparatus is provided with a DC measurement circuit for applying a voltage to an IC pin and measuring a pin current, and a relay provided corresponding to a pin connection terminal is used.
The measurement is performed by selectively connecting a DC measurement circuit to the pin connection terminal.

In order to reduce the time for such measurement, many recent IC inspection apparatuses include a plurality of DC measurement circuits.

One IC inspection device has 4 pins for 128 pin connection terminals.
The DC measurement circuit is equipped, and the measurement can be performed by connecting the DC measurement circuit to four pin connection terminals at the same time.

To further explain this IC inspection apparatus, the first DC measurement circuit is No. 1, No. 5,..., No. 65, No. 69,.
No. 25, a total of 32 pin connection terminals and their corresponding relays, the second DC measurement circuit is No. 2, No. 6,
, No. 66, No. 70,..., No. 126 are connected via a corresponding relay to a total of 32 pin connection terminals. Similarly, the third DC measurement circuit is the third, seventh, ..., 66,
The No. 71, ..., 127 pin connection terminals are connected via the corresponding relays, and the fourth DC measurement circuit is No. 4, 8, ...
・ Connected to the 68th, 72nd,..., 128th pin connection terminals via the corresponding relays.

Further, four 32-bit shift registers are provided for controlling the relay corresponding to each of the pin connection terminals, and the output signal at each bit position of each shift register outputs the relay signal corresponding to the specific pin connection terminal. Are assigned as control signals.

This allocation relationship is fixed, and each bit position of the first shift register is sequentially allocated to 32 relays connected to the first DC measurement circuit, and each bit position of the second shift register is 2 bits. Each bit position of the third shift register is sequentially allocated to the 32 relays connected to the third DC measurement circuit, and the bit positions of the third shift register are sequentially allocated to the 32 relays connected to the third DC measurement circuit. Each bit position of the fourth shift register is sequentially assigned to 32 relays connected to the fourth DC measurement circuit.

In such a configuration, "1" is set to the first bit position of each shift register, and each shift register is simultaneously shifted by the same shift pulse. First, since the output signal of the first bit position of each shift register becomes "1", a DC measurement circuit is simultaneously connected to the first, second, third, and fourth pins, and measurement is simultaneously performed for the four pins. Done.
Since the output signal at the second bit position of each shift register becomes "1" at the timing of the next shift pulse, the fifth, sixth, and seventh shift registers are output.
The DC measurement circuit is connected to pins # 8 and # 8 at the same time.
A measurement is made on the pin. Similarly, since the output signal at the 32nd bit position of each shift register becomes “1” at the timing of the last shift pulse, the 125th, 126th, 127th, and 12th
Pin 8 is measured simultaneously.

As described above, the DC measurement can be performed for each of the four pins for the 128-pin IC, so that the measurement time can be reduced to almost one fourth as compared with the case where the DC measurement is performed for each of the one pins.

[Problems to be Solved] However, in the above-described conventional IC inspection apparatus, since the correspondence between each bit position of the shift register and the relay is fixed, there is the following problem.

For example, consider a case in which two 64-pin ICs are set in an IC inspection apparatus and an inspection is performed. In this case, the pins of the first IC are connected to the 1st to 64th pin connection terminals,
Are connected to the 65th to 128th pin connection terminals.

When the shift operation of the four shift registers is performed as described above, first, the first IC is connected to the four pins No. 1 to No. 4, respectively.
No DC measurement circuit is connected to the IC. At the timing of the next shift pulse, the measurement circuit is directly connected to the fifth to eighth pins of the first IC, but the DC measurement circuit is not connected to the pins of the second IC.

Similarly, only the measurement of the first IC is performed continuously, during which time the measurement of the second IC is not performed. The measurement of the second IC starts at the timing of the next shift pulse after the measurement of the pins 61 to 64 of the first IC.

As described above, the conventional IC inspection apparatus cannot measure two (or three or more) ICs at the same time.

Therefore, an object of the present invention is to solve such a problem and to provide an IC inspection apparatus capable of flexibly dealing with measurement of one IC and simultaneous measurement of two or more ICs.

[Means for Solving the Problems] A feature of the IC inspection apparatus of the present invention for achieving such an object is to have m (m is a positive integer) measuring circuits,
Measurement of the IC under test by connecting m measurement circuits to m selected terminals out of n (n is an integer n> m) pin connection terminals to which the pins of the IC under test are respectively connected In the IC inspection apparatus for performing the above, m out of n terminals are sequentially assigned to each measurement circuit, and every m−1 terminals are assigned to m terminals.
N switch circuits respectively provided corresponding to each terminal connected to one of the measurement circuits and turned on in response to a control signal, and m number n provided corresponding to the m measurement circuits / m (where n / m is an integer, if n / m is not an integer, the integer part of the integer plus an integer of 1), a bit shift register, a register for storing data indicating connection conditions between the terminal of the IC to be measured and the measurement circuit, Receives data stored in a register and bit data of m shift registers, and controls a switch circuit corresponding to a combination of connections selected according to connection conditions among connections between a terminal and a measurement circuit according to the data. A switching circuit for generating a signal and switching connection with each terminal to be connected to the measurement circuit in accordance with a change in the content of the bit data due to the shift of the bit data; And a shift control circuit for setting a bit in the shift register and shifting the bit, and by sequentially shifting the bit of the shift register, the measuring circuit and the terminal are sequentially connected in a predetermined order.

[Operation] By providing a switching circuit for generating a signal for selecting a connection state as described above on the premise of a connection state between n switch circuits and m measurement circuits, a plurality of measurement circuits can be completely connected to arbitrary terminals. Although there is not enough freedom to connect to the circuit, it is much more flexible than in the past, and a plurality of measurement circuits can be simultaneously connected to the desired terminal with sufficient freedom for IC measurement. In addition, the control can be sequentially performed by the bit shift of the shift register, and it is not necessary to largely change the conventional control.

That is, the IC inspection apparatus according to the present invention has a configuration in which the correspondence between each bit position of the shift register and the switch element is not fixed in advance, but can be switched by the corresponding switching circuit according to the control information.

Therefore, control information to be given to the corresponding switching circuit is set according to the number of ICs set in the device, and when there is only one IC, switching is performed so that all the measuring circuits are simultaneously connected and measurement is performed. When there are two or more ICs, the association can be switched so that the measurement circuit is connected to each of the ICs at the same time to perform the measurement.

As described above, according to the present invention, the measurement of one IC is
Simultaneous measurement of more than one IC is also possible, and the flexibility of measurement using a plurality of measurement circuits can be improved.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a main configuration of an embodiment of an IC inspection apparatus according to the present invention. In this figure, P1 ~
P128 is a pin connection terminal, and a total of 128 pins are provided. 1 ₁ to 1 ₄ is a DC measuring circuit. RL1~RL128 is relay as a switch element for connection control between the pin connection terminal P1~P128 the DC measuring circuit 1 ₁ to 1 _4, pin connection terminal
A total of 128 are provided corresponding to each of P1 to P128. C1 to C128 are contacts of the respective relays RL1 to RL128.

The first DC measuring circuit 1 ₁ is a total of 32 pin connection terminal P
1, P5, P9, P13,..., P61, P67, P71,. The second DC measurement circuit
1 ₂ is a total of 32 pin connection terminals P2, P6, P10, P14, ..., P6
2, P68, P72, P76,..., P128 are connected via corresponding relay contacts. Third DC measuring circuit 1 ₃ total of 32 pin connections terminals P3, P7, P11, P15, ···, P63, P65, P69, P73, ·
..Connected via P125 and corresponding relay contact. Further, the fourth DC measuring circuit 1 ₄ total of 32 pin connections terminals
, P64, P66, P70, P74,..., P126 are connected via corresponding relay contacts.

2 ₁ to 2 ₁₂₈ is an AND gate for driving the relay RL1～RL128, provided total of 128.

Reference numeral 3 denotes a pin register, in which a bit pattern for designating a pin connection terminal to be subjected to DC measurement is CP.
Loaded from U4. The output signal of each bit position of the pin register 3 is inputted to the AND gate 2 ₁ to 2 ₁₂₈ that corresponds. Of the AND gates 2 ₁ to 2 _128, pin register 3
From "0" which signal is input is suppressed, the connection between the pin connection terminal and its corresponding DC measuring circuit 1 ₁ to 1 ₄ are prohibited.

5 ₁ to 5 ₄ are 32-bit shift registers provided for connection control between the pin connection terminal and a DC measuring circuit. The output signal of each bit position of the shift registers via the corresponding switching circuit 6, the AND gate 2 ₁ to 2 ₁₂₈ thereto by a pin connection terminal associated, is input as a relay control signal. The association by the association switching circuit 6 is switched according to control information given from the CPU 4 via the register 7. This control information
When one IC to be tested has 128 pins, the code data corresponds to the IC. When one IC has 64 pins, the code data corresponding thereto corresponds to the code data.
When two ICs are sequentially arranged to have 128 pins, the corresponding code data is obtained.

8 is a shift control circuit for controlling the shift register 5 ₁ to 5 _4, and a shift pulse CLK to be supplied to the common to the shift register 5 ₁ to 5 _4, to generate a data signal D.

Next, the operation when two 64-pin ICs are measured simultaneously will be described. The pin of the first IC is connected to the 1st to 64th pin connection terminals P1 to P64, and the pin of the second IC is 6
Connected to the 5th to 128th pin connection terminals.

In this case, the control information corresponding to the two simultaneous measurements is loaded from the CPU 4 into the register 7. Further, a bit pattern for specifying a pin to be measured is loaded into the pin register 3. However, for simplicity,
It is assumed that a bit pattern in which all bits are “1” is loaded.

The association by the association switching circuit 6 in this case is as follows.

For the first shift register 5 _1, the first bit position pin connection terminal No. 1, the pin connection terminal of the second bit position is 67th, the pin connection terminal of the third bit position # 5, the It is sequentially associated with the 71st pin connection terminal, and the 31st bit position is assigned to the 61st pin connection terminal.
The 32-bit position is associated with the 127th pin connection terminal.

For the second shift register 5 _2, in the first bit position 2 pin connection terminals of the pin connection terminal of the second bit position # 68, the pin connection terminal of the third bit position # 6, the The 4 bit position is sequentially associated with the 72nd pin connection terminal, and the 31st bit position is associated with the 62nd pin connection terminal, and the 32nd bit position is associated with the 128th pin connection terminal.

The third shift register 5 _3, the pin connection terminal of the first bit position 65th, the pin connection terminal of the second bit position is third, the pin connection terminal of the third bit position # 69, the The 4-bit position is sequentially associated with the 7th pin connection terminal, the 31st bit position is associated with the 125th pin connection terminal, and the 32nd bit position is associated with the 63rd pin connection terminal.

The fourth shift register 5 _4, the pin connection terminal of the first bit position number 66, the pin connection terminal of the second bit position number 4, the pin connection terminal of the third bit position No. 70, 4 The bit position is sequentially associated with the eighth pin connection terminal, and so on. The 31st bit position is associated with the 126th pin connection terminal P126, and the 32nd bit position is associated with the 64th pin connection terminal P64. .

When activated by the CPU 4, the shift control circuit 8 first generates a "1" signal as the data signal D and sends out the first shift pulse. After the first shift pulse is generated, the data signal D is reset to "0".

Because only the output signal of the first bit position of each shift register 5 ₁ to 5 ₄ becomes "1", the relay RL1, RL2, RL65, RL66 is excited, because the contact is closed, the direct current measuring circuit 1 ₁ 1
The pin connection terminal P1 turn, the DC measuring circuit 1 ₂ in the pin connection terminal P2 of the No. 2, the pin connection terminal P65 of the DC circuit 1 ₃ 65 No.,
The DC measurement circuit 1 ₄ are connected to the pin connection terminal P66 of number 66.

That is, the first 1st and DC measuring circuit 1 ₁ to pin No. 2 of the IC, 1 ₂ is carried out the measurement are connected respectively, at the same time the second 1st and DC measuring circuit to the pin number 2 of IC 1 _3, 1 ₄ is measured respectively connected are performed.

When the measurement is completed, the next shift pulse CLK is sent from the shift control circuit 8, only the output signal of the second bit position of each shift register 5 ₁ to 5 ₄ becomes "1". Relay RL
3, RL4, RL67, RL68 is closed respective contacts are energized, the DC measuring circuit 1 _1, 1 ₂ are connected respectively to the pin connection terminal 67 th and 68 th, the DC measuring circuit 1 _3, 1 ₄ Are connected to the third and fourth pin connection terminals, respectively. That is, the measurement is performed simultaneously on the third and fourth pins of the first IC and the second IC.

Similarly, when the 63rd shift clock is generated, the DC measurement circuits 11 ₁ and 1 are connected to pins 61 and 62 of the first IC.
₂ are respectively connected, a second current measuring circuit to pin 2 of the same number of IC 1 _3, 1 ₄ are connected respectively, are measured simultaneously performed. When the 64th shift clock occurs,
The first 63 No. IC and DC measuring circuit 1 ₃ the pin number 64, 1 ₄ are connected respectively. The second DC measurement circuit to pin 2 of the same number of IC 1 _1, 1 ₂ are connected respectively, is performed simultaneously measured.

In this way, the DC measurement circuit is simultaneously connected to the two pins of the same number of the two ICs, and the measurement is performed.

FIG. 2 is a table showing the temporal transition of each DC measurement circuit and the number of a pin connection terminal connected thereto. In this figure, the horizontal direction corresponds to the timing of the shift clock, and the numbers arranged in one vertical column are the numbers of the pin connection terminals to which the DC measurement circuit is simultaneously connected at the corresponding shift timing.

Next, the operation in the case where one 128-pin IC is set and measurement is performed will be described.

In this case, since the control information corresponding to one measurement is loaded into the register 7, the correspondence switching circuit 6 switches the correspondence between the bit position of the shift register and the pin connection terminal as follows. The correspondence switching circuit 6 is simply a shift register 5 _1, 5 _2, 5 _3, 5 ₄ side data necessary for connection in response to the input data from and the register 7 side sequentially generates its Since it is only necessary to send the data to the AND gates 2 ₁ , 2 ₂ ,..., 2 ₁₂₈ , the conversion of the data in the connection state is performed by the shift register in the gate array or the ROM or RAM memory as shown in the following example. Any circuit can be configured as long as it is possible according to the contents of the data.

That is, the shift register 5 _1, the first bit position is 1
The 2nd bit position corresponds to the 5th pin connection terminal, the 3rd bit position corresponds to the 9th pin connection terminal, the 4th bit position corresponds to the 13th pin connection terminal, and so on. The 32nd bit position is associated with the 125th pin connection terminal. The second shift register 5 _2, in the first bit position 2 pin connection terminals of the pin connection terminal of the second bit position 6th, the pin connection terminal of the third bit position number 10, fourth The bit position is sequentially associated with the 14th pin connection terminal, and so on, and the 32nd bit position is associated with the 126th pin connection terminal. Third shift register
5 ₃ indicates that the first bit position is
The bit position is the 7th pin connection terminal, the 3rd bit position is
The fourth bit position is sequentially associated with the 11th pin connection terminal, such as the 15th pin connection terminal, and the 32nd bit position is associated with the 127th pin connection terminal. Similarly 4
Th shift register 5 ₄ the pin connection terminal of the first bit position # 4, the pin connection terminal of the second bit position number 8, the pin connection terminal of the third bit position number 12, the fourth bit The position is sequentially associated with the 16th pin connection terminal, and so on, and the 32nd bit position is associated with the 128th pin connection terminal.

The operation of the shift register 8 is the same as in the case of simultaneous measurement of two shift registers.

Since the association is as described above, the set pins of the IC are simultaneously measured in order of four pins in numerical order. In other words, the measurement operation in this case is the same as that of the conventional device.

In either case of one-measurement or two-measurement, a bit pattern in which the bit corresponding to the pin to be measured is “1” and the bit corresponding to the pin not to be measured is “0” is loaded into the pin register 3. By doing so, it is possible to control the measurement execution of individual pins. Since this bit pattern can be dynamically changed by the CPU 4, such control of measurement execution of each individual pin can be dynamically performed.

Further, by separating the shift pulses applied to the four shift registers and operating the shift registers one by one in order, it is also possible to measure one pin at a time.

As mentioned above, although one Example was described in detail, this invention is not limited only to it.

For example, the above-described embodiment has a configuration capable of supporting one measurement and two simultaneous measurements of an IC. However, as will be apparent from the above description, a modification may be made so as to support three or more simultaneous measurements. it can.

Further, the measuring circuit in the above embodiment is a DC measuring circuit, but may be another measuring circuit.

Furthermore, in the above embodiment, a relay is used as a switch element for selective connection between the pin connection terminal and the DC measurement circuit. However, if various conditions such as DC resistance allow, a semiconductor switch element or the like is used. You may.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[Effects of the Invention] As is clear from the above description, the present invention has a plurality of measurement circuits, and the measurement circuits are connected to one or more pin connection terminals to which pins of the IC under test are connected. In an IC inspection apparatus for selectively connecting and measuring an IC under test, a switch element provided for each of the pin connection terminals for selective connection between the measurement circuit and the pin connection terminal, A shift register provided for controlling the switch element, and a corresponding switching circuit for switching a correspondence between each bit position of the shift register and each switch element according to control information; Since the control is performed according to the output signal of a specific bit position of the shift register associated with the corresponding switching circuit, the control is performed according to the number of ICMs set in the device. The control information to be given to the corresponding switching circuit is set in the same way, and when there is one IC, switching is performed so that all the measuring circuits are simultaneously connected to perform the measurement, and two or three or more ICs are connected. In such a case, it is possible to switch the correspondence so that the measurement circuit is connected to each of the ICs at the same time to perform the measurement, thereby improving the flexibility of the measurement using the plurality of measurement circuits. Have.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of an embodiment of an IC inspection apparatus according to the present invention. FIG. 2 is a diagram showing a DC measurement circuit for measuring two ICs simultaneously and the number of a pin connection terminal connected thereto. FIG. 9 is a table showing a time transition of the above. 1 ₁ to 1 ₄ ... DC measurement circuit, 2 ₁ to 2 ₁₂₈ ... AND gate,
3 ... pin register, 4 ... CPU, 5 _{1 to} 5 ₄ ... shift register, 6 ... corresponding switching circuit, 7 ... register, 8
…… Shift control circuit, P1 to P128 …… Pin connection terminal, RL1
~ R128 ... Relay, C1 ~ C128 ... Relay contacts.

Claims (1)

(57) [Claims] 1. It has m (m is a positive integer) measuring circuits,
Connecting the m measuring circuits to m selected terminals out of n (n is an integer n> m) pin connection terminals to which the pins of the IC to be connected are connected, respectively; In the IC inspection apparatus for performing the measurement of the above, m out of the n terminals are sequentially assigned to the respective measurement circuits, and every m−1 terminals are connected to one of the m measurement circuits. N switch circuits provided corresponding to the terminals and turned on in response to a control signal; and m n / m provided corresponding to the m measurement circuits (where n / m is an integer) If not, an integer part of the integer + 1) a bit shift register; a register for storing data indicating a connection condition between a terminal of the IC to be measured and the measurement circuit; and the data stored in the register. And the m shift registers Receives the bit data, it generates the control signal to the switch circuit corresponding to the combination of connections to be selected in accordance with the connection conditions of the connection between the terminal and the measuring circuit in accordance with these data, and,
A switching circuit for switching a connection between the measurement circuit and each terminal to be connected in accordance with a change in the content of the bit data due to the shift of the bit data; and setting a bit in the shift register and shifting the bit. An IC inspection device, comprising: a shift control circuit, wherein the measuring circuit and the terminal are sequentially connected in a predetermined order by sequentially shifting bits of the shift register.