JP2000111620A - Ic tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten processing time regardless of an output data form of a measuring object device, and to reduce storage capacity of data. SOLUTION: An IC tester has a switching unit 3 for switching an input passage of serial data and parallel data, a serial-parallel converter 5 for converting the serial data into the parallel data and a data converter 7 for rearranging the serial data in weight order of a bit, and when digital output from a DUT(device under test) 1 is a serial form, an address in the data converter 7 is designated by the parallel data from the serial-parallel converter 5 so that the parallel data of the address is written in a prescribe address of 1 in a storage device 9. Thus, there is no need to perform arithmetic processing for rearranging data one bit by one bit for converting the serial data into the parallel data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring an integrated circuit in which an analog circuit and a digital circuit are mixed.
It relates to a C tester.

[0002]

2. Description of the Related Art A digital output of an integrated circuit in which an analog circuit and a digital circuit coexist is "0",
There are many things that have meaning as numerical values as well as “1” logic. For example, such as a digital output of an A / D converter. An example of an integrated circuit in which such digital output has a numerical value is A /
When measuring a D converter, it is necessary to apply an analog voltage, take in the conversion result of the A / D converter at that time, and calculate an error from an ideal output.

FIG. 3 shows a configuration of a conventional IC tester for measuring such an integrated circuit. In FIG. 3, reference numeral 20 denotes a DUT (Device Under) measured by an IC tester.
Test: Generic term for measurement objects. The same applies to the following), 21
Is a comparator that determines the logic of output data from the DUT 20, 22 is a register that temporarily stores data, 23 is a storage device, 24 is a control processing device that controls the storage device 23, and 25 is a device that calculates measured data. Arithmetic processor, 26
Is a digital measurement system that generates a pattern for operating the DUT 20 and compares the pattern with an expected pattern of the output from the DUT 20.

In such a configuration, the DUT 20 is measured as various integrated circuits. When measuring the A / D converter as described above, the conversion result is stored in the storage device 23.
And an arithmetic processor 25 calculates an error from the ideal output. At this time, if the digital output of the numerical A / D converter is serial data, as shown in FIG. 4, each bit of the serial data is changed from LSB (least significant bit) to MSB (most significant bit). Up to the upper bit) are sequentially taken into the storage area of the storage device 23 at the predetermined address. Then, the arithmetic processor 25 converts the serially stored data into parallel data that can be handled by the arithmetic processor 25, and performs arithmetic processing on the converted parallel data.

[0005]

As described above, when the output data format from the device under test is serial, the conventional IC tester converts the data into parallel data that can be handled by the arithmetic processor 25. In the conversion process, there is a problem that it takes a lot of time to perform a process of rearranging each serial data stored in the storage device 23. The serial data is stored in the storage device 23.
Are stored bit by bit in the address direction at
When a plurality of data are acquired, there is a problem that a large storage capacity is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an IC tester capable of shortening the processing time and reducing the data storage capacity regardless of the output data format of the device under test.

[0007]

According to the first aspect of the present invention,
Data format conversion means for converting serial format data output from the device under test to parallel format data, and parallel numeric data corresponding to the serial format data, the serial format data A data converter that stores in advance at an address designated by parallel format data to be converted, and outputs parallel numerical data stored at the address when the conversion result by the data format conversion means is the parallel format data. Means.

[0008] The invention according to claim 2 is the invention according to claim 1.
In the C tester, a signal path for transmitting parallel data output from the device under test and data output from the device under test are input to the data format conversion means when the output format is serial, In the case of the parallel mode, an input path switching means for inputting to the signal path is further provided.

According to the third aspect of the present invention, there is provided the method according to the second aspect.
The C tester further includes a coupling unit that couples an output path of the data format conversion unit and an output path of the signal path, wherein the data conversion unit includes: The parallel numerical data indicated by the parallel-format data is stored in advance at an address designated by the parallel-format data, and when the output from the combining means is the parallel-format data, the parallel numerical data stored at the address is stored. It is characterized by outputting numerical data.

According to a fourth aspect of the present invention, there is provided the IC tester according to any one of the first to third aspects, further comprising storage means for storing parallel numerical data output from the data conversion means. And

According to a fifth aspect of the present invention, there is provided the method according to the fourth aspect, wherein
The C tester outputs to the data format conversion means a capture instruction signal for sequentially capturing serial format data output from the device under test, and outputs an output end signal for one word of the serial format data. It further comprises a data fetch instruction means for outputting to the storage means, wherein the storage means stores the parallel numerical data when receiving the output end signal.

As described above, according to the present invention, when the output format of the device under test is serial, the data format conversion means dedicated to the conversion processing and the data conversion means are added before the storage means, so that the storage means Storage capacity can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of an IC tester according to one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a DUT (device under test) to be measured by the present IC tester. 2
Is a comparator for determining the logic ("0" to "1") of the output data from the DUT1. Reference numeral 3 denotes a switch for switching the processing path of the output from the comparator 2 to the terminal a side or the terminal b side in the figure according to the output data format of the DUT 1. Here, the terminal a is composed of a plurality of terminal groups for transmitting parallel data, the terminal b is composed of a single terminal for transmitting serial data, and the terminals corresponding to these terminals are the DUT 1 and the comparator 2. And the corresponding terminals are connected in the switch 3.

Reference numeral 4 denotes a register connected to the terminal a of the switch 3, and temporarily stores parallel data received via the comparator 2 and the switch 3 when the output data format of the DUT 1 is parallel. 5 is a serial-parallel converter for converting serial data into parallel data,
It is connected to the terminal b of the switch 3. Reference numeral 6 denotes a logic element connecting the output path of the register 4 and the output path of the serial-parallel converter 5. Since the data from the register 4 and the data from the serial-parallel converter 5 are both in a parallel format, the logic element 6 serves to connect the parallel-type signal transmission paths (to form one parallel signal transmission path). Carry.

Reference numeral 7 denotes a data converter for converting data output from the logic element 6. This data converter 7 is
M, predetermined data is stored in advance at a predetermined address, and programmed to operate in accordance with the data received from the logic element 6 (the details of this program and the like will be described later). Reference numeral 8 denotes a control processor for controlling the switching operation of the terminals a and b of the switch 3 and controlling the data conversion in the data converter 7 (the program). Reference numeral 9 denotes a storage device that stores data converted by the data converter 7 under the control of the control processing device 8.

Reference numeral 10 denotes an arithmetic processor that performs arithmetic processing on data stored in the storage device 9. Numeral 11 generates a pattern signal for operating the DUT 1 and a DU.
This is a digital measurement system that compares the output from T1 with the expected pattern. This digital measurement system 11 uses a DUT
1, a register 4, a serial-parallel converter 5, and a storage device 9, which supply the generated pattern signal to the DUT 1, and a DUT 1 for the register 4 and the serial-parallel converter 5. An instruction signal for instructing to take in the output is output, and an instruction signal for instructing the storage device 9 to store the data converted by the data converter 7 is output.

Next, the operation of the above configuration will be described. First, switching of the switch 3 and programming of the data converter 7 are performed according to the DUT 1 to be measured.

When the DUT 1 is specified, it is known in advance whether the output data format from the DUT 1 is serial data or parallel data. Therefore, before the measurement of the DUT 1 is started, the DUT 1
1, switching information for forming a processing path suitable for the output data format. That is, the control processing device 8
When the output data format of the DUT 1 is parallel, information indicating that the output from the comparator 2 is connected to the terminal a, and when the output data format is serial, the information is provided to indicate that the output is connected to the terminal b. Thus, the switch 3 is switched according to the output data format of the DUT 1.

The control processor 8 transfers data to the data converter 7 according to the digital output from the DUT 1 and programs the data structure in the data converter 7. That is, the control processing device 8 associates each digital output of the DUT 1 with each address in the data converter 7, and converts each digital output to each address in the order of bit weight in parallel data (meaning as a numerical value). Is stored.) Then, the conversion operation of the data converter 7 is programmed so that the parallel data stored at the address specified by the parallel data from the logic element 6 is written to one predetermined address in the storage device 9.

After the switching of the switch 3 and the programming of the data converter 7 are performed in this way, the measurement of the DUT 1 is started. When measuring the DUT1, a power supply voltage, a digital pattern signal, and the like for operating the DUT1 are supplied from the digital measurement system 11, and the DUT1 operates according to the supplied pattern signal.

Then, the output of the DUT 1 is determined to be “1” or “0” by the comparator 2,
1 digital output is input. Thereby, when the connection in the switch 3 is on the terminal a side, the parallel data is output to the register 4, and when the connection in the switch 3 is on the terminal b side, the serial data is output to the serial-parallel converter 5. You.

Now, assuming that the output data format of the DUT 1 is serial, and serial data in a word unit consisting of a plurality of continuous bits having a meaning as a numerical value is output from the DUT 1, the switching unit 3 outputs a signal to the terminal b. The connection is made, and the digital output of the DUT 1 is sequentially output to the serial-parallel converter 5.

In this case, the digital measurement system 11
An instruction signal for capturing the digital output of T1 is sequentially generated at the bit interval of the serial data,
Output to the parallel converter 5. As a result, the serial-parallel converter 5 operates in synchronization with the instruction signal, and sequentially takes in the digital output of the DUT 1.

When one word of serial data has been output from the DUT 1, the digital measurement system 11 outputs an instruction signal to the storage device 9 to instruct storage.
At this time, the output of the serial-parallel converter 5 is DUT1
Is converted from parallel data of one word into parallel data. The parallel data is input to the data converter 7 via the logic element 6 and becomes an address input of the data converter 7. That is, an address in the data converter 7 is designated by the parallel data, and parallel data (numerical data) programmed in advance at the address is output to the storage device 9. As a result, the parallel data is written to one predetermined address in the storage device 9.

For example, when the serial data shown on the left side in FIG. 2 is input to the serial-parallel converter 5, if the address indicated by the parallel data converted from the serial data corresponds to "15h", “15
h "is an address input to the data converter 7. Then, for the address" 15h "of the data converter 7,
One predetermined address (“2a
h)), and the parallel data stored at the address “15h” of the data converter 7 is stored at the address “2ah” of the storage device 9. In this manner, the storage device 9 includes an arithmetic processor 10
The parallel numerical data which can be directly handled by the memory device is stored.
It is written to the address as parallel data.

When the digital output from the DUT 1 is in a serial format, according to the present IC tester, the storage capacity of the storage device 9 can be reduced by changing the method of the serial-parallel conversion processing as described above.

When the output data format of the DUT 1 is parallel, the connection to the terminal a is made by the switch 3 and the same processing as described above is performed by the parallel data output via the register 4. That is, the data converter 7 previously stores the parallel data (numerical data) at an address indicated by the parallel data output from the DUT 1. Then, the parallel data stored at the address in the data converter 7 specified by the parallel data from the register 4 is stored at a predetermined address in the storage device 9.

[0029]

As described above, according to the present invention, the parallel numerical data corresponding to the serial data output from the device under test is stored in advance at a predetermined address of the data conversion means and output. Since the parallel numerical data is output when the result of converting the serial format data specifies the address, if the output format of the device under test is the serial format, the serial data is stored in the storage device. 1 after storing in
Parallel numerical data indicated by the serial data can be obtained without the need to perform a process of rearranging individual data. This makes it possible to shorten the processing time when the output format of the device under test is a serial format.

According to the second aspect of the invention, when the output of the device under test is serial, the same processing is performed as described above, and when the output of the device under test is parallel, the output is transmitted through a signal path for a parallel format. Therefore, both serial and parallel output formats can be handled. According to the third aspect of the present invention, the serial and parallel output paths are combined to obtain parallel numerical data even when the output format of the device under test is the parallel format. And for both output formats, parallel
This can be dealt with by a similar circuit configuration with a simple circuit configuration. Thus, the processing time can be reduced regardless of the output data format of the device under test.

According to the fourth aspect of the invention, the obtained parallel numerical data is stored in the storage means, so that the output of the device under test is stored in the storage means regardless of whether the output is serial or parallel. Can be stored as parallel numerical data. This avoids a situation in which each bit of the serial data must be stored at a different address, and has the effect of reducing the data storage capacity. Further, it is not necessary to rearrange the data when performing the arithmetic processing or the like of the stored data, and the processing time can be shortened as described above.

According to the fifth aspect of the present invention, serial format data output from the device under test is sequentially fetched, and parallel numerical data is stored when output of one word of the serial format data is completed. Therefore, serial data in a word unit consisting of a plurality of continuous bits having a meaning as a numerical value can be accurately obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an IC tester according to an embodiment of the present invention.

FIG. 2 is a diagram showing a serial-parallel conversion method in the IC tester of FIG. 1;

FIG. 3 is a diagram showing a configuration of a conventional IC tester.

FIG. 4 is a diagram showing a serial-parallel conversion method in the IC tester of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 DUT 2 Comparator 3 Switcher 4 Register 5 Serial-parallel converter 6 Logic element 7 Data converter 8 Control processing unit 9 Storage device

Claims (5)

[Claims] 1. A data format conversion means for converting serial data output from a device under test into parallel data, and parallel numerical data corresponding to the serial data is converted by the data format conversion means. Parallel numeric data stored in advance at an address specified by the parallel format data to which the serial format data is converted, and stored at the address when the conversion result by the data format conversion means is the parallel format data An IC tester comprising: a data conversion unit that outputs the data. 2. The IC tester according to claim 1, wherein a signal path for transmitting parallel data output from the device under test, and data output from the device under test, wherein the output format is serial. And an input path switching means for inputting the data to the data format conversion means and inputting the data path to the signal path in the case of parallel. 3. The IC tester according to claim 2, further comprising a coupling unit that couples an output path of the data format conversion unit and an output path of the signal path, wherein the data conversion unit includes When the output format is a parallel format, parallel numerical data indicated by the parallel format data is stored in advance at an address designated by the parallel format data, and the output from the combining means is the parallel format data. And outputting parallel numerical data stored at the address when the error occurs. 4. The IC according to claim 1,
The tester, further comprising a storage unit for storing the parallel numerical data output from the data conversion unit.
C tester. 5. The IC tester according to claim 4, further comprising: outputting a fetch instruction signal for sequentially fetching serial data output from the device under test to said data format conversion means, and outputting the serial format data. Further comprising data capture instruction means for outputting an output end signal for one word of data to the storage means, wherein the storage means stores the parallel numerical data when the output end signal is received. An IC tester comprising: