JP2953633B2 - Test vector generator for logic IC testing machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test vector generator (test pattern generator) used for a logic integrated circuit (hereinafter referred to as "logic IC" or "IC") tester, and more particularly to a scan method (serial as input / output data). Data is used) and an economical configuration of a test vector generator of a test machine for a logic IC using the same.

[0002]

2. Description of the Related Art FIG. 4 shows an example of an IC under test 100 to which a test vector generator of this kind is applied. In this example, combinational logic circuits (hereinafter, referred to as combinational circuits or circuits) 1, 2, and 3 are accommodated in one IC package. Shift registers 4 and 5 are provided on the input side and the output side of the combinational circuit 1, respectively. Similarly, shift registers 6, 7 or 8, 9 are provided on the input side and output side of the combination circuits 2, 3, respectively. Parallel input terminal groups IA, IB, and IC are connected to input-side shift registers 4, 6, and 8, and parallel output terminal groups 0A, 0B, and 0C are connected to output-side shift registers 5, 7, and 9, respectively. On the other hand, input / output terminals P for scanning (that is, for serial data) corresponding to the combinational circuits 1, 2, 3
_k , P _m , and P _n are provided.
Shift registers 4, 5;
7; connected to 8, 9 serial data input or output terminals. Scan control terminals P ₁ , P ₂ , and P ₃ are provided in common for each combination circuit, and shift registers 4 to 9 are provided.
Connected to.

In a logic IC tester 200, as shown in FIG. 5, output terminals p ₁ and p _{1 of} a test vector generator 300 are
p ₂ ..., p _N are shaping, compared, via the driver circuit 400, input and output terminal P ₁ of the test IC 100, P ₂ ..., P
Connected to _N respectively. Shaping, comparison, driver circuit 4
00 includes a waveform shaping circuit, a logical comparison circuit, a voltage comparison circuit, a driver circuit, and the like, but does not directly relate to the present invention, and a detailed description thereof will be omitted. The test vector generator 300 outputs data of a logic level of H or L (referred to as a test vector) corresponding to logic "1" or "0".

FIG. 7 shows a block diagram of a conventional test vector generator 300. As shown in FIG. FIG. 6 shows an example of a test vector. Binary data is output with the passage of time corresponding to these pin numbers in the horizontal direction, taking pin numbers 1, 2,..., N in the horizontal direction. is there. Test period TA of combinational circuit 1 after initialization period (preparation period) TOA
Then, similarly, TOB, TB; TOC, TC periods are sequentially provided.

The pins p ₁ and p ₁ of the test vector generator 300
₂ and p ₃ correspond to the scanning control terminals P ₁ , P ₂ and P ₃ of the IC under test 100 in FIG.
Pin p _k of, p _m, p _n correspond respectively scan data terminal P _k of the IC, P _m, to P _n. In the test period TA of the combination circuit 1, pin p _1, p _2, p each 8 bits to the _third scan control data is output. The pin _pk has 8-bit scan data, and the pin p _k
Data of logic 0 is continuously output to _m and _pn for 8 bits. P between p ₃ and _pk and after P _n
Pin between the parallel data pin, and p _k and p _m to _N,
to p _m and (say pin parallel data, etc. below) pins between the p _n, as there is no adverse effect on the test by scan data, predetermined data at logic 1 or 0 to 8 consecutive bits are output You.

[0006] In testing period TB of the combination circuit 2, 8-bit serial data to the scan data terminal p _m is the scan data terminal p _k, and 8-bit continuous p _n data logical 0 is output. The data of the other terminals are the same as in the case of the combinational circuit 1. In testing period TC of the combination circuit 3, data is output 6 bits to each terminal, and the scan data terminal p _n to the 6-bit serial data is output, the terminal p _n, logic and 6 bits continuously p _m 0 data is output. The other pin data is the same as above.

Although the number of bits of serial data in the test period of each combinational circuit is 8 or 6, it is generally data having a large number of bits, for example, 256 bits. In addition, the number of scan control terminals and the number of scan data terminals are each set to 3, but generally the total number of these terminals is a large value, for example, 16, 32, 64. Scanning control terminal p _1, p _2, p ₃ and scan data terminal p _k, p _m, the test period applied to p _n TA, TB,
The data DA, DB, DC... In TC... Are written to the scan vector memory 21 as shown in FIG. The column number of the scan vector memory 21 is the channel number 22
It is said. When the number of bits in the vertical direction (address direction) is large, it can reach several megabits.

Data other than the scan data DA, DB, DC... Written in the scan vector memory 21 is shown in FIG.
The data is written to the test vector memory 24 as shown in FIG. That is, the data in the test vector memory 24 is the data to be applied to the terminals for parallel data and the like in the test periods TA, TB, TC... In the initialization periods TOA, TOB, TOC. Does not change). The test periods TA, TB, TC ...
Since the scan control terminal p _1, p _2, p ₃ and scan data terminal p _k, is p _m, the data given to p _n are stored in the scan data memory 21 in these terminals p _1, p _{2 , p 3, p k, p} m, all cells 0 test vector memory 24 corresponding to the p _n is written.

In the test vector memory 24, the data in the test periods TA, TB, TC,... Of each circuit are stored in the memory cells of one row. Means that these data are
It is necessary to repeatedly output 8 bits for A and TB and 6 bits for TC, and this is performed under the control of the sequence control circuit 25. That is, in FIG.
The addresses of the rows to be simultaneously output from the test vector memory 24 are sequentially input from the address register 26. The address register 26 is controlled by the sequence control circuit 25.

The test data DA (FIG. 8D) of the scan data memory 21 must be output during the test period TA (for eight time slots) of the circuit 1, and an address signal is supplied from the address counter 28. The increment input terminal INC of the address counter 28 is supplied with an increment signal that becomes logic 1 during the test period TA from the control data memory 30. During that time, the address counter 28 counts the clock CLK, and stores the count value in the scan vector memory 21. To the address input terminal. An initial value is set in the address counter 28 by the sequence control circuit 25 as needed.

An address signal is supplied from an address register 26 to an address input terminal of the control data memory 30. As shown in FIG. 8C, the enable data 31 and the increment data 32 are written in the control data memory 30. That is, the initialization periods TOA, TOB, TO
Addresses B _{1 to} B ₄ , B _{6 to} B ₉ , B ₁₁ to B corresponding to C
Data B ₁₄ at 0,0, but also the test period TA, TB,
At addresses B ₅ , B ₁₀ , and B ₁₅ corresponding to TC, respectively, data of 1,1 is written. The enable data 31 and the increment data 32 which become 1 continuously during the test period from the control data memory 30 are output from the enable terminal E and the increment terminal INC, respectively, and one input terminal of the AND gate 34 and the increment terminal INC of the address counter 28 are output. Supplied to

Output data (scan control data and scan data) of the scan vector memory 21 are output from output terminals SD _{1 to} SDq and applied to the other input terminal of the AND gate 34. The output of the AND gate 34 is provided to the input terminals I _{1 to} I _q of the multiplexer 36. Output terminal O ₁ ~ O _N multiplexer 36 is provided to one input terminal of the N gate 38, to their other input terminal, an output terminal VD ₁ to VD _N data each test vector memory 24 Is entered. The output of the OR gate 38 is given to output terminals p _{1 to PN} of the test vector generator 300, respectively.

The switching of the multiplexer 36 is controlled by data in a multiplexer control register 40. The number (equal to the channel number of the scan vector memory 21) of one input terminal (any one of I _{1 to} I _q ) to be connected to the output terminal O _i (i = 1 to N) of the multiplexer 36 is shown in FIG. As described above, the data is previously written in the memory cell r _i (i = 1 to N) of the multiplexer control register 40. Input terminals I _{1 to} I _q are connected to multiplexer output terminal O _i.
If none of the not connected, that is, when not using the data in the scan vector memory data 0 is written in the memory cell r _i. In FIG. 9, the multiplexer 36
Are connected between O ₁ -I ₁ , O ₂ -I ₂ , O ₃ -I ₃ , O ₄ , O ₅ ... O _k-1 are not connected to any of the input terminals, and O _k -I ₄ , data for connecting between _{O m -I 5, O n -I} 6 are shown. Multiplexer 36
Are controlled by the multiplexer control register 40.

[0014]

In the conventional apparatus, for example, in the case of FIG.
Test data of the combinational circuits 1, 2, and 3 are stored in 6ch, respectively. However, a closer look, the test data for the circuit 1 4ch is written to the cell at the address a ₁ ~a _8, data of a ₉ subsequent cells are all 0.
The test data for the circuit 2 of 5ch address a ₉ ~
written in the cells of a _16, are all other cells is zero. The test data for a circuit 3 of 6ch is written in the cell at the address a ₁₇ ~a _22, the other cells are 0.

[0015] Of the memory capacities of 4 to 6 channels, only about one third is used effectively.
In an actual device, the number of test data storage channels is several to several tens.
In the case where the number is large and the length in the address direction is as long as several megabits, the useless memory area becomes extremely large. An object of the present invention is to solve such a conventional drawback and to make the apparatus economical.

[0016]

The present invention comprises a test vector memory, a control data memory, a scan vector memory, a multiplexer, and a multiplexer control memory.
This is a test vector generator for the C test machine. The test vector memory has N terminals respectively corresponding to the terminals of the IC under test.
The data of the initialization period is stored in a plurality of rows of cells, and the data of the test period is stored in one row of cells for each combinational circuit accommodated in the IC. .

The scan vector memory has N ₁ channels corresponding to the scan control terminals of the IC, and N ₂ channels common to each of the circuits (each having N ₂ scan data terminals). Scan data of the respective circuits during the test period are sequentially stored. The multiplexer has N output terminals respectively corresponding to the respective terminals of the IC, and receives an output of each of the channels of the scan vector memory during the test period, and outputs one of the N output terminals. Crab output.

The multiplexer control memory has a plurality of addresses corresponding to the respective circuits, and stores a channel number of the scan vector memory to be output to each output terminal of the multiplexer for each of the addresses. The multiplexer is controlled by data. The control data memory stores address data to be supplied to the multiplexer control memory.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. According to the present invention, the channel for storing test data of each circuit in the scan vector memory 21 is, for example, only 4ch, and as shown in FIG. 2B, the channel storing 0 conventionally is abolished. As a result, the channel capacity q of the memory 21 is reduced to about 1/2 of the conventional one.

Further, a multiplexer control memory 51 (see FIG. 3) having a memory capacity equivalent to that of providing the same number of registers as the number M _{1 of} combinational circuits to be tested by one in place of the conventional multiplexer control register 40 is provided. 2
C) is provided. The data of the cells in the first row having the address C ₁ (= 1) in the multiplexer control memory 51 are all set to 0. That is, all of the output terminals O ₁ ~ O _N multiplexer 36 is not connected to any input terminal I ₁ ~I _q. In other words, the initialization period TOA, TOB, the address C ₁ is designated in the TOC. Address C
The channel number of the scan vector memory 21 used in the test period TA of the circuit 1 is stored in the cells of the second row having ₂ (= 2). Similarly, addresses C ₃ and C ₄
In the cells in the third and fourth rows, channel numbers used in the test periods TB and TC of the circuits 2 and 3 are stored, respectively.

The addresses C _{1 to} C ₄ of the multiplexer control memory 51 to be used in the initialization periods TOA, TOB, TOC and the test periods TA, TB, TC are written in the control data memory 30. That is, although the enable data 31 and the increment data 32 are conventionally written in the control data memory 30, the memory cells are further increased and the addresses C _{1 to} C ₄ (=
1 to 4) 52 are written. These addresses C _1-
The value of C ₄ is supplied to the multiplexer control memory 51 from the terminal CN.
Of the corresponding address C ₁
Set one -C ₄ is, multiplexer 36 by ch number of the data, i.e. scan vector memory 21 rows with the address is to switch control to the same manner as described in the prior art.

Other configurations and operations are the same as those of the conventional apparatus shown in FIG. In the above description, the number of scan data terminals P _k , P _m , and P _n of each combinational circuit of the IC under test is one for each circuit. However, when the scan input data terminal and the output data terminal are provided separately, Individual. Generally, the number may be an arbitrary number (for example, N ₂ ).

Modified Embodiment As shown in FIG.
_{1 to} ID _N are added, and the output terminal V of the test vector memory is
Connect D ₁ to VD _N respectively, a multiplexer 36
Output terminal p ₁ ~p _N of the output terminals O ₁ ~ O _N Direct device
, And the OR gate 38 may be omitted. In this case, i of the multiplexer control memory 51
When the data in the column (i = 1 to N) is 0, the output terminal O _i of the multiplexer 36 and the input terminal ID _i are connected, and the output data of the test vector memory 24 is
It is supplied to the ₁ ~p _N. The other switching connections of the multiplexer 36 are the same as in the embodiment of FIG.

[0024]

According to the present invention, the capacity of the scan vector memory 21 for storing the scan control data and scan data supplied to the IC under test is N ₂ (1 in this embodiment), which is much smaller than the conventional scan data. ) Channels, so it can be reduced to almost half of the conventional one.

In the present invention, although the capacities of the multiplexer control memory 51 and the control data memory 30 are increased as compared with the prior art, the former number of columns N and the latter number of cells in the address direction are different from those of the scan vector memory 21 in the address direction. Since it is a very small value such as several tenths to several hundredths of the capacity, it hardly causes a problem compared to the memory capacity of the scan vector memory 21 which can be reduced. Therefore, it is clear that the present invention can provide a vector generator which is significantly more economical than the conventional one.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of data stored in a control data memory 30, a scan vector memory 21, and a multiplexer control memory 51 of FIG.

FIG. 3 is a block diagram showing a modified embodiment of the present invention.

FIG. 4 is a block diagram showing an example of an IC under test.

FIG. 5 is a block diagram showing a configuration of a logic IC tester.

FIG. 6 is a view showing an example of output data of a test vector generator 300 in FIG. 5;

FIG. 7 is a block diagram of a conventional test vector generator.

8 is a diagram showing an example of data stored in a test vector memory 24, a control data memory 30, and a scan vector memory 21 of FIG. 7, and an example of repeat data output from a sequence controller 25 of FIG. 7;

FIG. 9 is a view showing an example of data written in a multiplexer control register 40 of FIG. 7;

Claims (1)

(57) [Claims] 1. A test vector generator for a logic IC tester, comprising a test vector memory, a control data memory, a scan vector memory, a multiplexer, and a multiplexer control memory, and targeting a scan type logic IC. The test vector memory has N channels respectively corresponding to each terminal of the IC under test, and for each combinational circuit accommodated in the IC, the data of the initialization period is stored in a plurality of rows of cells. The scan vector memory stores the data during the test period in one row of cells. The scan vector memory includes N ₁ channels corresponding to the scan control terminals of the IC, and the circuits (N each).
And a common N ₂ pieces of channels having _two scan data terminal), the are those scan data in the test period of each circuit is sequentially stored, the multiplexer, the terminals of the IC And corresponding N
The output of each of the channels of the scan vector memory is input during the test period, and is output to any of the N output terminals. It has a plurality of addresses corresponding to the respective circuits, and stores a channel number of the scan vector memory to be output to each output terminal of the multiplexer for each of the addresses, and controls the multiplexer by the data. A test vector generator for a logic IC tester, wherein the control data memory stores address data to be supplied to the multiplexer control memory.