JPH04289472A - Test vector generator for logical ic tester - Google Patents

Abstract

PURPOSE:To economize an apparatus by reducing the capacity of a scanning vector memory storing the scanning control data and scanning data supplied to an IC to be tested. CONSTITUTION:A scanning vector memory 21 has N1 channels corresponding to N1 scanning control terminals of an IC to be tested and N2 channels common to respective circuits respectively having N2 scanning data terminals and successively stores the scanning data during the test period of the respective circuits. During the test period, the outputs of the respective channels of the memory 21 are inputted to a muliplexer 36 and selected so as to be changed over by a multiplexer control memory 51 to be outputted to N output terminals P1-PN of an apparatus. In this apparatus, the capacity of the memory 51 or a control data memory 30 is increased but the increase quantity thereof is far small as compared with the reducible capacity of the memory 21. Therefore, large economization can be achieved.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a test vector generator (test pattern generator) used in a logic integrated circuit (hereinafter referred to as logic IC or simply IC) testing machine, and in particular to a scan method (serial input/output data). The present invention relates to an economical construction of a test vector generator for a tester intended for logic ICs (using data).

0002

2. Description of the Related Art An example of an IC under test 100 targeted by this type of test vector generator is shown in FIG. 4, and will be briefly described. In this example, combinational logic circuits (hereinafter referred to as combinational circuits or circuits) 1, 2, and 3 are housed in one IC package. Shift registers 4 and 5 are provided on the input side and output side of the combinational circuit 1, respectively. Similarly, shift registers 6, 7 or 8, 9 are provided on the input and output sides of combinational circuits 2, 3, respectively. The shift registers 4, 6, and 8 on the input side have parallel input terminal groups IA, IB, and IC, and the shift register 5 on the output side
, 7, and 9 are connected to parallel output terminal groups 0A, 0B, and 0C, respectively. On the other hand, input/output terminals Pk for scanning (that is, for serial data) correspond to combinational circuits 1, 2, and 3.
, Pm, and Pn are provided, and are connected to shift registers 4, 5 via input/output switching circuits 11, 12, and 13, respectively;
Connected to serial data input or output terminals 6, 7; 8, 9. Further, scan control terminals P1, P2, and P3 are provided in common to each combinational circuit, and are connected to shift registers 4 to 9.

In the logic IC tester 200, as shown in FIG.
, p2 ..., pN are the shaping, comparison, and driver circuits 400
The input/output terminals P1 and P of the IC under test 100 are connected via
2..., PN, respectively. The shaping, comparison, and driver circuit 400 includes a waveform shaping circuit, a logic comparison circuit, a voltage comparison circuit, a driver circuit, etc., but since these are not directly related to the present invention, detailed explanations will be omitted. The test vector generator 300 outputs H or L logic level data (referred to as a test vector) corresponding to logic "1" or "0".

A block diagram of a conventional test vector generator 300 is shown in FIG. Figure 6 shows an example of a test vector, with pin numbers 1, 2,..., N taken in the horizontal direction, and binary data output over time corresponding to each pin number in the vertical direction. be. After the initialization period (preparation period) TOA, there is a test period TA for combinational circuit 1.
, and thereafter, TOB, TB, TOC, and TC periods are sequentially provided.

Pin p1 of the test vector generator 300,
p2 and p3 correspond to the scan control terminals P1, P2, and P3 of the IC under test 100 shown in FIG. handle. During the test period TA of the combinational circuit 1, 8-bit scan control data is output to pins p1, p2, and p3, respectively. 8 for pin pk
As bit scan data, 8 consecutive bits of logic 0 data are output to pins pm and pn, respectively. Parallel data pin between p3 and pk and from Pn to PN, pin between pk and pm, p
To the pin between m and pn (hereinafter referred to as parallel data pin, etc.), predetermined data that is 8 consecutive bits of logic 1 or 0 is output so as not to adversely affect the test using scan data.

During the test period TB of the combinational circuit 2, 8-bit serial data is output to the scan data terminal pm, and 8 bits of continuous logic 0 data are output to the scan data terminals pk and pn. The data of other terminals are the same as in the case of combinational circuit 1. During the test period TC of the combinational circuit 3, 6-bit data is output to each terminal, and the scan data terminal pn
6-bit serial data is output to terminals pn and pm.
6 consecutive bits of logic 0 data are output. The data for other pins is the same as above.

Although the number of bits of the serial data during the test period for each combinational circuit is 8 or 6, it is generally data with a large number of bits, such as 256 bits. Although the number of scan control terminals and scan data terminals is three each, the total number of these terminals is generally a large value such as 16, 32, or 64, for example. Test period T given to scan control terminals p1, p2, p3 and scan data terminals pk, pm, pn
Data DA, DB, DC, . . . in A, TB, TC, . . . are written into the scan vector memory 21 as shown in FIG. 8D. The column number of scan vector memory 21 is called channel number 22. The number of bits in the vertical direction (address direction) can reach several megabits if it is large.

Data other than the scan data DA, DB, DC, etc. written in the scan vector memory 21 is shown in FIG.
It is written into the test vector memory 24 as shown in A. That is, the data in the test vector memory 24 includes data in the initialization periods TOA, TOB, TOC, etc., and data to be applied to terminals for parallel data, etc. in the test periods TA, TB, TC, etc. of each circuit (1 or 0 during the test period). does not change). Furthermore, since the data given to the scan control terminals p1, p2, p3 and the scan data terminals pk, pm, pn during the test periods TA, TB, TC, etc. are stored in the scan data memory 21, these terminals p1, p2, p3, pk,
All 0s are written into the cells of the test vector memory 24 corresponding to pm and pn.

In the test vector memory 24, data during the test periods TA, TB, TC, etc. of each circuit are stored in one row of memory cells each, so when actually supplied to the IC under test, , these data are T
It is necessary to repeatedly output 8 bits for A and TB and 6 bits for TC, and this is done under the control of the sequence control circuit 25. That is, in FIG.
Addresses of rows of the test vector memory 24 to be simultaneously output are sequentially inputted from the address register 26. Address register 26 is controlled by sequence control circuit 25.

During the test period TA (eight time slots) of the circuit 1, it is necessary to output the test data DA (FIG. 8D) of the scan data memory 21, and an address signal is given from the address counter 28. An increment signal that becomes logic 1 during the test period TA is applied from the control data memory 30 to the increment input terminal INC of the address counter 28, during which the address counter 28 counts the clock CLK and transfers the counted value to the scan vector memory 2. Supplied to the address input terminal of An initial value is set in the address counter 28 by the sequence control circuit 25 as necessary.

An address signal is supplied from an address register 26 to an address input terminal of the control data memory 30. Enable data 31 and increment data 32 are written into the control data memory 30, as shown in FIG. 8C. That is, the initialization periods TOA, TOB, TO
Addresses B1 to B4, B6 to B9 corresponding to C
, B11 to B14 contain data of 0, 0, and addresses B5, 0 corresponding to the test periods TA, TB, and TC, respectively.
Data 1 and 1 are written in B10 and B15, respectively. 1 continuously from the control data memory 30 during the test period.
Enable data 31 and increment data 32 are outputted from enable terminal E and increment terminal INC, respectively, and supplied to one input terminal of AND gate 34 and increment terminal INC of address counter 28.

Output data of scan vector memory 21 (
scan control data and scan data) are output from output terminals SD1 to SDq and applied to the other input terminal of AND gate 34. The output of the AND gate 34 is applied to input terminals I1 to Iq of a multiplexer 36. The output terminals O1 to ON of the multiplexer 36 are applied to one input terminal of N OR gates 38, and the data of the output terminals VD1 to VDN of the test vector memory 24 are input to the other input terminals, respectively. The output of the OR gate 38 is the test vector generator 30
0 output terminals p1 to pN, respectively.

Multiplexer 36 is switched and controlled by data in multiplexer control register 40. As shown in FIG. control register 40
has been written in advance to the memory cell ri (i=1 to N). Input terminal I to multiplexer output terminal Oi
1 to Iq are not connected, that is, when the data in the scan vector memory is not used, data 0 is written to the memory cell ri. In FIG. 9, in the multiplexer 36, O1 -I1, O2 -I2
, O3 - I3 are connected, O4 , O5 ...Ok
-1 is not connected to any input terminal, and OK -
Data is shown when connecting I4, Om-I5, and On-I6. Multiplexer 36 is switched and controlled by multiplexer control register 40.

[0014]

[Problems to be Solved by the Invention] In the conventional apparatus, for example, in the case of FIG.
Test data for combinational circuits 1, 2, and 3 are stored in channel 6, respectively. However, if you look closely, the test data for the 4ch circuit 1 is written to cells at addresses a1 to a8, and all data in cells after a9 are set to 0. Also, the test data for circuit 2 of 5ch is at address a9.
Written to cell ~a16, all other cells are 0
It is said that Further, the test data for the 6ch circuit 3 is written to the cells at addresses a17 to a22, and the other cells are set to 0.

[0015] As described above, only about 1/3 of the memory capacity of 4 to 6 channels is effectively used. In actual equipment, the number of test data storage channels ranges from several to several tens.
Since there are many memory cells, and the length in the address direction can reach several megabits if the length is long, the memory area that is wasted becomes extremely large. The object of the present invention is to solve these conventional drawbacks and to make the device more economical.

[0016]

[Means for Solving the Problems] The present invention provides a logic I/O device for a scan type logic IC, which includes a test vector memory, a control data memory, a scan vector memory, a multiplexer, and a multiplexer control memory.
This is a test vector generator for C test machine. The test vector memory has N vectors corresponding to each terminal of the IC under test.
For each combinational circuit housed in the IC, data for an initialization period is stored in multiple rows of cells, and then data for a test period is stored in one row of cells. .

[0017] The scan vector memory includes N1 channels corresponding to scan control terminals of the IC;
N2 channels common to each of the circuits (each having N2 scan data terminals), and scan data of each circuit during the test period is sequentially stored. The multiplexer has N output terminals corresponding to each terminal of the IC, and during the test period, inputs the output of each channel of the scan vector memory and selects any one of the N output terminals. It outputs the following information:

The multiplexer control memory has a plurality of addresses corresponding to each of the circuits, and for each address, the channel number of the scan vector memory to be output to each output terminal of the multiplexer is stored. The multiplexer is controlled by data. The control data memory stores address data to be supplied to the multiplexer control memory.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is shown in FIG. 1, in which parts corresponding to those in FIG. 7 are designated by the same reference numerals and redundant explanation will be omitted. In this invention, the number of channels for storing test data of each circuit in the scan vector memory 21 is, for example, only 4 channels, and as shown in FIG. 2B, the channels that conventionally stored 0 are abolished. As a result, the channel capacity q of the memory 21 is reduced to approximately 1/2 of that of the conventional memory.

In addition, the number M1 of combinational circuits to be tested instead of the conventional multiplexer control register 40 is
A multiplexer control memory 51 (FIG. 2C) is provided which has the same memory capacity as if one more registers 40 were provided. The data of the cells in the first row having the address C1 (=1) of the multiplexer control memory 51 are all set to 0. In other words, all output terminals O1 to ON of the multiplexer 36 are connected to any input terminals I1 to I
It is not connected to q either. That is, the initialization period TOA, TO
This address C1 is specified in B and TOC. The cell in the second row with address C2 (=2) has circuit 1
The channel number of the scan vector memory 21 used during the test period TA is stored. Similarly, the cells in the third and fourth rows of addresses C3 and C4 have circuits 2 and 4.
, 3 are stored, respectively, to be used during test periods TB and TC.

Addresses C1 to C4 of the multiplexer control memory 51 to be used during the initialization periods TOA, TOB, and TOC and during each test period TA, TB, and TC are written into the control data memory 30. That is, conventionally, enable data 31 and increment data 32 were written in the control data memory 30, but the number of memory cells is further increased, and the addresses C1 to C used are
4 (=1 to 4) 52 is written. The values of these addresses C1 to C4 are input from the terminal CN to the address input terminal of the multiplexer control memory 51, one of the corresponding addresses C1 to C4 is set, and the data of the row having that address, that is, the channel of the scan vector memory 21 Depending on the number, the multiplexer 36 is switched in the same manner as described in the conventional example.

Other configurations and operations are the same as those of the conventional device shown in FIG. 7, so explanations will be omitted. In the explanation so far, the scan data terminal Pk of each combinational circuit of the IC under test is
, Pm, and Pn are set to one per circuit, but if the scan input data terminal and output data terminal are provided separately, the number becomes two. In general, the number may be any number (for example, N2).

Modified Embodiment As shown in FIG. 3, the multiplexer 36 has an input terminal ID
1 to IDN are connected to the output terminals VD1 to VDN of the test vector memory, respectively, and the output terminals O1 to ON of the multiplexer 36 are directly connected to the output terminals p1 to pN of the device, respectively.
may be omitted. In this case, when the data in the i column (i=1 to N) of the multiplexer control memory 51 is 0, the output terminal Oi of the multiplexer 36 and the input terminal I
Di is connected to the test vector memory 24, and output data of the test vector memory 24 is supplied to output terminals p1 to pN, respectively. The other switching connections of multiplexer 36 are similar to the embodiment of FIG.

[0024]

According to the present invention, the capacity of the scan vector memory 21 for storing scan control data and scan data supplied to the IC under test is N2 (1 in the embodiment), which is much smaller than conventional scan data. ), it can be reduced to about half of the conventional size.

In the present invention, although the capacity of the multiplexer control memory 51 and the control data memory 30 is increased compared to the conventional one, the number of columns N of the former and the number of cells in the address direction of the latter are determined by the number of cells in the address direction of the scan vector memory 21. Since it is an extremely small value of several tenths to several hundredths of the capacity, it is hardly a problem compared to the memory capacity that can be reduced in the scan vector memory 21. Therefore, it is clear that the present invention can provide a vector generator that is much more economical than the prior art.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention.

FIG. 2 is a diagram showing an example of data stored in control data memory 30, scan vector memory 21, and multiplexer control memory 51 in FIG. 1;

FIG. 3 is a block diagram showing a modified embodiment of the invention.

FIG. 4 is a block diagram showing an example of an IC under test.

FIG. 5 is a block diagram showing the configuration of a logic IC tester.

6 is a diagram showing an example of output data of the test vector generator 300 of FIG. 5. FIG.

FIG. 7 is a block diagram of a conventional test vector generator.

8 is a diagram showing an example of data stored in the test vector memory 24, control data memory 30, and scan vector memory 21 of FIG. 7, and repeat data output from the sequence controller 25 of FIG. 7;

9 is a diagram showing an example of data written to the multiplexer control register 40 of FIG. 7. FIG.

Claims (1)

[Claims] Claim 1: A test vector memory, a control data memory, a scan vector memory, a multiplexer,
A test vector generator for a logic IC tester targeting a scan-type logic IC, comprising a multiplexer control memory, wherein the test vector memory
has N channels corresponding to each terminal of
For each combinational circuit accommodated in the IC, data for an initialization period is stored in multiple rows of cells, and then data for a test period is stored in one row of cells, and the scan vector memory includes: N1 channels corresponding to the scan control terminals of the IC, and N2 channels common to each of the circuits (each having N2 scan data terminals).
channels, in which scan data of each circuit during the test period is sequentially stored;
The multiplexer has N output terminals corresponding to each terminal of the IC, and during the test period,
The output of each channel of the scan vector memory is inputted and outputted to one of the N output terminals, and the multiplexer control memory has a plurality of addresses corresponding to each of the circuits. A channel number of the scan vector memory to be output to each output terminal of the multiplexer is stored for each address, and the multiplexer is controlled by these data, and the control data memory is connected to the multiplexer control memory. A test vector generator for a logic IC tester, characterized in that it stores address data to be supplied.